人工智能芯片以及用于人工智能芯片的测试访问方法
By combining the JTAG interface and AMBA bus test access method in the AI chip, and using TDR and synchronous conversion circuits to achieve signal synchronization and transmission, the problem of increased circuit area during AI chip testing is solved, and the circuit area is reduced.
CN121997863BActive Publication Date: 2026-07-17SHANGHAI BIREN TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2026-04-10
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
When existing AI chips need to be tested via the JTAG interface after tape-out, the circuit area of the on-chip functional modules increases, resulting in an increase in the overall chip area.
Method used
The test access method combines the JTAG interface and the AMBA bus. The control state is stored and recorded by the TDR of the test driver module, and the signal synchronization and transmission are realized by the synchronous conversion circuit. This reduces the JTAG logic of the on-chip functional modules and uses the AMBA bus for test access.
Benefits of technology
The circuit area of the AI chip was reduced, and the circuit area of the on-chip functional modules was also reduced, thereby reducing the overall chip area.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN121997863B_ABST
Abstract
本公开涉及人工智能芯片以及用于人工智能芯片的测试访问方法。基于本申请，人工智能芯片的片内功能模块可以具有控制逻辑比JTAG逻辑简化的同步转换电路，该同步转换电路的转换控制器可以基于由外部主机维护的控制状态，控制外部主机通过JTAG接口写入的测试信号依据AMBA总线的总线时钟向该同步转换电路的信号同步寄存器的信号同步，并且还可以控制信号同步寄存器中的测试信号通过人工智能芯片中的AMBA总线向功能寄存器的数据传输。因此，人工智能芯片的片内功能模块可以不需要具有JTAG逻辑，从而有助于减小片内功能模块的电路面积，进而有助于减小人工智能芯片的电路面积。
Need to check novelty before this filing date? Find Prior Art