高加速应力测试载板的器件布局方法、装置及电子设备
By automating the determination and adjustment of the pin end point coordinates of the chip under test, the device layout of the high-acceleration stress test carrier board is realized, solving the problems of time-consuming and error-prone manual layout, and ensuring the standardized arrangement and efficient layout of devices on the circuit board.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JIANG SHAN GIGA FORCE ELECTRONICS CO LTD
- Filing Date
- 2026-04-08
- Publication Date
- 2026-07-17
AI Technical Summary
In the existing technology, the manual placement of devices on high-accelerated stress test substrates is time-consuming and prone to errors, especially in the high-density testing of ball grid array packaged chips, where device placement efficiency is low and misalignment or omissions are likely to occur.
By determining the target pin lines of the chip under test, determining the initial coordinates based on the end point coordinates, and performing grouping and offset adjustments, the device layout is automated, ensuring that the devices present a matrix-like stepped array with standardized spacing on the circuit board.
It achieves efficient and accurate component placement, avoiding the time-consuming and error-prone process of manual placement, and ensuring that components are arranged in a standardized manner on the circuit board to meet manufacturing requirements.
Smart Images
Figure CN121997879B_ABST