Chip power consumption control methods, devices, chips, network interface cards, equipment, media, and software products

Abstract

This application relates to a chip power consumption control method, apparatus, chip, network interface card, device, medium, and program product. The method includes: acquiring network traffic characteristics of at least one dimension of the chip; generating a hardware resource activation strategy based on the network traffic characteristics, including: determining the network traffic processing hardware corresponding to the network traffic characteristics; obtaining the traffic demand based on the network traffic characteristics, and obtaining the activation level of the network traffic processing hardware based on the traffic demand, using the activation level of the network traffic processing hardware as the hardware resource activation strategy; and controlling the power consumption of at least one network traffic processing hardware of the chip based on the hardware resource activation strategy. This method enables dynamic adjustment of chip hardware resources and power consumption status based on real-time network traffic characteristics.

Description

Technical Field

[0001] This application relates to the field of network chip technology, and in particular to a chip power consumption control method, apparatus, chip, network interface card, device, medium, and program product. Background Technology

[0002] With the development of chip technology, controlling chip power consumption has become particularly important.

[0003] In traditional technologies, chip power consumption can be controlled through hardware static optimization and dynamic adjustment techniques.

[0004] Hardware static optimization techniques include process upgrades and low-leakage transistor design. Process upgrades, by adopting more advanced processes (such as upgrading from 14nm to 7nm / 5nm), reduce transistor leakage current and switching power consumption (power consumption reduction of 30%-50% under the same computing power). The downside is a sharp increase in cost, while the proportion of static power consumption actually increases. Low-leakage transistor design uses high-threshold voltage (High-Vth) transistors to reduce leakage current during idle periods (static power consumption can be reduced by 40%). However, transistor switching speed is reduced by 15%-20%, leading to performance loss in high-frequency scenarios; it cannot dynamically adapt to changes in flow rate, requiring switching to low-threshold voltage (Low-Vth) transistors under high loads, with switching delays reaching hundreds of nanoseconds, making it unsuitable for sudden flow surges.

[0005] Dynamic adjustment technologies include traditional DVFS (Dynamic Voltage and Frequency Scaling), clock gating, and port-level sleep. Traditional DVFS adjusts the voltage / frequency based on the overall chip load (e.g., PPU utilization), reducing it from 1.0V / 1GHz to 0.8V / 500MHz. Its drawbacks include: adjustment based on "global average load," resulting in lag (response time ≥100μs), inability to handle microsecond-level burst traffic, and potential performance jitter (latency fluctuation ≥50μs). Clock gating disables the clock signal for idle modules (e.g., disabling the PPU clock when there are no packets), reducing dynamic power consumption. Its drawbacks include: while suppressing dynamic power consumption, it is ineffective against static leakage power (limited optimization effect in scenarios where leakage accounts for more than 50%); clock on / off introduces "glitch power," which can increase power consumption by 10%~15% with frequent switching. Port-level sleep enters a low-power sleep mode (disabling part of the PHY circuitry) when there is no traffic, and wakes up when traffic is detected. The disadvantages are: long sleep / wake cycle (≥10ms), which cannot adapt to the microsecond-level burst traffic of 5G base stations and data centers (wake-up delay leads to first packet loss rate ≥1%).

[0006] In summary, there is an urgent need for a low-power solution that can dynamically adjust chip hardware resources and power consumption based on real-time network traffic characteristics. Summary of the Invention

[0007] Therefore, it is necessary to provide a chip power consumption control method, device, chip, network interface card, equipment, medium, and program product that can dynamically adjust the chip hardware resources and power consumption status based on real-time network traffic characteristics to address the above-mentioned technical problems.

[0008] In a first aspect, this application provides a chip power consumption control method, the method comprising:

[0009] Obtain network traffic characteristics in at least one dimension from the collected chip;

[0010] A hardware resource activation strategy is generated based on the network traffic characteristics.

[0011] Power consumption control is performed on at least one network traffic processing hardware of the chip based on the hardware resource activation strategy. In one embodiment, generating the hardware resource activation strategy based on the network traffic characteristics includes:

[0012] Determine the network traffic processing hardware corresponding to the network traffic characteristics;

[0013] Based on the network traffic characteristics, the traffic demand is obtained, and based on the traffic demand, the hardware resource activation strategy corresponding to the network traffic processing hardware is obtained. The hardware resource activation strategy includes the activation amount of the network traffic processing hardware.

[0014] In one embodiment, the network traffic characteristics include at least one of port traffic characteristics, interactive traffic characteristics between source and destination ports, service traffic characteristics, and burst traffic characteristics; the network traffic processing hardware for determining the network traffic characteristics includes:

[0015] At least one of the following is identified as the network traffic processing hardware: the port, the switching structure module, the packet processing unit, and the cache module corresponding to the network traffic characteristics.

[0016] In one embodiment, obtaining the traffic demand based on the network traffic characteristics and obtaining the hardware resource activation strategy corresponding to the network traffic processing hardware based on the traffic demand includes:

[0017] When the network traffic processing hardware includes ports, a traffic demand is generated based on at least one of the port instantaneous bandwidth and the duration of no traffic, and at least one of the rate adjustment strategy of the port physical layer and the media access control layer of the chip and the hierarchical sleep strategy of the port physical layer and the media access control layer of the chip is obtained based on the traffic demand.

[0018] When the network traffic processing hardware includes a switching structure module, a traffic demand is generated based on the corresponding link bandwidth ratio of each source port and each destination port, and a hardware resource activation strategy is generated based on the traffic demand to close idle links and / or reduce the clock frequency. The idle links are links whose corresponding link bandwidth ratio of each source port and each destination port is less than the first bandwidth ratio.

[0019] When the network traffic processing hardware includes a packet processing unit, a traffic demand is generated based on at least one of service priority and packet processing complexity, and at least one of a hardware resource activation strategy for service allocation and a hardware resource activation strategy for service processing path is generated based on the traffic demand.

[0020] When the network traffic processing hardware includes a caching module, the traffic demand is obtained by predicting the caching demand in the future time period based on the traffic burst parameters, and the number of cache activations is generated based on the traffic demand to obtain a hardware resource activation strategy.

[0021] In one embodiment, the network traffic processing hardware includes a port;

[0022] The power consumption control of at least one network traffic processing hardware of the chip based on the hardware resource activation strategy includes:

[0023] If the hardware resource activation strategy includes a rate adjustment strategy, adjust the rate at which the port sends network traffic.

[0024] When the hardware resource activation strategy includes a hierarchical sleep strategy, the functional modules in the port physical layer other than the preamble detection module, and the functional modules in the media access control layer other than the wake-up trigger module are managed.

[0025] In one embodiment, the rate adjustment strategy for the port physical layer and media access control layer of the chip based on the traffic demand includes:

[0026] When the instantaneous bandwidth of the port is continuously lower than the first target threshold for a preset duration, a rate adjustment strategy for rate degradation of the port physical layer and media access control layer of the chip is generated.

[0027] When the instantaneous bandwidth of the port is continuously greater than or equal to the second target threshold for a preset duration, a rate adjustment strategy for rate upgrade of the port physical layer and media access control layer of the chip is generated, wherein the first target threshold is less than the second target threshold, and both the first target threshold and the second target threshold are determined based on the current rate of the port.

[0028] In one embodiment, the network traffic processing hardware includes a switching structure module;

[0029] The power consumption control of at least one network traffic processing hardware of the chip based on the hardware resource activation strategy includes:

[0030] When the hardware resource activation strategy includes shutting down idle links, the clock drive of the link is turned off and the power is cut off through the switching structure module;

[0031] When the hardware resource activation strategy includes reducing the clock frequency, the clock frequency of the corresponding link is reduced through the switching structure module;

[0032] When the hardware resource activation strategy includes shutting down idle links or reducing the clock frequency, the routing information corresponding to the activated links is stored, and the idle links are marked as invalid.

[0033] In one embodiment, the network traffic processing hardware includes a packet processing unit;

[0034] The power consumption control of at least one network traffic processing hardware of the chip based on the hardware resource activation strategy includes:

[0035] When the hardware resource activation strategy includes a hardware resource activation strategy for service allocation, services with different service priorities are processed through different core groups of the chip.

[0036] When the hardware resource activation strategy includes a hardware resource activation strategy for service processing paths, services with different packet processing complexities are processed based on the service processing paths.

[0037] In one embodiment, the chip includes a first core group and a second core group; the hardware resource activation strategy for generating service allocation based on traffic demand includes:

[0038] The highest priority tasks are assigned to the first core group for processing.

[0039] In the presence of second-priority services other than first-priority services, the second core group is dynamically activated via clock gating, and the second-priority services are allocated to the second core group.

[0040] If there are no second-priority services other than the first-priority service, turn off the clock of the second core group.

[0041] In one embodiment, the network traffic processing hardware includes a caching module, and the caching module includes several storage blocks that can be independently hibernated;

[0042] The power consumption control of at least one network traffic processing hardware of the chip based on the hardware resource activation strategy includes:

[0043] The corresponding storage block in the cache module is activated according to the number of cache activations.

[0044] In one embodiment, generating the cache activation quantity based on the traffic demand includes:

[0045] The cache activation quantity is generated based on the aforementioned cache requirements and the first redundancy ratio.

[0046] Activating the corresponding storage block in the cache module according to the number of cache activations includes:

[0047] If the actual cache usage in the cache module exceeds the target required capacity, the number of activations is increased, wherein the target required capacity is determined based on the cache requirement and a second redundancy ratio, and the second redundancy ratio is greater than the first redundancy ratio.

[0048] Secondly, this application also provides a chip power consumption control device, the device comprising:

[0049] The network traffic feature acquisition module is used to acquire network traffic features of at least one dimension of the collected chip.

[0050] A hardware resource activation strategy generation module is used to generate a hardware resource activation strategy based on the network traffic characteristics.

[0051] A low-power module is used to control the power consumption of at least one network traffic processing hardware of the chip based on the hardware resource activation strategy.

[0052] Thirdly, this application also provides a chip, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in any of the above embodiments.

[0053] Fourthly, this application also provides a network interface card, including a chip as described in any of the above embodiments and multiple interfaces, wherein the chip processes data or communicates externally through the interfaces.

[0054] Fifthly, this application also provides a computer device including the network interface card described in any of the above embodiments, wherein the network interface card is used for processing data or external communication.

[0055] Sixthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the above embodiments.

[0056] In a seventh aspect, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in any of the above embodiments.

[0057] The aforementioned chip power consumption control method, apparatus, chip, network interface card, device, medium, and program product acquire at least one dimension of network traffic characteristics of the collected chip; generate a hardware resource activation strategy based on the network traffic characteristics; and perform power consumption control on at least one network traffic processing hardware of the chip based on the hardware resource activation strategy. This allows for granular control of power consumption for each network traffic processing hardware based on its network traffic characteristics. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is an application environment diagram of the chip power consumption control method in one embodiment;

[0060] Figure 2 This is a flowchart illustrating a chip power consumption control method in one embodiment;

[0061] Figure 3 Here is a flowchart of dynamic port rate adjustment in one embodiment;

[0062] Figure 4 Here is a flowchart of the predictive management process for the cache storage block (Bank) in one embodiment;

[0063] Figure 5 This is a structural block diagram of a chip power consumption control device in one embodiment;

[0064] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0066] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0067] The low-power control method for chips provided in this application can be applied to, for example... Figure 1 In the application environment shown, the traffic monitoring and judgment subsystem communicates with the low-power module. The traffic monitoring and judgment subsystem includes a network traffic feature acquisition module and a hardware resource activation strategy generation module. The low-power module controls the power consumption of at least one network traffic processing hardware component of the chip according to the hardware resource activation strategy output by the traffic monitoring and judgment subsystem. The network traffic processing hardware includes at least one of a port, a switching structure module, a packet processing unit, and a buffer module. The clock and power management unit (CPMU) can adjust the voltage (0.7V-1.0V) and clock frequency (125MHz-1GHz) of each network traffic processing hardware component. In other embodiments, the voltage and clock frequency ranges can be other values, which are not specifically limited here.

[0068] The network traffic feature acquisition module includes a port layer acquisition unit for port traffic features, a switching layer acquisition unit for acquiring interactive traffic features between source and destination ports, a service layer acquisition unit for acquiring service traffic features, and a burst layer acquisition unit for acquiring burst traffic features.

[0069] The hardware resource activation strategy generation module can be implemented using a RISC-5 core, and all parameters can be adjusted in real time according to the algorithm.

[0070] The low-power module includes a port policy generation unit that generates port power control strategies based on port traffic characteristics, a switching policy generation unit that generates low-power strategies for the switching structure module based on the interaction traffic characteristics of the source port and the destination port, a service policy generation unit that generates service low-power strategies based on service traffic characteristics, and a burst policy generation unit that generates burst low-power strategies based on burst traffic characteristics.

[0071] In one exemplary embodiment, such as Figure 2 As shown, a low-power control method for a chip is provided, including steps 202 to 206. Wherein:

[0072] S202: Acquire network traffic characteristics of at least one dimension of the collected chip.

[0073] Among them, network traffic characteristics include at least one of port traffic characteristics, interactive traffic characteristics between source and destination ports, service traffic characteristics, and burst traffic characteristics.

[0074] In this embodiment, the network traffic feature acquisition module includes a port-layer acquisition unit for collecting port traffic features, an interaction-layer acquisition unit for collecting the interaction traffic features between source and destination ports, a service-layer acquisition unit for collecting service traffic features, and a burst-layer acquisition unit for collecting burst traffic features. Specifically:

[0075] Port layer acquisition unit: The port traffic characteristics are acquired through a built-in traffic counter. The port traffic characteristics include at least one of the following: instantaneous port bandwidth (accuracy ±2%), duration of no traffic (resolution 100μs), and frame length distribution (64B / 128B / 1518B ratio). The port traffic characteristics are updated once every 1ms. In other embodiments, the update frequency of the port traffic characteristics can be other periods, which are not specifically limited here.

[0076] The switching layer acquisition unit generates the interaction traffic characteristics between the source port and the destination port through the cross-node monitoring circuit, such as the traffic interaction matrix between the source port and the destination port. Optionally, the interaction matrix can be refreshed once every 5ms. The interaction matrix is ​​used to record the bandwidth ratio of each link.

[0077] The service layer acquisition unit is used to collect service traffic characteristics, such as parsing the DSCP / 802.1p field in the frame header to identify service priorities. Optionally, the service priorities include three levels: EF (Expedited Forwarding), AF (Assured Forwarding), and BE (Best-Effort). In other embodiments, the service priorities can be other than those specified here. The processing complexity is obtained by processing pipelined labeled packets. This processing complexity can include four levels: L2 forwarding, L3 routing, ACL matching, and deep inspection. In other embodiments, the complexity can be other than those specified here.

[0078] The burst layer acquisition unit is used to acquire traffic burst parameters through a sliding window, where the size of the sliding window can be 100ms. In other embodiments, it can also be other values. Burst parameters can include burst period, peak bandwidth, average duration, etc., which are not specifically limited here.

[0079] S204: Generate hardware resource activation strategies based on network traffic characteristics.

[0080] Optionally, in this embodiment, the collected network traffic characteristics are transformed into hardware resource activation strategies based on a preset "traffic-resource" mapping model.

[0081] In some optional embodiments, generating a hardware resource activation strategy based on network traffic characteristics includes: determining the network traffic processing hardware corresponding to the network traffic characteristics; obtaining the traffic demand based on the network traffic characteristics; and obtaining the hardware resource activation strategy corresponding to the network traffic processing hardware based on the traffic demand, wherein the hardware resource activation strategy includes the activation amount of the network traffic processing hardware.

[0082] Different network traffic characteristics correspond to different network traffic processing hardware. In this application, network traffic characteristics include at least one of port traffic characteristics, interactive traffic characteristics between source and destination ports, service traffic characteristics, and burst traffic characteristics. Optionally, determining the network traffic processing hardware corresponding to the network traffic characteristics includes: determining at least one of the port, switching structure module, packet processing unit, and buffer module corresponding to the network traffic characteristics as the network traffic processing hardware.

[0083] The network traffic processing hardware corresponding to port traffic characteristics includes the physical layer and media access control layer of the port; the network traffic processing hardware corresponding to the interaction traffic characteristics of the source port and the destination port includes the link and / or clock frequency of the port; the network traffic processing hardware corresponding to service traffic characteristics includes different core groups of the chip and / or service processing paths; and the network traffic processing hardware corresponding to burst traffic characteristics includes buffers.

[0084] The hardware resource activation strategies include at least one of the following: port rate adjustment strategy, switching link on / off status strategy, packet processing core activation quantity strategy, and cache bank (storage block) activation quantity strategy.

[0085] Specifically, the port rate adjustment strategy is generated based on port traffic characteristics, the switching link switch status strategy is generated based on the interaction traffic characteristics of the source port and the destination port, the packet processing core activation quantity strategy is generated based on service traffic characteristics, and the cache bank (storage block) activation quantity is generated based on burst traffic characteristics.

[0086] After determining the network traffic processing hardware, the system also determines the traffic demand based on network traffic characteristics, and obtains the corresponding hardware resource activation strategy based on the traffic demand.

[0087] In some optional embodiments, the hardware resource activation strategy corresponding to the network traffic processing hardware is obtained based on the traffic demand, including: when the network traffic processing hardware includes ports, generating a traffic demand based on at least one of the instantaneous bandwidth of the port and the duration of no traffic, and obtaining at least one of the rate adjustment strategy of the chip's port physical layer and media access control layer and the hierarchical sleep strategy of the chip's port physical layer and media access control layer based on the traffic demand; when the network traffic processing hardware includes a switching structure module, generating a traffic demand based on the corresponding link bandwidth ratio of each source port and each destination port, and generating a strategy to close idle links and / or based on the traffic demand. Alternatively, a hardware resource activation strategy that reduces clock frequency can be used, where idle links are those whose corresponding link bandwidth ratio for each source port and each destination port is less than the first bandwidth ratio; when the network traffic processing hardware includes a packet processing unit, a traffic demand is generated based on at least one of service priority and packet processing complexity, and at least one of a hardware resource activation strategy for service allocation and a hardware resource activation strategy for service processing paths is generated based on the traffic demand; when the network traffic processing hardware includes a caching module, the traffic demand is obtained by predicting the caching demand in the future time period based on traffic burst parameters, and the number of cache activations is generated based on the traffic demand to obtain the hardware resource activation strategy.

[0088] In some optional embodiments, the port rate policy adjustment strategy includes at least one of a rate adjustment strategy and a tiered sleep strategy. In this embodiment, a traffic demand can be generated based on at least one of the port instantaneous bandwidth and the duration of no traffic. Then, at least one of the rate adjustment strategy and the tiered sleep strategy is obtained based on the traffic demand. For example, when the traffic demand is determined based on the port instantaneous bandwidth, a rate adjustment strategy for the chip's port physical layer and media access control layer can be obtained; when the traffic demand is determined based on the duration of no traffic, at least one of the tiered sleep strategy for the chip's port physical layer and media access control layer can be obtained.

[0089] The switching link on / off status policy includes hardware resource activation policies that disable idle links and / or reduce clock frequency. First, the traffic demand is generated based on the corresponding link bandwidth ratio of each source port and each destination port. Then, based on the traffic demand, the hardware resource activation policy that disables idle links and / or reduces clock frequency is generated. Idle links are those whose corresponding link bandwidth ratio of each source port and each destination port is less than a first bandwidth ratio.

[0090] The core activation quantity strategy for packet processing includes at least one of the hardware resource activation strategy for service allocation and the hardware resource activation strategy for service processing paths. Specifically, the traffic demand can be generated first based on at least one of service priority and packet processing complexity, and then at least one of the hardware resource activation strategies for service allocation and service processing paths can be generated.

[0091] The number of cache banks (storage blocks) enabled includes the number of cache activations. This can be achieved by first predicting cache demand over a future time period based on traffic burst parameters, then generating the number of cache activations based on this demand to determine the hardware resource activation strategy.

[0092] Traffic demand can be the total amount of data that is to be sent, i.e., the global network traffic determined based on network traffic characteristics. Finally, the activation level of network traffic processing hardware is obtained based on the traffic demand; for example, the activation level of network traffic processing hardware is equal to or slightly greater than the traffic demand.

[0093] For details on the generation of traffic demand and corresponding hardware resource activation strategies, please refer to the following text.

[0094] In the above embodiments, a dynamic mapping is established between multi-dimensional traffic parameters such as port bandwidth, service priority, and burst characteristics and hardware resources (port rate, switching link, core, and cache storage block Bank) to achieve a precise match between "resource activation amount and traffic demand amount".

[0095] S206: Power consumption control of at least one network traffic processing hardware of the chip based on hardware resource activation strategy.

[0096] The network traffic processing hardware includes at least one of the following: a port, a switching structure module, a packet processing unit, and a cache module.

[0097] In this application, the power and clock of the chip's ports, switching structure modules, packet processing units, and buffer modules are independently adjusted according to each hardware resource activation strategy to start or stop the corresponding network traffic processing hardware, so that the chip power consumption changes dynamically with traffic characteristics. For example, if the activation level of the network traffic processing hardware corresponding to the hardware resource activation strategy is greater than the current activation level, then some or all of the network traffic processing hardware is turned off. If the activation level of the network traffic processing hardware corresponding to the hardware resource activation strategy is less than the current activation level, then some or all of the network traffic processing hardware is turned on again.

[0098] The aforementioned chip power consumption control method acquires at least one dimension of network traffic characteristics of the chip; generates a hardware resource activation strategy based on the network traffic characteristics; and performs power consumption control on at least one network traffic processing hardware of the chip based on the hardware resource activation strategy. This granularity allows for power consumption control of at least one network traffic processing hardware based on network traffic characteristics.

[0099] In some optional embodiments, the port traffic characteristics include at least one of port instantaneous bandwidth and no-traffic duration; the network traffic processing hardware includes a port; power consumption control is performed on at least one network traffic processing hardware of the chip based on a hardware resource activation strategy, including: adjusting the rate at which the port sends network traffic when the hardware resource activation strategy includes a rate adjustment strategy; and managing functional modules in the port physical layer other than the preamble detection module, and functional modules in the media access control layer other than the wake-up trigger module, when the hardware resource activation strategy includes a hierarchical sleep strategy.

[0100] The port includes the physical layer and the media access control layer. The hardware resource activation policy of the port is the policy that controls the physical layer and the media access control layer of the port. This policy includes rate adjustment policy and hierarchical sleep policy.

[0101] The rate adjustment strategy is used to adjust the rate at which the port sends network traffic. The port supports Dynamic Rate Scaling (DRS): the physical layer PHY supports multi-rate switching between 100G, 50G, 25G, and 10G (in other embodiments, the rate can also be other values, which are not specifically limited here). The switching time of the physical layer for rate switching is <5μs, and the current rate is synchronized with the peer device. The negotiation success rate is >99.9%.

[0102] The hierarchical sleep strategy refers to the physical layer PHY being shut down by 90% after a preset period of no traffic, such as 50ms, for example, only the preamble detection module is retained with power consumption <1mW, the media access control layer MAC enters clock gating state, and only the receive FIFO retains the wake-up trigger logic.

[0103] In some optional embodiments, the rate adjustment strategy for the chip's port physical layer and media access control layer is obtained based on the traffic demand, including: generating a rate adjustment strategy for rate degradation of the chip's port physical layer and media access control layer when the port instantaneous bandwidth is continuously lower than a first target threshold for a preset duration; and generating a rate adjustment strategy for rate upgrade of the chip's port physical layer and media access control layer when the port instantaneous bandwidth is continuously greater than or equal to a second target threshold for a preset duration, wherein the first target threshold is less than the second target threshold, and both the first target threshold and the second target threshold are determined based on the current rate of the port.

[0104] For ease of understanding, combined with Figure 3 As shown, Figure 3 This is a flowchart of a port rate dynamic adjustment process in one embodiment, where the port layer updates the instantaneous bandwidth periodically, for example, every 1ms.

[0105] The preset duration can be 3ms, i.e., 3 consecutive cycles. Other values ​​may be used in other embodiments, and no specific limitation is made here. The first target threshold can be 30% of the port's current rate. In other embodiments, the first target threshold can be other values. The second target threshold can be 80% of the port's current rate, wherein the first target threshold is less than the second target threshold, and both the first and second target thresholds are determined based on the port's current rate.

[0106] When the instantaneous bandwidth of a port is continuously less than a first target threshold for a preset duration, a rate adjustment strategy for rate degradation of the chip's port physical layer and media access control layer is generated. For example, if the current rate is 100G, it can be reduced to 50G. When the instantaneous bandwidth of a port is continuously greater than 80% of the current rate, a rate adjustment strategy for rate upgrade of the chip's port physical layer and media access control layer is generated. For example, if the current rate is 50G, it can be reduced to 100G. If the instantaneous bandwidth of a port is continuously greater than or equal to the first target threshold and less than or equal to the second target threshold, a rate adjustment strategy that keeps the current rate unchanged is generated.

[0107] Since higher speeds result in higher power consumption, this embodiment adjusts the speed to reduce power consumption and achieve energy saving.

[0108] In some optional embodiments, the interaction traffic characteristics of the source port and the destination port include the corresponding link bandwidth ratio of each source port and each destination port; the network traffic processing hardware includes a switching structure module; power consumption control of at least one network traffic processing hardware of the chip is performed based on a hardware resource activation strategy, including: when the hardware resource activation strategy includes closing idle links, disabling the clock drive of the link through the switching structure module and cutting off the power supply; when the hardware resource activation strategy includes reducing the clock frequency, reducing the clock frequency of the corresponding link through the switching structure module; when the hardware resource activation strategy includes closing idle links or reducing the clock frequency, storing the routing information corresponding to the activated link and marking the idle link as invalid.

[0109] The interactive traffic characteristics can be implemented through an interactive matrix. The corresponding link bandwidth percentages for each source port and each destination port are recorded in the interactive matrix. The switching link policy is generated based on the corresponding link bandwidth percentages for each source port and each destination port. This switching link policy includes closing idle links and / or reducing the clock frequency. For example, links with a bandwidth percentage less than the first bandwidth percentage in the interactive matrix are marked as "sleepable," that is, marked as idle links; links with a bandwidth percentage greater than or equal to the first bandwidth percentage but less than the second bandwidth percentage are marked as "frequency reduction," that is, reducing the clock frequency; and links with a bandwidth percentage greater than the second bandwidth percentage are marked as "full speed."

[0110] The first bandwidth percentage can be 5%, and the second bandwidth percentage can be 30%. In other embodiments, the first bandwidth percentage and the second bandwidth percentage can be other values, which are not specifically limited here.

[0111] The exchange structure module (Clos / Crossbar) includes:

[0112] Link-level power gating: For "sleepable" links, the power domain is cut off by the power switching transistor (PMOS) (voltage drops from 1.0V to 0V), and the clock drive is turned off at the same time; for "downclocked" links, the clock frequency is reduced from 500MHz to 125MHz (achieved by PLL frequency division, switching time <2μs).

[0113] In addition, the switching structure module also includes a dynamic routing table: it uses SRAM to store the routing information of the currently active links, and marks the routing entries of idle links as "invalid" to avoid the power consumption of invalid lookups.

[0114] In the above embodiments, low-bandwidth links can be shut down based on the bandwidth of each link, thereby reducing power consumption. In addition, the dynamic routing table is updated to reduce the power consumption caused by invalid route lookups.

[0115] In some optional embodiments, the service traffic characteristics include service priority and packet processing complexity, and the network traffic processing hardware includes a packet processing unit; power consumption control of at least one network traffic processing hardware of the chip based on a hardware resource activation strategy includes: when the hardware resource activation strategy includes a hardware resource activation strategy for service allocation, processing services with different service priorities through different core groups of the chip; when the hardware resource activation strategy includes a hardware resource activation strategy for service processing paths, processing services with different packet processing complexities based on the service processing paths.

[0116] Business traffic characteristics include business priority and packet processing complexity.

[0117] Service priority can generate service allocation strategies, assigning different processor cores to different services. Packet processing complexity can generate service processing paths, with different service processing paths corresponding to different power consumption.

[0118] Optionally, the chip includes a first core group and a second core group; a hardware resource activation strategy for service allocation based on traffic demand is generated, including: allocating first-priority services to the first core group for processing; dynamically activating the second core group through clock gating and allocating second-priority services to the second core group when there are second-priority services other than first-priority services; and turning off the clock of the second core group when there are no second-priority services other than first-priority services.

[0119] The first core group P0 and the second core group P1 are obtained by classifying the cores of the chip. Different core groups handle services with different service priorities. For example, high-priority services (EF) are bound to the first core group P0, while medium- and low-priority services (AF / BE) are handled by the second core group P1. The number of P1 cores can be dynamically allocated according to the load of medium- and low-priority services. For example, the service volume of medium- and low-priority services is counted every 2ms (or other values ​​in other embodiments). The dynamic allocation of the second core group P1 can be such that for every 20% increase in load, one more core is activated.

[0120] In the above embodiment, the core grouping architecture is as follows: the first core group P0 runs all-time, handling only EF-level services and control plane protocols (BGP / OSPF), with static power consumption reduced by 50% compared to conventional cores; the second core group P1 is dynamically activated through clock gating, with idle cores having their clocks turned off (leakage power consumption <50μW / core). Through the grouping design of the first core group P0 (low-leakage cores are bound to high-priority cores) and the second core group P1 (dynamically activated and load-adapted), the computing power redundancy power consumption is reduced while ensuring the performance of critical services.

[0121] In addition, regarding adaptive processing paths, low-complexity services (such as L2 passthrough) in this application skip the deep packet inspection (DPI) pipeline and are forwarded through a dedicated hardware accelerator (MAC address lookup + CRC check), reducing the energy consumption per processing cycle by 60%. This allows for different processing paths to be used for services with different processing complexities, thereby reducing power consumption.

[0122] In some optional embodiments, the burst traffic characteristics include traffic burst parameters, the network traffic processing hardware includes a cache module, and the cache module includes several storage blocks that can be independently hibernated; power consumption control of at least one network traffic processing hardware of the chip based on a hardware resource activation strategy includes: activating the corresponding storage block in the cache module according to the number of cache activations.

[0123] In this embodiment, a lightweight LSTM model (parameters are fixed in ROM, computation latency < 100μs; other models may be used in other embodiments, and no specific restrictions are made here) can be used to estimate cache demand for a future time period, such as the next 5ms. Then, based on the cache demand, a cache activation quantity is generated. Optionally, in this application, the activation quantity = cache demand × first redundancy ratio. Optionally, the first redundancy ratio can be 1.1; in other embodiments, it can also be other values. Unused cache storage blocks (Banks) enter a deep sleep state (only retaining data and keeping the capacitors powered) to reduce power consumption.

[0124] In the above embodiments, a hardware-based lightweight LSTM model is used to predict traffic bursts, and a 10% redundancy design is used to activate the cache storage block Bank in advance to solve the problem of packet loss caused by "sleep-wake-up lag", with a prediction accuracy of over 90%.

[0125] In some optional embodiments, generating the cache activation quantity based on the traffic demand includes: generating the cache activation quantity based on the cache demand and a first redundancy ratio; activating the corresponding storage block in the cache module according to the cache activation quantity includes: increasing the activation quantity when the actual cache occupancy in the cache module is greater than the target demand capacity, wherein the target demand capacity is determined based on the cache demand and a second redundancy ratio, and the second redundancy ratio is greater than the first redundancy ratio.

[0126] For ease of understanding, the following is combined Figure 4 As shown, Figure 4The diagram below shows a predictive management flowchart for the cache storage blocks (Banks) in one embodiment. In this embodiment, the SRAM cache is divided into 16 (or other values ​​in other embodiments) independent storage blocks (Banks, each 10MB), and their power supply is independently controlled by the power management unit (PMU). The hibernation storage blocks (Banks) have their main power supply turned off, retaining only the data retention capacitors (Retention Voltage = 0.3V). The data retention time is >100ms, and the wake-up time is <800ns, thereby reducing power consumption.

[0127] If the actual cache usage exceeds the target capacity, the number of activations is increased, for example, by immediately activating one backup bank, and the LSTM model parameters are adjusted through incremental learning (updated every 100 cycles; in other embodiments, these can be different values). If the actual cache usage does not exceed the target capacity, the original number of activations is maintained.

[0128] The target capacity requirement is determined based on the cache requirement and the second redundancy ratio, which is greater than the first redundancy ratio. For example, the second redundancy ratio can be 15%.

[0129] In the above embodiments, the power consumption reduction is significant: during periods of low traffic (such as nighttime in data centers), the total power consumption of the chip is reduced by 40%-65% (static power consumption is reduced by more than 60%), far exceeding existing solutions (10%-20%); through predictive activation (5ms in advance) and fast wake-up (<2μs), the packet loss rate under burst traffic is <0.001%, and the latency jitter is <3μs, meeting the requirements of carrier-grade reliability; it supports a full rate range of 100Mbps-800Gbps, and can be adapted to multiple scenarios such as data centers (high bandwidth and stable traffic), AI intelligent computing (burst traffic), and edge computing (low power consumption requirements); based on the modification of the existing chip architecture (the proportion of new modules is <10%), it is compatible with standards such as IEEE 802.3 (Ethernet) and IEEE 802.1AB (LLDP) without modifying the upper-layer protocol stack.

[0130] To facilitate understanding, a complete embodiment is provided below. The implementation process of this application is described in detail below with reference to typical application scenarios:

[0131] Chip specifications: 8 100G ports, Clos switching architecture, 8-core RISC-5 (4 P0 high priority, 4 P1 low priority, 8MB cache capacity, divided into 16 BANK internal data caches).

[0132] First, initialize the configuration (T=0ms):

[0133] The FADC (Fluidized Adaptive Traffic Detection and Analysis) subsystem loads the following basic parameters: rate switching threshold (30% / 80%), sleep trigger duration (50ms), and LSTM initialization model (trained based on historical traffic).

[0134] P0 core activated (processing EF services), 4 P1 cores activated (default, other values ​​can be used in other embodiments), and 4 cache blocks (basic reserved) activated.

[0135] Low traffic period (port traffic = 20G):

[0136] Traffic monitoring and judgment central subsystem FADC collects data: Port1 bandwidth = 20G (20% < 30% of 100G) for 3 consecutive cycles (3ms). The interaction matrix shows that there is traffic only between Port1 and Port2, and between Port3 and Port4 (accounting for 20%). The business is mainly BE level (accounting for 90%).

[0137] The hardware resource activation strategy generation module generates the following hardware resource activation strategy: Port1 / Port2 / Port3 / Port4 are reduced to 25G, and the physical layer PHY and MAC of the remaining 4 ports are turned off; 1 P1 core is retained (load = 15% < 20%); LSTM predicted cache requirement = 30MB (activate 4 storage blocks); power is turned off for idle switching links; 12 storage blocks are turned off for cache.

[0138] Period of sudden traffic surge (port traffic suddenly increases to 90G):

[0139] Traffic monitoring and judgment central subsystem FADC data collection: Port1 bandwidth = 90G (360% of 25G > 80%), burst peak = 100G, duration prediction = 20ms.

[0140] The hardware resource activation strategy generation module generates the following hardware resource activation strategies: Port1 and Port2 are immediately upgraded to 100G; all switching links are activated and restored to full speed; P1 cores are activated to 4; cache demand prediction = 8MB (activating 16 banks); the standby bank is woken up within 800ns; packet loss rate during the burst period = 0.

[0141] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0142] Based on the same inventive concept, this application also provides a chip power consumption control device for implementing the chip power consumption control method described above. The solution provided by this device is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more chip power consumption control device embodiments provided below can be found in the limitations of the chip power consumption control method described above, and will not be repeated here.

[0143] In one exemplary embodiment, such as Figure 5 As shown, a chip power consumption control device is provided, including: a network traffic feature acquisition module 501, a hardware resource activation strategy generation module 502, and a low-power module 503, wherein:

[0144] The network traffic feature acquisition module 501 is used to acquire network traffic features of at least one dimension of the collected chip.

[0145] The hardware resource activation strategy generation module 502 is used to generate hardware resource activation strategies based on network traffic characteristics.

[0146] The low-power module 503 is used to control the power consumption of at least one network traffic processing hardware of the chip based on a hardware resource activation strategy.

[0147] In some optional embodiments, the hardware resource activation strategy generation module 502 is specifically used to determine the network traffic processing hardware corresponding to the network traffic characteristics; obtain the traffic demand based on the network traffic characteristics, and obtain the activation amount of the network traffic processing hardware based on the traffic demand, and use the activation amount of the network traffic processing hardware as the hardware resource activation strategy.

[0148] In some optional embodiments, network traffic characteristics include at least one of port traffic characteristics, interactive traffic characteristics between source and destination ports, service traffic characteristics, and burst traffic characteristics; the hardware resource activation policy generation module 502 is specifically used to determine at least one of the port, switching structure module, packet processing unit, and cache module corresponding to the network traffic characteristics as network traffic processing hardware.

[0149] In some optional embodiments, the hardware resource activation policy generation module 502 is specifically used to generate a traffic demand based on at least one of the instantaneous bandwidth of the port and the duration of no traffic when the network traffic processing hardware includes ports, and to obtain at least one of the rate adjustment policy of the port physical layer and the media access control layer of the chip and the hierarchical sleep policy of the port physical layer and the media access control layer of the chip based on the traffic demand; when the network traffic processing hardware includes a switching structure module, it generates a traffic demand based on the corresponding link bandwidth ratio of each source port and each destination port, and generates a policy to close idle links and / or reduce the clock frequency based on the traffic demand. The hardware resource activation strategy is as follows: the idle links are links whose corresponding link bandwidth ratios for each source port and each destination port are less than a first bandwidth ratio; when the network traffic processing hardware includes a packet processing unit, a traffic demand is generated based on at least one of service priority and packet processing complexity, and at least one of a hardware resource activation strategy for service allocation and a hardware resource activation strategy for service processing paths is generated based on the traffic demand; when the network traffic processing hardware includes a caching module, the traffic demand is obtained by predicting the caching demand in the future time period based on the traffic burst parameters, and the number of cache activations is generated based on the traffic demand to obtain the hardware resource activation strategy.

[0150] In some alternative embodiments, the network traffic processing hardware includes ports;

[0151] The aforementioned low-power module 503 is specifically used to adjust the rate at which the port sends network traffic when the hardware resource activation strategy includes a rate adjustment strategy; and to manage the functional modules in the physical layer of the port other than the preamble detection module, and the functional modules in the media access control layer other than the wake-up trigger module, when the hardware resource activation strategy includes a hierarchical sleep strategy.

[0152] In some optional embodiments, the hardware resource activation strategy generation module 502 is used to generate a rate adjustment strategy for rate degradation of the chip's port physical layer and media access control layer when the port instantaneous bandwidth is continuously lower than a first target threshold for a preset duration; and to generate a rate adjustment strategy for rate upgrade of the chip's port physical layer and media access control layer when the port instantaneous bandwidth is continuously greater than or equal to a second target threshold for a preset duration, wherein the first target threshold is less than the second target threshold, and both the first target threshold and the second target threshold are determined based on the current rate of the port.

[0153] In some alternative embodiments, the network traffic processing hardware includes a switching infrastructure module;

[0154] The aforementioned low-power module 503 is specifically used to, when the hardware resource activation strategy includes closing idle links, disable the clock drive of the link and cut off the power supply through the switching structure module; when the hardware resource activation strategy includes reducing the clock frequency, reduce the clock frequency of the corresponding link through the switching structure module; and when the hardware resource activation strategy includes closing idle links or reducing the clock frequency, store the routing information corresponding to the activated link and mark the idle link as invalid.

[0155] In some alternative embodiments, the network traffic processing hardware includes a packet processing unit;

[0156] Specifically, the low-power module 503 is used to process services with different service priorities through different core groups of the chip when the hardware resource activation strategy includes a service allocation hardware resource activation strategy; and to process services with different packet processing complexities based on the service processing path when the hardware resource activation strategy includes a service processing path hardware resource activation strategy.

[0157] In some optional embodiments, the chip includes a first core group and a second core group; the low-power module 503 is used to allocate first-priority services to the first core group for processing; when there are second-priority services other than the first priority, the second core group is dynamically activated by clock gating and the second-priority services are allocated to the second core group; when there are no second-priority services other than the first priority, the clock of the second core group is turned off.

[0158] In some alternative embodiments, the network traffic processing hardware includes a caching module, and the caching module includes several independently hibernating storage blocks;

[0159] The aforementioned low-power module 503 is specifically used to activate the corresponding storage block in the cache module according to the number of cache activations.

[0160] In some optional embodiments, the hardware resource activation strategy generation module 502 is used to generate the cache activation quantity based on cache requirements and a first redundancy ratio;

[0161] The aforementioned low-power module 503 is specifically used to increase the number of activated modules when the actual cache usage in the cache module exceeds the target required capacity. The target required capacity is determined based on the cache requirement and the second redundancy ratio, which is greater than the first redundancy ratio.

[0162] Each module in the aforementioned chip power consumption control device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0163] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 6 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a chip power consumption control method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0164] Those skilled in the art will understand that Figure 6The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0165] In one exemplary embodiment, a chip is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.

[0166] In one exemplary embodiment, a network interface card is provided, including a chip as described in any of the above embodiments and multiple interfaces, through which the chip processes data or communicates externally.

[0167] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0168] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0169] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0170] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0171] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0172] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0173] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A chip power consumption control method, characterized in that, The method includes: The system acquires the port traffic characteristics corresponding to the chip's ports, the interaction traffic characteristics of the source and destination ports corresponding to the chip's switching structure modules, the service traffic characteristics corresponding to the chip's packet processing units, and the burst traffic characteristics corresponding to the chip's buffer modules. Traffic demand is generated based on the instantaneous bandwidth of the port and / or the duration of no traffic, and the rate adjustment strategy and / or hierarchical sleep strategy of the port physical layer and media access control layer of the chip are obtained based on the traffic demand. Traffic demand is generated based on the link bandwidth ratio of each source port and each destination port, and switching link switching state policies are generated based on the traffic demand to close idle links and / or reduce clock frequency. Traffic demand is generated based on business priority and / or package processing complexity, and a package processing core activation quantity strategy, including business allocation and / or business processing path, is generated based on the traffic demand. Based on the traffic burst parameters, the cache demand in the future time period is predicted to obtain the traffic demand, and the number of cache activations is generated based on the traffic demand. According to the rate adjustment strategy, the rate at which the port sends network traffic is adjusted; according to the hierarchical sleep strategy, the functional modules in the port physical layer other than the preamble detection module, and the functional modules in the media access control layer other than the wake-up trigger module are managed. According to the switching link switching state policy, the switching structure module shuts down the clock drive of the link and cuts off the power supply. The switching structure module also reduces the clock frequency of the corresponding link, stores the routing information corresponding to the active link, and marks the idle link as invalid. Based on the core activation quantity strategy for packet processing, different core groups of the chip process services with different service priorities, and services with different packet processing complexities are processed based on the service processing path; Based on the number of cache activations, activate the corresponding storage block in the cache module.

2. The method according to claim 1, characterized in that, The method further includes: When the instantaneous bandwidth of the port is continuously lower than the first target threshold for a preset duration, a rate adjustment strategy for rate degradation of the port physical layer and media access control layer of the chip is generated. When the instantaneous bandwidth of the port is continuously greater than or equal to the second target threshold for a preset duration, a rate adjustment strategy for rate upgrade of the port physical layer and media access control layer of the chip is generated, wherein the first target threshold is less than the second target threshold, and both the first target threshold and the second target threshold are determined based on the current rate of the port.

3. The method according to claim 1, characterized in that, The chip includes a first core group and a second core group; the method further includes: The highest priority tasks are assigned to the first core group for processing; In the presence of second-priority services other than the first-priority services, the second core group is dynamically activated through clock gating, and the second-priority services are allocated to the second core group. If there are no second-priority services other than the first priority, turn off the clock of the second core group.

4. The method according to claim 1, characterized in that, The method further includes: The cache activation quantity is generated based on the aforementioned cache requirements and the first redundancy ratio. If the actual cache usage in the cache module exceeds the target required capacity, the number of activations is increased, wherein the target required capacity is determined based on the cache requirement and a second redundancy ratio, and the second redundancy ratio is greater than the first redundancy ratio.

5. A chip power consumption control device, characterized in that, The device includes: The network traffic feature acquisition module is used to acquire the port traffic features corresponding to the port of the chip, the interaction traffic features of the source port and destination port corresponding to the switching structure module of the chip, the service traffic features corresponding to the packet processing unit of the chip, and the burst traffic features corresponding to the buffer module of the chip. The hardware resource activation strategy generation module is configured to: generate traffic demand based on instantaneous port bandwidth and / or duration of no traffic, and obtain rate adjustment strategies and / or hierarchical sleep strategies for the chip's port physical layer and media access control layer based on the traffic demand; generate traffic demand based on the link bandwidth ratio corresponding to each source port and each destination port, and generate switching link on / off state strategies for closing idle links and / or reducing clock frequency based on the traffic demand; generate traffic demand based on service priority and / or packet processing complexity, and generate a packet processing core activation quantity strategy including service allocation and / or service processing path based on the traffic demand; predict cache demand in future time periods based on traffic burst parameters to obtain traffic demand, and generate cache activation quantity based on the traffic demand; The low-power module is configured to: adjust the rate at which the port transmits network traffic according to a rate adjustment strategy; manage all functional modules in the port physical layer except for the preamble detection module, and all functional modules in the media access control layer except for the wake-up trigger module, according to a hierarchical sleep strategy; disable the clock drive of the link and cut off the power supply through the switching structure module according to a switching link on / off state strategy; reduce the clock frequency of the corresponding link through the switching structure module; store the routing information corresponding to the active link; and mark the idle link as invalid. According to a packet processing core activation quantity strategy, process services with different service priorities through different core groups of the chip, and process services with different packet processing complexities based on the service processing path. Activate the corresponding storage block in the cache module according to the cache activation quantity.

6. A chip comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 4.

7. A network interface card, characterized in that, It includes the chip as described in claim 6 and multiple interfaces, through which the chip processes data or communicates externally.

8. A computer device, characterized in that, Includes the network interface card as described in claim 7, wherein the network interface card is used for processing data or external communication.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

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