Small-size CT open trench IGBT device and manufacturing method thereof

Abstract

This invention discloses a small-size CT-type trench IGBT device and its fabrication method, relating to the field of semiconductor device technology. The fabrication method includes the following steps: fabricating a drift region, a carrier storage region, a bulk doped region, a source region, and a trench gate structure on a semiconductor substrate; using a second mask, etching is performed in the region between the trench gate structures to expose the bulk doped region; selective epitaxial growth of Si is performed on the surface of the exposed bulk doped region, and in-situ doping is performed during the epitaxial growth process to form a selective epitaxial growth region; contact hole metal pillars and a surface metal layer are formed on the selective epitaxial growth region. This invention can effectively solve the problem of high-quality ohmic contact at the bottom of small-size CT openings, while avoiding the introduction of additional photolithography steps, reducing process complexity, and improving device reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a small-size CT-type trench IGBT device and its fabrication method. Background Technology

[0002] In the development of power electronics technology, compared with planar gate structures, trench insulated gate bipolar transistors (IGBTs) have gradually become the mainstream because the conductive channels are formed vertically on the trench sidewalls, eliminating the traditional JFET region. This allows for a larger effective channel width within the same chip area, significantly reducing on-resistance and increasing current and power density.

[0003] As technology advances, cell pitch continues to shrink, leading to a dramatic reduction in the size of the metal contact hole (CT hole) at the top of the cell. When the CT hole size is very small while the depth remains constant, its aspect ratio increases, forming a narrow and deep hole. During P+ ion implantation into the P-body region at the bottom of the CT hole to form an ohmic contact, the high aspect ratio of the hole wall severely blocks incident ions, resulting in an ion implantation shadowing effect, where only a very small number of ions reach the bottom of the hole. This results in a severely insufficient boron ion dose implanted into the P-body region at the bottom of the hole, making it impossible to form a high-quality, low-resistance P+ ohmic contact.

[0004] To address the aforementioned issues, a related technology known to the inventors involves advancing the P+ implantation process before etching the CT aperture. Specifically, after completing the front-end structures such as the trench gate, P-body, and N+ source region, a separate photolithography step is performed, using a new mask to define the area below the future CT aperture where P+ contacts will form. Then, a high dose of boron ions is implanted onto the flat silicon wafer surface to form the P+ region, followed by annealing for activation. Finally, normal CT aperture photolithography and etching are performed.

[0005] However, this existing technical solution has the following drawbacks: The process is complex and costly: it adds a dedicated P+ lithography mask and the corresponding lithography, cleaning and inspection processes, which directly increases the manufacturing cost and process complexity.

[0006] The overlay accuracy requirements are extremely high: subsequent CT hole etching must be precisely aligned in three-dimensional space with the previously fabricated, invisible P+ region. Any tiny alignment deviation may lead to poor contact between the metal electrode and the P+ region, or a short circuit with the adjacent N+ source region, placing extremely high demands on the overlay accuracy of the lithography machine.

[0007] Lattice damage and defects: High doses of P+ ion implantation can cause severe lattice damage on the silicon surface, which is difficult to completely repair even after annealing, and may become a hidden danger to the long-term reliability of the device.

[0008] Thermal budget side effects: The high-temperature annealing process after P+ implantation can cause additional longitudinal and lateral diffusion of impurities in the already formed N+ source region. This may lead to changes in channel length, affecting the stability of the device threshold voltage, and also apply additional thermal stress to the gate oxide layer on the trench sidewalls, potentially impairing its reliability.

[0009] Therefore, there is an urgent need in this field for a novel trench IGBT device structure and its fabrication method that can effectively solve the problem of high-quality ohmic contact at the bottom of small-sized CT openings, while avoiding the introduction of additional photolithography steps, reducing process complexity, and improving device reliability. Summary of the Invention

[0010] The purpose of this invention is to provide a small-size CT-grooved IGBT device and its fabrication method to solve the problems existing in the prior art. It can effectively solve the problem of high-quality ohmic contact at the bottom of small-size CT openings, while avoiding the introduction of additional photolithography steps, reducing process complexity, and improving device reliability.

[0011] To achieve the above objectives, the present invention provides the following solution: This invention provides a method for fabricating a small-size CT-grooved IGBT device, comprising the following steps: Fabricate drift regions, carrier storage regions, bulk doped regions, source regions, and trench gate structures on semiconductor substrates; Using a second mask, etching is performed in the region between the trench gate structures to expose the bulk doped region; Selective epitaxial growth of Si is performed on the exposed bulk doped region surface, and in-situ doping is performed during the epitaxial growth process to form a selective epitaxial growth region. Contact hole metal pillars and surface metal layers are formed on the selective epitaxial growth region.

[0012] Preferably, the etching step using the second mask includes: using the second mask as a barrier to etch the source region, with the etching stopping inside the bulk doped region, thereby exposing the bulk doped region.

[0013] Preferably, the second mask is a multilayer composite material, comprising, from bottom to top, a SiO2 layer, a BPSG layer, and a Si3N4 layer; wherein the thickness of the SiO2 layer is 1000Å-3000Å, the thickness of the BPSG layer is 3000Å-6000Å, and the thickness of the Si3N4 layer is 5000Å-12000Å; after etching, the SiO2 layer and the BPSG layer are retained to form a gate-source isolation layer.

[0014] Preferably, the selective epitaxial growth of Si involves in-situ doping with the same doping polarity as the bulk doped region and opposite to that of the source region, and the doping concentration is 10. 13 cm -3 Up to 10 21 cm -3 .

[0015] Preferably, the selective epitaxial growth of Si uses a silicon source gas and a dopant gas; the selective growth is performed only on the semiconductor surface of the bulk doped region, and no growth is performed on the source region sidewalls of opposite polarity.

[0016] Preferably, in the steps of fabricating the drift region, carrier storage region, bulk doped region, and source region, the carrier storage region and the bulk doped region are formed by maskless ion implantation and jointly activated by high-temperature annealing; the source region is formed by maskless ion implantation and activated by high-temperature annealing.

[0017] Preferably, in the step of fabricating the trench gate structure, a trench is etched using a first mask, and the trench is oxidized and filled with polysilicon to form a gate oxide layer and a polysilicon gate.

[0018] Preferably, the method further includes the step of sequentially forming a field cutoff region, a back doped region, and a metal collector on the back side of the semiconductor substrate.

[0019] The present invention also provides a small-size CT-type trench IGBT device, manufactured by the method described above. The device includes: a drift region, a carrier storage region located above the drift region, a bulk doped region located above the carrier storage region, a source region located above the bulk doped region, a trench gate structure, and a selective epitaxial growth region formed by selective epitaxial growth and in-situ doping of Si. The selective epitaxial growth region is located in the mesa region between the trench gate and is in contact with the bulk doped region.

[0020] Preferably, the structure comprises, in sequence along the vertical direction: a metal collector, a back-side doped region, a field-stop region, the drift region, the carrier storage region, the bulk doped region, the selective epitaxial growth region, the source region, a gate-source isolation layer, a contact hole metal pillar, and a surface metal layer.

[0021] The present invention achieves the following technical effects compared to the prior art: This invention reduces the use of P+ photomasks in existing processes by using a second mask in conjunction with selective epitaxial growth and in-situ doping of Si. It allows for higher doping concentrations without causing lattice damage and achieves higher doping uniformity. The resistivity of the CT vias in the device is lower, resulting in better ohmic contact. The selective growth temperature is lower, avoiding the high-temperature annealing of the P+ region in existing processes, preventing secondary diffusion in the N+ source region, maintaining the stability of the device's threshold voltage, and avoiding the potential decrease in gate oxide reliability on the trench sidewalls caused by existing processes. The use of the second mask also reduces the use of high-precision CT photomasks in existing processes, lowering the requirements for the overlay accuracy of the lithography machine.

[0022] Furthermore, by combining ion implantation and annealing with the first mask, the carrier storage region, the bulk doped region, the gate oxide layer, and the polysilicon are formed sequentially. Compared with the existing process, in which the trench gate, carrier storage region, and bulk doped region all need to be realized through photolithography masks, this method effectively reduces the use of masks, simplifies the process flow, and saves costs. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a trench-type IGBT device known to the inventors of this invention; Figure 2 A schematic diagram of the structure after fabricating drift region, carrier storage region, bulk doped region and source region on a semiconductor substrate; Figure 3 In order to be in Figure 2 Based on this, a schematic diagram of the structure after placing the first mask is shown; Figure 4 In order to be in Figure 3 Based on this, a structural schematic diagram of the trench grid structure is created; Figure 5 In order to be in Figure 4 Based on the above, a schematic diagram of the structure after placing the second mask is shown; Figure 6 In order to be in Figure 5 Based on this, a schematic diagram of the structure after etching the CT holes and exposing the bulk doped region is shown. Figure 7 In order to be in Figure 6 Based on this, selective epitaxial growth of Si is performed, and in-situ doping is carried out during the epitaxial growth process to form a structural diagram of the selective epitaxial growth region; Figure 8 In order to be in Figure 7 Based on this, a schematic diagram of the structure after forming the metal pillar of the contact hole is shown; Figure 9 In order to be in Figure 8 Based on this, a schematic diagram of the structure after forming a field cutoff region, a back doped region, and a metal collector sequentially on the back side of a semiconductor substrate is shown. Wherein, 1-metal collector; 10-backside doped region; 20-field cutoff region; 30-drift region; 40-carrier storage region; 41-polysilicon; 42-gate oxide layer; 50-bulk doped region; 51-selective epitaxial growth region; 52-source region; 60-gate-source isolation layer; 70-surface metal layer; 71-contact hole metal pillar; 81-first mask; 82-second mask. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] The purpose of this invention is to provide a small-size CT-grooved IGBT device and its fabrication method to solve the problems existing in the prior art. It can effectively solve the problem of high-quality ohmic contact at the bottom of small-size CT openings, while avoiding the introduction of additional photolithography steps, reducing process complexity, and improving device reliability.

[0027] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] The contact hole in this manual refers to the CT hole.

[0029] The following is combined Figures 1 to 9 The following describes embodiments of the present invention.

[0030] Example 1 This invention provides a method for fabricating a small-size CT-grooved IGBT device, comprising the following steps: A drift region 30, a carrier storage region 40, a bulk doped region 50, a source region 52, and a trench gate structure are fabricated on a semiconductor substrate. Using the second mask 82, etching is performed in the region between the trench gate structures to expose the bulk doped region 50; Selective epitaxial growth of Si is performed on the exposed bulk doped region 50 surface, and in-situ doping is performed during the epitaxial growth process to form a selective epitaxial growth region 51. Contact hole metal pillars 71 and surface metal layer 70 are formed on the selective epitaxial growth region 51.

[0031] This method fundamentally avoids the shadowing effect of high aspect ratio CT holes on ion implantation by introducing a "first-open, then-epitaxy" process sequence. Specifically, after etching to expose the flat surface of the bulk doped region 50, selective epitaxial growth is then performed. At this point, reactive gases (such as SiH4) and dopant gases (such as B2H8) can reach the target semiconductor surface without obstruction, directly forming a single-crystal silicon layer through vapor-phase epitaxy, and in-situ incorporating high concentrations of P-type impurity atoms into the silicon lattice. This process thermodynamically and kinetically tends to occur on the semiconductor surface rather than on insulating media (such as silicon oxide or silicon nitride), thus exhibiting excellent selectivity. The formed epitaxial region and the bulk doped region 50 are single-crystal continuations with high interface quality, and the doping concentration can be precisely controlled by gas flow, far exceeding the surface concentration achievable after activation following traditional ion implantation. This naturally forms a high-quality, low-resistance P+ ohmic contact region at the bottom of the CT hole, without affecting the stability of the device threshold voltage, and avoiding the defects of reduced gate oxide layer reliability on the trench sidewalls that may occur with the original process. Meanwhile, since epitaxial growth is carried out within existing CT holes, there is no need to introduce additional photolithography steps to form the P+ region, simplifying the process flow.

[0032] In some embodiments, the step of etching using the second mask 82 includes: using the second mask 82 as a barrier, etching the source region 52, and stopping the etching inside the body doped region 50, thereby exposing the body doped region 50.

[0033] This embodiment explicitly stops the etching within the bulk doped region 50, ensuring that the exposed surface is a single-crystal silicon bulk doped region 50. This provides a perfect seed layer for subsequent high-quality selective epitaxial growth, a prerequisite for achieving perfect single-crystal epitaxy. Furthermore, the use of the second mask 82 reduces the need for high-precision CT photomasks in existing processes, lowering the requirements for the overlay accuracy of the photolithography machine.

[0034] The second mask 82 is a hard mask.

[0035] Specifically, in some embodiments, the second mask 82 is a multilayer composite material, comprising, from bottom to top, a SiO2 layer, a BPSG layer, and a Si3N4 layer; wherein the thickness of the SiO2 layer is 1000Å-3000Å, the thickness of the BPSG layer is 3000Å-6000Å, and the thickness of the Si3N4 layer is 5000Å-12000Å; after etching, the SiO2 layer and the BPSG layer are retained, forming the gate-source isolation layer 60.

[0036] This specific mask design cleverly achieves "multi-purpose use," serving as both an etching hard mask and the final dielectric layer. During the etching stage, the Si3N4 layer provides excellent resistance to dry etching. After etching, the Si3N4 is removed, leaving the SiO2 / BPSG composite layer as an insulating layer between the gate electrode and the source region 52 metal. This design eliminates the step of separately depositing the gate-source isolation dielectric, simplifying the process and reducing costs.

[0037] In some embodiments, the selective epitaxial growth of Si is performed with in-situ doping, the doping polarity being the same as that of the bulk doped region 50 and opposite to that of the source region 52, and the doping concentration being 10. 13 cm -3 Up to 10 21 cm -3 To form a good ohmic contact.

[0038] In some embodiments, selective epitaxial growth of Si uses silicon source gas and dopant gas; selective growth is performed only on the semiconductor surface of the bulk doped region 50, and no growth is performed on the sidewalls of the source region 52 of opposite polarity. More specifically, due to the etching step of the CT hole, a groove is formed on the bulk doped region 50, and its growth rate on the bottom surface of the groove (i.e., the semiconductor surface of the bulk doped region 50) is much greater than its growth rate on the sidewalls of the groove.

[0039] This invention ensures that dopants are precisely added only to the bulk regions where ohmic contacts are needed, preventing short circuits caused by polysilicon growth on gate oxide or other dielectrics, and avoiding the formation of parasitic P-type layers on the sidewalls of the N+ source region 52, which would reduce the effective area of ​​the source region 52 or induce parasitic transistor effects. Secondly, selective growth avoids the need for additional patterning steps to remove unwanted epitaxial material, maintaining process simplicity. This selectivity stems from the intrinsic surface reaction kinetics differences in the epitaxial growth process: single-crystal silicon surfaces readily adsorb silanes and decompose for growth, while SiO2 or Si3N4 surfaces are less prone to nucleation. By precisely controlling the temperature, pressure, and gas ratio of the reaction chamber, this selectivity can be maximized, thereby achieving self-aligned contact region formation.

[0040] In some embodiments, in the steps of fabricating the drift region 30, the carrier storage region 40, the bulk doped region 50, and the source region 52, the carrier storage region 40 and the bulk doped region 50 are formed by ion implantation and jointly activated by high-temperature annealing; the source region 52 is formed by ion implantation and activated by high-temperature annealing, that is, the carrier storage region 40, the bulk doped region 50, and the source region 52 are all formed by maskless ion implantation.

[0041] This embodiment combines the implantation and activation of the carrier storage region 40 and the bulk doped region 50, resulting in significant optimization. The implantation depth and concentration distribution of the carrier storage region 40 (typically N-type) and the bulk doped region 50 (P-type) require meticulous co-design to optimize the device's conduction and switching characteristics. By activating them in the same annealing cycle, not only is one high-temperature thermal treatment step reduced, lowering the process thermal budget and manufacturing cost, but more importantly, it ensures that both impurities diffuse under the same thermal treatment, which is beneficial for obtaining a more stable and predictable vertical doping profile, reducing impurity distribution fluctuations caused by multiple annealings, and improving the consistency of device parameters. The implantation and activation of the source region 52 are performed separately, allowing for independent optimization of its junction depth and surface concentration to accommodate subsequent contact hole etching and selective epitaxial process windows.

[0042] In some embodiments, during the step of fabricating the trench gate structure, a trench is etched using a first mask 81, and the trench is oxidized and filled with polysilicon 41 to form a gate oxide layer 42 and a polysilicon gate 41.

[0043] In this embodiment, the carrier storage region 40, the bulk doped region 50, the gate oxide layer 42, and the polysilicon 41 are formed sequentially through a first mask combined with ion implantation and annealing. Compared with the existing process, where the trench gate, the carrier storage region 40, and the bulk doped region 50 all need to be realized through photolithography masks, this embodiment effectively reduces the use of masks, simplifies the process flow, and saves costs.

[0044] Furthermore, the aforementioned process scheme also optimizes the fabrication steps of the source region 52. During the subsequent etching of the contact holes using the second mask 82, the etching definition of both source regions 52 can be completed simultaneously, up to the middle of the bulk doped region 50. This further integrates the process steps, avoiding the need for a separate photolithography step for source region patterning, and maintaining the core advantages of this scheme in simplifying the process and improving efficiency.

[0045] In some embodiments, the trench depth is 2µm-7µm and the gate oxide layer 42 thickness is 500Å-2000Å.

[0046] In some embodiments, the method further includes the step of sequentially forming a field cutoff region 20, a back doped region 10, and a metal collector 1 on the back side of the semiconductor substrate. When the semiconductor substrate is a single-crystal silicon substrate, before forming the field cutoff region 20, the back doped region 10, and the metal collector 1, the semiconductor substrate needs to be thinned to form a thin film.

[0047] In some embodiments, the semiconductor substrate may be selected from Si and wide bandgap semiconductors such as SiC, GaN, SiGe, GaAs, and diamond; when the semiconductor substrate is a single-crystal silicon substrate, the single-crystal silicon substrate serves as the drift region 30 of the structure; the drift region 30 may be N-type or P-type doped.

[0048] In some embodiments, the contact hole metal pillar 71 and the surface metal layer 70 are Ti / TiN alloy and tungsten metal, which are formed by magnetron sputtering and have a thickness of 10 to 50 kÅ.

[0049] Example 2 The present invention also provides a small-size CT-type trench IGBT device, which is manufactured by the method described above. The device includes: a drift region 30, a carrier storage region 40 located above the drift region 30, a bulk doped region 50 located above the carrier storage region 40, a source region 52 located above the bulk doped region 50, a trench gate structure, and a selective epitaxial growth region 51 formed by selective epitaxial growth and in-situ doping of Si. The selective epitaxial growth region 51 is located in the mesa region between the trench gate and is in contact with the bulk doped region 50.

[0050] This device structure is the physical embodiment of the invention, and its core advantage lies in the integration of a "selective epitaxial growth region 51". Located at the bottom of the contact hole, this region serves as a natural extension and reinforcement of the bulk doped region 50. It boasts high single-crystal quality, seamless connection with the bulk region, and extremely low interfacial resistance. Because it is formed through vapor-phase doping, the impurity concentration can far exceed the ion implantation limit and is uniformly distributed, thus achieving a near-ideal P+ ohmic contact at the bottom of the tiny CT hole. This structural feature allows the device to maintain stable and low on-resistance even as the cell size continues to shrink, while avoiding localized overheating and reliability degradation caused by poor contact. Compared to traditional structures with CT holes of the same size, this structure significantly improves the robustness and lifetime of the device while maintaining high current density.

[0051] In some embodiments, the following are included sequentially along the vertical direction: a metal collector 1, a back doped region 10, a field cutoff region 20, a drift region 30, a carrier storage region 40, a bulk doped region 50, a selective epitaxial growth region 51, a source region 52, a gate-source isolation layer 60, a contact hole metal pillar 71, and a surface metal layer 70.

[0052] Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. Furthermore, those skilled in the art will recognize that, based on the ideas of this invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A method for fabricating a small-size CT-grooved IGBT device, characterized in that, Includes the following steps: Fabricate drift regions, carrier storage regions, bulk doped regions, source regions, and trench gate structures on semiconductor substrates; Using a second mask, etching is performed in the region between the trench gate structures to expose the bulk doped region; Selective epitaxial growth of Si is performed on the exposed bulk doped region surface, and in-situ doping is performed during the epitaxial growth process to form a selective epitaxial growth region. Contact hole metal pillars and surface metal layers are formed on the selective epitaxial growth region.

2. The method for fabricating a small-size CT-grooved IGBT device according to claim 1, characterized in that: The step of etching using the second mask includes: using the second mask as a barrier, etching the source region, stopping the etching inside the bulk doped region, thereby exposing the bulk doped region.

3. The method for fabricating a small-size CT-grooved IGBT device according to claim 2, characterized in that: The second mask is a multilayer composite material, consisting of a SiO2 layer, a BPSG layer, and a Si3N4 layer from bottom to top; wherein the thickness of the SiO2 layer is 1000Å-3000Å, the thickness of the BPSG layer is 3000Å-6000Å, and the thickness of the Si3N4 layer is 5000Å-12000Å; after etching, the SiO2 layer and the BPSG layer are retained to form a gate-source isolation layer.

4. The method for fabricating a small-size CT-grooved IGBT device according to claim 1, characterized in that: The selective epitaxial growth of Si involves in-situ doping with the same doping polarity as the bulk doped region and opposite to that of the source region, at a doping concentration of 10. 13 cm -3 Up to 10 21 cm -3 .

5. The method for fabricating a small-size CT-grooved IGBT device according to claim 4, characterized in that: The selective epitaxial growth of Si uses silicon source gas and dopant gas; selective growth is performed only on the semiconductor surface of the bulk doped region, and no growth is performed on the source region sidewalls of opposite polarity.

6. The method for fabricating a small-size CT-grooved IGBT device according to claim 1, characterized in that: In the steps of fabricating the drift region, carrier storage region, bulk doped region, and source region, the carrier storage region and the bulk doped region are formed by maskless ion implantation and jointly activated by high-temperature annealing; the source region is formed by maskless ion implantation and activated by high-temperature annealing.

7. The method for fabricating a small-size CT-grooved IGBT device according to claim 6, characterized in that: In the step of fabricating the trench gate structure, a trench is etched using a first mask, and the trench is oxidized and filled with polysilicon to form a gate oxide layer and a polysilicon gate.

8. The method for fabricating a small-size CT-grooved IGBT device according to claim 1, characterized in that: It also includes the step of sequentially forming a field cutoff region, a back doped region, and a metal collector on the back side of the semiconductor substrate.

9. A small-size CT-grooved IGBT device, characterized in that, The device is manufactured by the method of any one of claims 1 to 8, and comprises: Drift zone; The carrier storage region located above the drift region; A bulk doped region located above the carrier storage region; The source region located above the bulk doped region; The trench gate structure; and the selective epitaxial growth region formed by selective epitaxial growth and in-situ doping of Si, the selective epitaxial growth region being located in the mesa region between the trench gates and in contact with the bulk doped region.

10. The small-size CT-grooved IGBT device according to claim 9, characterized in that, The structure comprises, in sequence along the vertical direction: a metal collector, a back-side doped region, a field-stop region, the drift region, the carrier storage region, the bulk doped region, the selective epitaxial growth region, the source region, a gate-source isolation layer, a contact hole metal pillar, and a surface metal layer.

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