A high-performance face incidence germanium-on-silicon detector structure and a preparation method thereof

Abstract

This invention relates to the field of semiconductor optoelectronic device technology, and discloses a high-performance surface-incident silicon-based germanium detector structure and its fabrication method. The structure includes an SOI substrate, a silicon substrate, a buried oxide layer, and an inner doped region formed by etching the top silicon layer from bottom to top. A partially suspended silicon oxide template layer is provided above the inner doped region. A germanium lateral epitaxial region is provided between the buried oxide layer and the template layer, which includes an intrinsic germanium absorption layer and an outer doped region, forming a lateral PIN structure together with the inner doped region. Electrodes penetrate the template layer to achieve electrical connection in the corresponding regions. During fabrication, a suspended template and seed crystal are formed by selective etching back, and then germanium is laterally epitaxially grown in the cavity to fabricate electrodes. This invention decouples light absorption from carrier transport direction, improving device responsivity and bandwidth; it utilizes the physical capture of interface mismatch dislocations at the insulating layer boundary to reduce dark current; the process is compatible with standard CMOS platforms, facilitating large-scale, low-cost integration.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic device technology, specifically to a high-performance surface-incident silicon-based germanium detector structure and its fabrication method. Background Technology

[0002] In silicon photonics integrated systems, surface-incident silicon-based germanium detectors are the core devices for photoelectric signal conversion. Traditional surface-incident silicon-based germanium detectors typically employ a vertical PIN structure, where a bottom doped layer, an intrinsic absorption layer, and a top doped layer are arranged sequentially from bottom to top along the epitaxial growth direction of the material. In this conventional structure, the absorption direction of photons is parallel to the transport direction of charge carriers. To ensure the device fully absorbs incident light of a specific wavelength to achieve high photoresponsivity, the physical thickness of the intrinsic germanium layer needs to be increased. However, increasing the thickness of the intrinsic layer lengthens the transit distance of photogenerated charge carriers under the influence of an electric field, resulting in a longer carrier transit time and thus reducing the high-frequency operating bandwidth of the detector. Therefore, there is an inherent contradiction between device responsivity and bandwidth in the traditional vertical structure.

[0003] Meanwhile, conventional surface-incident detectors require surface-doped regions and metal electrodes for external electrical connections on top of the germanium absorption layer. The physical presence of these top structures directly blocks part of the incident light beam. Furthermore, the free carrier absorption effect and lattice scattering phenomenon induced by the high-concentration doped region on the top layer cause additional light energy loss, further limiting the improvement of the overall device responsivity.

[0004] At the material preparation level, due to the approximately 4% lattice constant mismatch between silicon and germanium, when germanium is directly grown heteroepitaxially on a silicon substrate, stress release at the silicon-germanium interface leads to the formation of high-density penetrating dislocations within the germanium epitaxial layer. These lattice defects penetrating the active region act as non-radiative recombination centers during device operation, forming leakage channels within the material. This causes a significant increase in the device's dark current, severely degrading the detector's signal-to-noise ratio. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a high-performance surface-incident silicon-based germanium detector structure and its fabrication method. This solves the problem that in traditional silicon-based germanium detectors, during heteroepitaxial growth, lattice mismatch between silicon and germanium leads to a high density of penetrating dislocations within the germanium epitaxial layer. These lattice defects act as non-radiative recombination centers, increasing the dark current of the device and thus limiting the detector's signal-to-noise ratio and overall optoelectronic performance. This invention also provides a high-performance surface-incident silicon-based germanium detector structure that resolves the mutual constraint between bandwidth and responsivity in traditional surface-incident silicon-based germanium detectors.

[0006] To address the above problems, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a high-performance surface-incident silicon-based germanium detector structure, employing the following technical solution: A high-performance surface-incident silicon-based germanium detector structure includes: an SOI substrate, comprising, from bottom to top, a silicon substrate, a buried oxide layer, and an inner doped region, wherein the inner doped region is formed by local etching of the top silicon layer of the SOI substrate; a silicon oxide template layer disposed above the inner doped region, with the portion of the silicon oxide template layer not supported by the inner doped region suspended above the buried oxide layer, forming a semi-suspended state; a germanium lateral epitaxial region located between the buried oxide layer and the semi-suspended silicon oxide template layer, and laterally connected to the inner doped region; the germanium lateral epitaxial region includes an intrinsic germanium absorption layer and an outer doped region, which together with the inner doped region form a PIN structure; and electrodes penetrating the corresponding region of the silicon oxide template layer, forming electrical connections with the top surfaces of the inner and outer doped regions, respectively.

[0008] By employing the above technical solution, this invention utilizes a semi-suspended silicon oxide template layer and a bottom buried oxide layer to construct a lateral growth physical space. During the lateral epitaxy of germanium material, penetrating dislocations caused by silicon-germanium lattice mismatch are blocked by the boundaries of the upper and lower insulating layers as they slide along specific crystal planes. Specifically, the dislocation lines extend to the interface of the silicon oxide template layer or the buried oxide layer after sliding a certain distance and then terminate there. This geometric confinement mechanism in the structure intercepts a large number of lattice dislocations in the initial growth region near the inner ring doped region, resulting in the intrinsic germanium absorber layer grown at the far end of the channel having better single-crystal integrity. The improvement in crystal quality directly reduces the deep-level defect density in the photoelectric conversion region, thereby reducing the device's dark current. In addition, the inner ring doped region, the intrinsic germanium absorber layer, and the outer ring doped region are arranged sequentially in the horizontal direction to form a lateral PIN structure, decoupling the photon absorption direction from the carrier transport direction on a spatial physical scale. Under this mechanism, the vertical light absorption depth is no longer limited by the carrier drift distance, thus ensuring sufficient light absorption volume to maintain the device's high responsivity. Simultaneously, the narrow intrinsic layer span in the horizontal direction effectively reduces the carrier transit time under electric field drive. This physical-level structural decoupling overcomes the inherent bottleneck of mutual constraint between responsivity and bandwidth in traditional vertical detectors, achieving a simultaneous improvement in photoelectric responsivity and high-frequency bandwidth.

[0009] Preferably, the thickness of the inner doped region is 220 nm to 2 μm; the material of the inner doped region is doped single-crystal silicon. The thickness of the silicon oxide template layer is 200 nm to 1 μm. The total lateral width of the germanium lateral epitaxial region is 600 nm to 1.5 μm.

[0010] By adopting the above technical solution, setting the thickness of the inner doped region within the range of 220 nm to 2 μm provides sufficient end faces for germanium lateral epitaxy as crystal growth templates, avoiding instability of the subsequent crystallization interface due to insufficient contact area. Simultaneously, controlling the total width of the germanium lateral epitaxial region between 600 nm and 1.5 μm not only ensures sufficient slip space for mismatched dislocations at the interface to be captured by the upper and lower boundaries, but also takes into account the width requirements of the depletion region within the PIN junction, thereby maintaining a suitable lateral electric field strength to facilitate carrier separation. Furthermore, setting the thickness of the silicon oxide template layer to 200 nm to 1 μm ensures that it maintains necessary structural support even when partially suspended, preventing stress deformation of the device during subsequent heat treatment or metal deposition.

[0011] Secondly, the present invention provides a method for fabricating a high-performance surface-incident silicon-based germanium detector structure, employing the following technical solution: A method for fabricating a high-performance surface-incident silicon-based germanium detector structure includes the following steps: Prepare an SOI substrate consisting of a silicon substrate, a buried oxide layer, and a top silicon layer. Perform a doping treatment on the top silicon layer to make it doped. Silicon oxide is deposited on the top silicon layer to obtain a silicon oxide template layer, and the mesa structure of the stacked top silicon and silicon oxide template layer is etched out. Selective wet etching is performed on the top silicon layer in the above mesa structure. The remaining part forms the inner doped region. Due to the local removal of the bottom silicon layer, the unsupported part of the upper silicon oxide template layer naturally forms a semi-suspended state. Using the exposed side face of the inner ring doped region as a seed crystal, germanium is laterally epitaxially grown in the gap formed by the buried oxide layer and the silicon oxide template layer to obtain the germanium lateral epitaxial region. A doping source is introduced in the process to form the outer ring doped region, thereby constructing a complete PIN structure. The silicon oxide template layer above the corresponding areas of the deposited outer and inner doped regions is etched to open the electrode holes; Metal is deposited inside the electrode holes to achieve electrical connection of the device, forming an electrical connection with the inner ring doped region and the outer ring doped region, thus fabricating the electrode and finally obtaining the high-performance surface-incident silicon-based germanium detector structure.

[0012] By employing the above-described technical solution, this method utilizes the difference in etching rates between top-layer single-crystal silicon and silicon oxide in a specific chemical solution. Through selective etching back, the lateral etching amount of the silicon material is controlled, creating a microstructure cavity within the device, sandwiched between a suspended silicon oxide template layer and a buried oxide layer. The retained inner-ring doped region side face directly serves as a seed crystal exposed at the bottom of the cavity. In the subsequent vapor phase epitaxy stage, the gaseous precursor enters the cavity and undergoes pyrolysis on the seed crystal surface, driving the crystal growth front to continuously advance horizontally along the cavity. This fabrication approach, based on conventional silicon-based microelectronics processes, avoids complex wafer bonding operations, reducing process integration difficulty while improving the overall fabrication yield of the detector structure.

[0013] Preferably, in the step of depositing silicon oxide to obtain a silicon oxide template layer, a silicon oxide template layer is deposited on the top silicon layer using plasma chemical vapor deposition, low-pressure chemical vapor deposition, or atmospheric pressure chemical vapor deposition. In the step of selectively etching back the top silicon layer, the etching solution used is tetramethylammonium hydroxide solution, potassium hydroxide solution, or ethylenediamine-catechol solution; when tetramethylammonium hydroxide solution is used, the mass fraction of the tetramethylammonium hydroxide solution is 25%, and the temperature of the etching environment is 70℃~90℃. In the step of laterally epitaxializing germanium to obtain the germanium lateral epitaxial region, the lateral epitaxy of germanium is performed using ultra-high vacuum chemical vapor deposition, low-pressure chemical vapor deposition, or metal-organic chemical vapor deposition. The step of forming the outer ring doped region is achieved by in-situ doping before the end of the lateral epitaxy of germanium, or by ion implantation after the completion of the lateral epitaxy of germanium. In the step of depositing metal to prepare the electrode, the electrode is deposited using electron beam evaporation, magnetron sputtering or thermal evaporation; the electrode material is selected from combinations of Ni and Al, Ti and Au, Cr and Au or elemental Al.

[0014] By employing the above-mentioned technical solution, during the wet etching of silicon materials, hydroxide ions in the solution undergo a redox reaction with silicon atoms, breaking silicon-silicon bonds and generating soluble silicate ions and hydrogen gas. Because this chemical reaction exhibits significant etching selectivity for silicon and silicon oxide, the buried oxide layer and silicon oxide template layer maintain their morphological integrity in the etching solution, thereby accurately defining the physical dimensions of the microcavities. Furthermore, using a 25% (w / w) tetramethylammonium hydroxide solution at a temperature between 70°C and 90°C effectively controls the kinetic rate of the above reaction; the moderate reaction rate avoids the impact damage to the silicon seed crystal end face caused by a large number of hydrogen bubbles generated by the violent reaction, ensuring the flatness of the epitaxial starting interface. In addition, using chemical vapor deposition for germanium epitaxial growth, relying on the long-range diffusion capability of gas molecules within the microcavities, germanium atoms can effectively fill the internal steps of the slits, reducing the probability of voids appearing inside the epitaxial layer. In the final electrode fabrication stage, metal films with specific material combinations can form low-resistance ohmic contacts with the underlying doped silicon or doped germanium after heat treatment. This reduction in parasitic resistance has a direct effect on improving the output characteristics of high-frequency electrical signals of the device.

[0015] This invention provides a high-performance surface-incident silicon-based germanium detector structure and its fabrication method. It offers the following advantages: 1. The surface-incident silicon-based germanium detector of the present invention adopts a lateral PIN structure to decouple the photon absorption direction from the carrier transport direction. By independently adjusting the vertical thickness and lateral doping spacing of the intrinsic germanium absorption layer, the transit time of carriers under a horizontal electric field can be shortened while ensuring that the incident light is fully absorbed by the thick germanium layer, thus overcoming the contradiction between responsivity and bandwidth in traditional surface-incident detectors. At the same time, no doped layer or metal electrode is placed directly above the intrinsic absorption layer, eliminating the physical obstruction of the electrode and the loss of incident light caused by the absorption of free carriers in the doped region, thereby improving the overall photoelectric responsivity of the device.

[0016] 2. This invention constructs a confined horizontal space through a suspended silicon oxide template layer and an underlying buried oxide layer, thereby enabling template-assisted lateral selective epitaxy of germanium. During the lateral crystal growth stage, mismatch dislocations generated at the silicon-germanium heterojunction interface are physically restricted by the insulating boundaries on both sides and by the mirror force within the material. They extend upwards and downwards and terminate directly at the silicon oxide template or buried oxide layer interface. This mechanism blocks the propagation of penetrating dislocations into the intrinsic germanium absorption layer, avoiding the formation of through-type leakage channels and reducing the dark current of the device from the material structure level.

[0017] 3. The fabrication method described in this invention is compatible with existing standard CMOS manufacturing processes. By utilizing the etching selectivity ratio between different semiconductor materials to perform lateral etching back on the top silicon layer, a physical microcavity for epitaxial growth is naturally formed. Combined with conventional chemical vapor deposition and metal deposition processes, the detector can be constructed. The overall process requires fewer masking and photolithography steps, avoids complex wafer bonding operations, reduces the fabrication complexity of the device, and facilitates the low-cost and large-scale integration of silicon-based optoelectronic chips. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a surface-incident silicon-based germanium detector according to an embodiment of the present invention; Figure 2 A schematic diagram of the fabrication of a surface-incident silicon-based germanium detector; Figure 3 A schematic diagram illustrating the defect evolution at the germanium-silicon interface for germanium epitaxy using template-assisted selective area mapping; Figure 4 The figures show the performance test results of the silicon-based germanium detectors of different sizes of the present invention. (a) represents the measured 3dB bandwidth variation of the detector prepared in the example under different intrinsic absorption layer lateral widths, and (b) represents the absolute responsivity variation extracted under different top silicon thicknesses. Figure 5 This is a comparison diagram of the photoelectric performance distribution of the embodiments of the present invention and Comparative Example 1; Figure 6 This is a comparison diagram of the reverse dark current characteristics of the embodiment of the present invention and Comparative Example 2; Figure 7 This is a comparison diagram of the photoelectric conversion response characteristics of the embodiment of the present invention and Comparative Example 3.

[0019] Among them, 100 is the SOI substrate; 110 is the silicon substrate; 120 is the buried oxide layer; 131 is the inner doped region; 200 is the silicon oxide template layer; 300 is the germanium lateral epitaxial region; 310 is the outer doped region; and 400 is the electrode. Detailed Implementation

[0020] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Preparation Examples 1-4: Preparation Example 1: This preparation example provides a method for preparing a seed substrate with a semi-suspended silicon oxide template layer 200, including the following steps: Step 1: Prepare and clean the SOI substrate 100. The SOI substrate 100 consists of a silicon substrate 110, a buried oxide layer 120, and a top silicon layer. The thickness of the top silicon layer is 500 nm, and the top silicon layer is highly doped single crystal silicon.

[0022] Step 2: A silicon oxide layer with a thickness of 400 nm is deposited on the top silicon layer using plasma chemical vapor deposition process to obtain a silicon oxide template layer 200.

[0023] Step 3: The position of the surface-incident silicon-based germanium detector on the SOI substrate 100 is determined by ultraviolet lithography, and the mesa structure of the stacked top silicon and silicon oxide template layer 200 is etched by inductively coupled plasma etching process.

[0024] Step 4: Using a 25% (w / w) tetramethylammonium hydroxide solution, selectively etch back the top silicon at 70°C to the target size to obtain the inner doped region 131. At this time, the silicon oxide template layer 200 is supported by the inner doped region 131, and the unsupported part forms a semi-suspended state, thus completing the preparation of the seed crystal substrate with the semi-suspended silicon oxide template layer 200.

[0025] Preparation Example 2: This preparation example provides a method for preparing a seed substrate with a semi-suspended silicon oxide template layer 200, including the following steps: Step 1: Prepare and clean the SOI substrate 100. The SOI substrate 100 consists of a silicon substrate 110, a buried oxide layer 120, and a top silicon layer. The thickness of the top silicon layer is 220 nm. The top silicon layer is ordinary single crystal silicon, which is subsequently doped in the inner ring through an ion implantation process.

[0026] Step 2: Deposit a silicon oxide layer on the top silicon layer using a low-pressure chemical deposition process, with a deposition thickness of 200 nm, to obtain a silicon oxide template layer 200.

[0027] Step 3: The position of the surface-incident silicon-based germanium detector on the SOI substrate 100 is determined by electron beam exposure, and the mesa structure of the stacked top silicon and silicon oxide template layer 200 is etched by reactive plasma etching process.

[0028] Step 4: Using potassium hydroxide solution, the top silicon layer is selectively etched to the target size to obtain the inner doped region 131. At this time, the silicon oxide template layer 200 is supported by the inner doped region 131, and the unsupported part forms a semi-suspended state, thus completing the preparation of the seed crystal substrate with the semi-suspended silicon oxide template layer 200.

[0029] Preparation Example 3: This preparation example provides a method for preparing a seed substrate with a semi-suspended silicon oxide template layer 200, including the following steps: Step 1: Prepare and clean the SOI substrate 100. The SOI substrate 100 consists of a silicon substrate 110, a buried oxide layer 120, and a top silicon layer. The thickness of the top silicon layer is 2 μm, and the top silicon layer is highly doped single crystal silicon.

[0030] Step 2: Deposit a silicon oxide layer on the top silicon layer using atmospheric pressure chemical deposition method. The deposition thickness is 1 μm, and a silicon oxide template layer 200 is obtained.

[0031] Step 3: The position of the surface-incident silicon-based germanium detector on the SOI substrate 100 is determined by laser direct writing, and the mesa structure of the top silicon and silicon oxide template layer 200 stacked is etched by ion beam etching process.

[0032] Step 4: Using an ethylenediamine-catechol solution, the top silicon layer is selectively etched to the target size to obtain the inner doped region 131. At this time, the silicon oxide template layer 200 is supported by the inner doped region 131, and the unsupported part forms a semi-suspended state, thus completing the preparation of the seed crystal substrate with the semi-suspended silicon oxide template layer 200.

[0033] Preparation Example 4: This preparation example provides a method for preparing a seed substrate with a semi-suspended silicon oxide template layer 200, including the following steps: Step 1: Prepare and clean the SOI substrate 100. The SOI substrate 100 consists of a silicon substrate 110, a buried oxide layer 120, and a top silicon layer. The thickness of the top silicon layer is 1 μm, and the top silicon layer is highly doped single crystal silicon.

[0034] Step 2: A silicon oxide layer with a thickness of 600 nm is deposited on the top silicon layer using plasma chemical vapor deposition process to obtain a silicon oxide template layer 200.

[0035] Step 3: The position of the surface-incident silicon-based germanium detector on the SOI substrate 100 is determined by ultraviolet lithography, and the mesa structure of the stacked top silicon and silicon oxide template layer 200 is etched by inductively coupled plasma etching process.

[0036] Step 4: Using a 25% tetramethylammonium hydroxide solution, selectively etch the top silicon layer to the target size at 90°C to obtain the inner doped region 131. Since it is anisotropic etching, the remaining top silicon layer cross-section is a crystal plane. At this time, the silicon oxide template layer 200 is supported by the inner doped region 131, and the unsupported part forms a semi-suspended state, thus completing the preparation of the seed crystal substrate with the semi-suspended silicon oxide template layer 200.

[0037] Examples 1-4: Example 1: This embodiment provides a high-performance surface-incident silicon-based germanium detector structure and its fabrication method, including the following steps: Step 1: Using the method described in Preparation Example 1, a seed substrate with a semi-suspended silicon oxide template layer 200 is obtained.

[0038] Step 2: Using the inner ring doped region 131 as a seed crystal, germanium is laterally epitaxially grown between the buried oxide layer 120 and the silicon oxide template layer 200 using an ultra-high vacuum chemical vapor deposition process to obtain a germanium lateral epitaxial region 300. First, a 300nm wide intrinsic germanium absorption layer is epitaxially grown. Before the epitaxial growth ends, a doping source is introduced for in-situ doping to obtain an outer ring doped region 310 with a width of 400nm. Finally, a complete PIN structure of inner ring doped region 131-intrinsic germanium-outer ring doped region 310 is obtained.

[0039] Step 3: Select the silicon oxide template layer 200 region above the outer ring doped region 310 and the inner ring doped region 131 by ultraviolet lithography, and then etch the electrode holes using reactive plasma etching process.

[0040] Step 4: The pattern is transferred to the photoresist using ultraviolet lithography. Electron beam evaporation is then used to deposit metal inside the electrode holes, and the metal on the photoresist is stripped away, completing the deposition of electrode 400 to achieve electrical connection of the device. The materials used for electrode 400 are Ni and Al. The final fabricated surface-incident silicon-based germanium detector structure is shown below. Figure 1 and Figure 2 As shown.

[0041] Example 2: This embodiment provides a high-performance surface-incident silicon-based germanium detector structure and its fabrication method, including the following steps: Step 1: Using the method described in Preparation Example 4, a seed substrate with a semi-suspended silicon oxide template layer 200 is obtained.

[0042] Step 2: Using the inner ring doped region 131 as a seed crystal, germanium is laterally epitaxially grown between the buried oxide layer 120 and the silicon oxide template layer 200 using a low-pressure chemical vapor deposition process to obtain a germanium lateral epitaxial region 300 with a total epitaxial width of 600 nm. The intrinsic germanium in the outer ring is subsequently doped by ion implantation to form the outer ring doped region 310, while the intrinsic germanium absorption layer is retained inside to obtain a complete PIN structure.

[0043] Step 3: Select the silicon oxide template layer 200 region above the outer ring doped region 310 and the inner ring doped region 131 by electron beam exposure, and etch electrode holes using inductively coupled plasma coupling process.

[0044] Step 4: Electrode 400 is deposited inside the electrode holes using magnetron sputtering. Electrode 400 is made of Ti and Au materials. Electrical connections of the device are then completed. The final fabricated surface-incident silicon-based germanium detector structure is shown below. Figure 1 and Figure 2 As shown.

[0045] Example 3: This embodiment provides a high-performance surface-incident silicon-based germanium detector structure and its fabrication method, including the following steps: Step 1: Using the method described in Preparation Example 2, a seed substrate with a semi-suspended silicon oxide template layer 200 is obtained.

[0046] Step 2: Using the inner ring doped region 131 as a seed crystal, germanium is laterally epitaxially grown between the buried oxide layer 120 and the silicon oxide template layer 200 using a metal-organic chemical vapor deposition process to obtain a germanium lateral epitaxial region 300 with a total epitaxial width of 1.5 μm. Before the epitaxial growth ends, an outer ring doped region 310 is obtained through in-situ doping to obtain a complete PIN structure.

[0047] Step 3: Select the silicon oxide template layer 200 area above the outer ring doped region 310 and the inner ring doped region 131 by laser direct writing, and etch out the electrode holes.

[0048] Step 4: Electrode 400 is deposited inside the electrode holes using a thermal evaporation process. Electrode 400 is made of Cr and Au materials. Electrical connections of the device are then completed. The final fabricated surface-incident silicon-based germanium detector structure is shown below. Figure 1 and Figure 2 As shown.

[0049] Example 4: This embodiment provides a high-performance surface-incident silicon-based germanium detector structure and its fabrication method, including the following steps: Step 1: Using the method described in Preparation Example 2, a seed substrate with a semi-suspended silicon oxide template layer 200 is obtained.

[0050] Step 2: Using the inner ring doped region 131 as a seed crystal, germanium is laterally epitaxially grown between the buried oxide layer 120 and the silicon oxide template layer 200 using an ultra-high vacuum chemical vapor deposition process to obtain a germanium lateral epitaxial region 300. Before the epitaxial growth ends, an outer ring doped region 310 is obtained by in-situ doping. The intrinsic germanium in the outer ring is subsequently doped by ion implantation to form the outer ring doped region 310, thereby obtaining a complete PIN structure.

[0051] Step 3: Select the silicon oxide template layer 200 region above the outer ring doped region 310 and the inner ring doped region 131 by ultraviolet lithography, and etch the electrode holes using reactive plasma etching process.

[0052] Step 4: Electrode 400 is deposited inside the electrode holes using electron beam evaporation via ultraviolet lithography. The electrode 400 material is Al. This completes the electrical connection of the device. The final fabricated surface-incident silicon-based germanium detector structure is shown below. Figure 1 and Figure 2 As shown.

[0053] Comparative Examples 1-3: Comparative Example 1: Compared with Example 1, the difference is that a conventional surface-incident vertical PIN structure is used, and the photon absorption direction and the carrier transport direction are consistent. Otherwise, they are the same.

[0054] Comparative Example 2: Compared with Example 1, the difference is that the silicon oxide template layer 200 was not constructed, and the intrinsic germanium layer was directly heteroepitaxially grown on the surface of the top silicon layer. Otherwise, they are the same.

[0055] Comparative Example 3: Compared with Example 1, the difference is that the doped layer and electrode 400 are directly covered above the intrinsic absorption layer of germanium, and the incident light signal must pass through the physical covering structure such as electrode 400 and doped layer to reach the intrinsic absorption region. Otherwise, they are the same.

[0056] Test Examples 1-4: Test Example 1: This experiment selected four groups of surface-incident silicon-based germanium detectors (referred to as test sample 1 and example samples 2 to 4) prepared based on the method of the embodiments, but with different structural size parameters, as test objects.

[0057] Using a high-powered microscope, each detector sample is fixed on the constant-temperature test stage of the high-frequency probe station. The three-dimensional fine-tuning frame is adjusted so that the high-frequency microwave probe is accurately inserted into the electrode 400 above the outer ring doped region 310 and the inner ring doped region 131. An external DC source is connected and a reverse bias voltage of -1V is applied.

[0058] Turn on the tunable laser, set the output light signal wavelength to 1310nm, and use a single-mode fiber to irradiate the intrinsic absorption region (germanium lateral epitaxial region 300) directly above the detector with continuous light perpendicularly. Use an optical power meter to monitor the absolute optical power at the input end.

[0059] Record the output photocurrent value fed back by the DC source meter, according to the formula. Calculate the absolute response of samples of different sizes.

[0060] By switching the light source system, a microwave beat frequency optical signal at different frequency points is generated using an optical heterodyne testing system and input into the intrinsic absorption region. The high-frequency electrical signal received at the probe end is connected to a frequency response analyzer. The RF response power variation curve from DC to 250 GHz is scanned and recorded. The frequency point corresponding to the response power dropping to half of the peak value (i.e., a 3 dB drop) is extracted as the measured 3 dB bandwidth. Finally, this is compared with the theoretical formula that ignores the RC delay effect and only considers the transit time limitation. The comparison confirmed the decoupling effect.

[0061] Table 1. Photoelectric performance test data of incident silicon-based germanium detectors with different structural sizes

[0062] According to Table 1 and Figure 4 Changes in the physical structure dimensions directly impact the optoelectronic performance of the device. In traditional device design, increasing the thickness of the absorption layer often leads to a prolonged carrier drift time, thus limiting the microwave response rate. In this test, the lateral PIN structure alters this constraint. Observation of the device's internal structure reveals that the thickness of the top silicon layer primarily determines the vertical depth of the intrinsic germanium absorption layer, ensuring sufficient absorption path for the incident light. Comparing the results of test sample 1 and example sample 3, when the top silicon thickness increases from 502.4 nm to 805.2 nm, the absolute responsivity increases from 0.856 A / W to 0.912 A / W due to the corresponding increase in internal quantum conversion efficiency. On the other hand, tests on high-frequency response characteristics show that, since the direction of the internal electric field is perpendicular to the incident light direction, carriers are transported by the lateral electric field between the inner doped region 131 and the outer doped region 310. This design makes the width of the lateral intrinsic layer the primary factor determining the transit time. Specifically, based on the data from sample 2 of the embodiment, when the lateral width of the intrinsic absorption layer is reduced to approximately 203.8 nm, the device achieves a measured 3dB bandwidth of 214.3 GHz while maintaining a responsivity of 0.811 A / W. Furthermore, the lateral structural confinement during the early crystal epitaxy process guides lattice-mismatched dislocations to terminate at the dielectric interface, which to some extent improves the crystal quality in the intrinsic region and reduces lattice scattering of charge carriers during high-speed transmission. By physically separating the longitudinal light absorption volume and the lateral carrier drift distance in three-dimensional space, designers can adjust the depth and width parameters according to specific performance requirements, thereby providing a hardware solution for optoelectronic transceiver modules that balances responsivity and bandwidth.

[0063] Test Example 2: This experiment selected three groups of surface-incidence silicon-based germanium detectors with different intrinsic layer lateral widths (Example samples A to C) and three groups of surface-incidence detectors with conventional vertical PIN structures (Comparative Example 1 samples A to C) as test objects.

[0064] The sample from the example and the sample from Comparative Example 1 were fixed on the sample tray of the probe station, respectively. The high-frequency microwave probe was adjusted to accurately penetrate the electrode pad. An external DC power supply was connected and the bias voltage was set to -1V.

[0065] A tunable laser with a wavelength of 1310nm was used as the light source. Continuous light was vertically aligned with the photosensitive surface directly above each detector through a single-mode fiber. The input light power was monitored synchronously and the source meter feedback current was read. Based on this, the absolute responsivity value of the sample was derived and recorded.

[0066] Replace the light source with a microwave beat frequency optical testing system, input the light wave carrying the high-frequency modulation signal into the intrinsic absorption region of the detector on the wafer, connect the probe output to a frequency response analyzer, scan the frequency range and extract the specific frequency point when the response power drops by 3dB, and obtain the measured bandwidth value.

[0067] Table 2. Comparison of photoelectric performance test data between Example 1 and Comparative Example 1

[0068] According to Table 2 and Figure 5 The differences in structural design directly lead to differences in the optoelectronic properties of the devices. The test data for Comparative Example 1 illustrates the limitations inherent in traditional vertical structures. In the parameter settings of Comparative Example 1 sample C, increasing the vertical absorption layer thickness to 813.4 nm resulted in an absolute responsivity of 0.915 A / W, but also increased the time required for carriers to cross the intrinsic region in the electric field, causing the measured bandwidth to drop to 45.7 GHz. Since the photon incident direction and carrier drift direction coincide in conventional structures, this physical correlation limits the device's application in high-speed communication scenarios. In contrast, the lateral PIN layout spatially separates the light absorption volume from the carrier transit path. The test records show that Example A achieved a responsivity of 0.823 A / W with a top silicon thickness of 505.2 nm; simultaneously, by controlling the width of its lateral epitaxial region to 206.5 nm, the carrier drift time was significantly shortened, and the measured bandwidth was 211.5 GHz. Further investigation into the impact of thickness variation on bandwidth revealed that, in the testing of sample C in this embodiment, the top silicon thickness was increased to 795.8 nm to improve device responsivity. Due to strict control over the span of the lateral intrinsic region, the microwave bandwidth remained at 153.2 GHz. By altering the coupling relationship of the optoelectronic parameters, the device was able to maintain a high high-frequency carrier transport rate while preserving photon absorption, providing a certain reference for the design of optical communication hardware.

[0069] Test Example 3: This experiment selected multiple groups of surface incident detectors (example samples) prepared based on the template-assisted selective epitaxy of the present invention and surface incident detectors prepared by direct heteroepitaxial epitaxy of germanium on silicon (comparative example 2 sample) as test objects.

[0070] The test wafer is placed in the vacuum chamber of the semiconductor parameter test stage equipped with a metal shielding box. The chamber door is closed to block all external natural light sources and indoor lighting, ensuring that the test system is under strict dark conditions.

[0071] Using a three-dimensional micromanipulator to manipulate the tungsten needle tip, the electrode pads at both ends of the contact device are secured, and the probe coaxial cable is connected to the source measurement unit of a high-precision semiconductor parameter analyzer.

[0072] Set the reverse bias voltage scan range to 0V to -3V on the analyzer control panel, set the sampling step to -0.1V, and start the voltage scan test program.

[0073] The absolute value of the reverse leakage current recorded inside the parameter analyzer was extracted, and multiple sets of device test results were sorted out and abnormal abrupt changes caused by poor probe contact were removed. The dark current characteristic data were then obtained.

[0074] Table 3. Comparison of Dark Current Characteristics Test Data between Example 1 and Comparative Example 2

[0075] According to Table 3 and Figure 6 The dark current of devices using different epitaxial processes exhibits magnitude differences. In the structure of Comparative Example 2, the germanium layer is directly grown heteroepitaxially over a large area on the silicon substrate 110. Due to the lack of stress relief and defect control structures, lattice mismatch dislocations at the interface extend along the crystal growth direction. These penetrating dislocations through the intrinsic absorption layer form internal leakage channels. Tests showed that the dark current of Comparative Example 2 was 89.3 nA at a bias voltage of -1V, and reached 314.5 nA when the bias voltage was increased to -3V. This leakage characteristic affects the signal-to-noise ratio of the detector under weak light conditions. In contrast, after introducing a silicon oxide template for selective area confinement, the reverse leakage current of the example sample decreased under the same bias voltage conditions, with a measured dark current of 2.4 nA at -1V. This improvement in dark current characteristics is mainly due to the confinement effect of the structure on crystal defects. Within the lateral growth space, dislocations generated at the germanium-silicon interface slide under the pull of the surrounding dielectric layer, eventually terminating at the interface between the silicon oxide template and the buried oxide layer 120. Because the main leakage path is blocked by the physical interface, the material integrity of the detector's intrinsic region is preserved, thereby improving the device's ability to detect weak light signals while ensuring response performance.

[0076] Test Example 4: This experiment selected a surface-incident detector (example sample) fabricated based on a transverse PIN structure with no obstruction above the intrinsic absorption region, and a detector (comparative example 3 sample) using a conventional longitudinal PIN structure with the top partially obscured by a doped layer and a ring electrode 400 as test objects.

[0077] The wafer with two types of detector samples fixed on it is placed on a high-frequency anti-vibration optical platform. The micron-level three-dimensional displacement stage is adjusted so that the single-mode fiber optic probe is vertically aligned with the center of the detector's light-receiving surface.

[0078] The detector surface pads are connected to a precision DC power supply using a high-frequency microwave probe, and a -1V operating bias voltage is set. Simultaneously, the tunable laser is activated, locking the output continuous light wavelength to the 1310nm communication band, and a high-precision optical variable attenuator is connected in series in the optical path.

[0079] By gradually adjusting the knob of the optical variable attenuator, the absolute optical power incident on the detector surface is changed, and the accurate optical power value at the input end is monitored and recorded synchronously using a spectrometer.

[0080] After stabilizing the illumination conditions, the magnitude of the DC photocurrent generated and output by the detector is read in real time using a precision source meter, and the photoelectric conversion data under different input powers are summarized.

[0081] Table 4. Comparison of unobstructed light absorption characteristics between Example 1 and Comparative Example 3: Test data

[0082] According to Table 4 and Figure 7 Different detector structures exhibit varying current conversion efficiencies under optical signal illumination. In the traditional vertical architecture, as shown in Comparative Example 3, the device is covered by a doped layer and a metal contact ring. Incident photons must pass through these surface structures before reaching the intrinsic germanium absorption region at the bottom. Absorption of free carriers within the doped region, lattice scattering, and the physical shielding by the metal electrode 400 all reduce the transmitted light intensity. Test data shows that at an input optical power of 3.12 mW, the photocurrent generated by the Comparative Example 3 sample was 1.516 mA, indicating that some light energy was not effectively converted into an output electrical signal. In contrast, the embodiment structure distributes the inner doped region 131, the outer doped region 310, and the lead-out electrode 400 on the horizontal plane where the germanium lateral epitaxial region 300 is located. In this unshielded structure, incident light with a wavelength of 1310 nm can directly reach the intrinsic core region, reducing transmission losses in the surface dielectric layer. Under the same input condition of 3.12 mW, the photocurrent measured in the embodiment sample reached 2.628 mA. By avoiding physical obstruction and additional absorption losses from the top structure, the optical signal conversion efficiency of the device is improved accordingly.

Claims

1. A high performance face-incident silicon-germanium detector structure, characterized by, include: SOI substrate (100), the SOI substrate (100) includes, from bottom to top, a silicon substrate (110), a buried oxide layer (120) and an inner doped region (131), the inner doped region (131) being formed by local etching of the top silicon layer of the SOI substrate (100); A silicon oxide template layer (200) is disposed above the inner ring doped region (131), and the portion of the silicon oxide template layer (200) not supported by the inner ring doped region (131) is suspended above the buried oxide layer (120), forming a semi-suspended state; The germanium lateral epitaxial region (300) is located between the buried oxide layer (120) and the silicon oxide template layer (200) in a semi-suspended state, and is laterally connected to the inner ring doped region (131); the germanium lateral epitaxial region (300) includes an intrinsic germanium absorption layer and an outer ring doped region (310), which are arranged sequentially with the inner ring doped region (131) in the horizontal direction to form a lateral PIN structure; The electrode (400) penetrates the silicon oxide template layer (200) in the corresponding region and forms an electrical connection with the top surface of the inner ring doped region (131) and the top surface of the outer ring doped region (310), respectively.

2. The high performance face incidence silicon-germanium photodetector structure of claim 1, wherein, The thickness of the inner doped region (131) is 220 nm to 2 μm; The inner ring doped region (131) is made of doped single-crystal silicon.

3. The high performance face incidence silicon-germanium photodetector structure of claim 1, wherein, The thickness of the silicon oxide template layer (200) is 200 nm to 1 μm.

4. The high performance face incidence silicon-germanium photodetector structure of claim 1, wherein, The total lateral width of the germanium lateral epitaxial region (300) is 600 nm to 1.5 μm.

5. A preparation method of high-performance face incidence silicon germanium detector structure, applied to the high-performance face incidence silicon germanium detector structure of any one of claims 1-4, characterized in that, Includes the following steps: First, an SOI substrate (100) consisting of a silicon substrate (110), a buried oxide layer (120), and a top silicon layer is prepared, wherein the top silicon layer is doped to make the top silicon layer doped. Next, silicon oxide is deposited on the top silicon layer to obtain a silicon oxide template layer (200). Then, the mesa structure of the stacked top silicon and the silicon oxide template layer (200) is etched out; Subsequently, selective etching back is performed on the top silicon layer to obtain the inner doped region (131), and the unsupported portion of the silicon oxide template layer (200) is made to form a semi-suspended state; Subsequently, using the inner ring doped region (131) as a seed crystal, germanium is laterally epitaxially grown between the buried oxide layer (120) and the silicon oxide template layer (200) to obtain a germanium lateral epitaxial region (300), and an outer ring doped region (310) is formed to obtain a complete PIN structure. Next, the silicon oxide template layer (200) above the outer ring doped region (310) and the inner ring doped region (131) is etched to form electrode holes; Finally, metal is deposited inside the electrode hole to form an electrical connection with the inner ring doped region (131) and the outer ring doped region (310) respectively, to obtain the electrode (400), thereby obtaining the high-performance surface-incident silicon-based germanium detector structure.

6. The method of claim 5, wherein the method further comprises: In the step of obtaining a silicon oxide template layer (200) by depositing silicon oxide, a layer of the silicon oxide template layer (200) is deposited on the top silicon layer by plasma chemical vapor deposition, low-pressure chemical deposition or atmospheric pressure chemical deposition process.

7. The method of claim 5, wherein the method further comprises: In the step of selectively etching back the top silicon layer, the etching solution used is tetramethylammonium hydroxide solution, potassium hydroxide solution, or ethylenediamine-catechol solution; When a tetramethylammonium hydroxide solution is selected, the mass fraction of the tetramethylammonium hydroxide solution is 25%, and the temperature of the corrosive environment is 70℃~90℃.

8. The method of claim 5, wherein the method further comprises: In the step of obtaining the germanium lateral epitaxial region (300) by lateral epitaxy of germanium, the lateral epitaxy of germanium is performed by ultra-high vacuum chemical vapor deposition process, low pressure chemical vapor deposition process or metal-organic chemical vapor deposition process.

9. The method of claim 5, wherein the method further comprises: The step of forming the outer ring doped region (310) is achieved in any of the following ways: Before the lateral epitaxial germanium is completed, a doping source is introduced to perform in-situ doping; Alternatively, doping can be achieved through ion implantation after the germanium lateral epitaxy is completed.

10. The method of claim 5, wherein the method further comprises: In the step of depositing metal inside the electrode hole and forming an electrical connection with the inner ring doped region (131) and the outer ring doped region (310) respectively to obtain the electrode (400), the electrode (400) is deposited by electron beam evaporation, magnetron sputtering or thermal evaporation. The electrode (400) is made of a combination of Ni and Al, a combination of Ti and Au, a combination of Cr and Au, or elemental Al.

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