Simultaneous diversity signal real-time detection method

Abstract

The application discloses a simultaneous diversity signal real-time detection method, and belongs to the technical field of radar signal reconnaissance. The method comprises the following steps: S1, full-channel signal detection and parameter measurement; S2, hierarchical cache management of pulse description words; S3, matching detection and fusion processing of the simultaneous diversity signal; and S4, data re-caching and detection circulation. The simultaneous diversity signal real-time detection and measurement method can solve the technical problem that a traditional digital channelization radar reconnaissance receiver is difficult to rapidly and effectively detect the simultaneous diversity signal in real time. Through the core design of hierarchical cache management, fixed reference matching fusion and closed-loop circulation detection, the method realizes accurate and real-time detection and parameter extraction of the simultaneous diversity signal, and has excellent engineering realizability and scene adaptability. The method realizes breakthroughs in signal detection performance, processing real-time performance, hardware landing performance and engineering practicability, and greatly improves the signal processing capability of the radar reconnaissance system in a complex electromagnetic environment.

Description

Technical Field

[0001] This invention relates to the field of radar signal reconnaissance technology, and more specifically, to a method for real-time detection of simultaneous diversity signals. Background Technology

[0002] In the field of modern electronic warfare, the competition between radars continues to escalate. Radar signal reconnaissance is a core and fundamental component of radar countermeasure systems. Its ability to detect radar signals in real time, measure parameters accurately, and identify their types is a crucial prerequisite for radar jammers to effectively interfere with enemy radars. To counter enemy jamming, various radar waveforms with anti-jamming capabilities are widely used. Among them, simultaneous diversity signals, with their excellent anti-jamming performance, have become a commonly used waveform system in advanced radar systems.

[0003] The simultaneous diversity signal refers to a radar simultaneously transmitting multiple pulse signals at different carrier frequencies. These signals have multiple sub-pulses with consistent arrival times, pulse widths, pulse amplitudes, intra-pulse modulation methods, and modulation bandwidths, differing only in their carrier frequencies. By employing this multi-carrier frequency simultaneous transmission diversity method, this type of signal can significantly reduce the interception probability and jamming effectiveness of radar jammers, posing a serious challenge to the signal detection capabilities of traditional radar reconnaissance receivers.

[0004] Current mainstream radar reconnaissance systems generally adopt a digital channelized receiver architecture. Traditional digital channelized signal detection and measurement methods only process independent pulse signals within a single channel, generating pulse descriptors for each intercepted pulse as an independent radar signal. This makes it difficult to accurately and in real-time correlate and identify simultaneous, co-originating sub-pulses that cross channels. When processing simultaneous diversity signals using this traditional method, it is impossible to determine whether multiple intercepted pulses belong to the same group of simultaneous diversity signals. It cannot output a simultaneous diversity signal presence indicator, nor can it accurately extract key characteristic parameters such as the number of sub-pulses, the carrier frequency of each sub-pulse, and the frequency difference between sub-pulses. As a result, radar jammers cannot formulate matching jamming strategies for such signals, severely weakening the jamming effect against radars using simultaneous diversity signals.

[0005] In addition, the few existing detection schemes for simultaneous diversity signals generally suffer from high computational complexity, long processing delays, and high hardware resource consumption, making it difficult to implement in engineering on embedded hardware platforms such as FPGAs. They cannot meet the application requirements of modern radar reconnaissance systems for real-time signal processing, high reliability, and miniaturization. At the same time, the number of simultaneous diversity signal sub-pulses that can be adapted is limited, making it difficult to cover the mainstream application needs in actual reconnaissance scenarios. Summary of the Invention

[0006] The purpose of this invention is to provide a method for real-time detection of simultaneous diversity signals to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] Simultaneous diversity signal real-time detection method includes the following steps:

[0009] Step S1, Full-channel signal detection and parameter measurement: Down-convert the radio frequency signal received by the radar reconnaissance receiver and perform sampling and digital channelization processing. Perform signal detection and parameter measurement on the output data of each channel to generate a pulse description word (PDW) corresponding to each single pulse signal.

[0010] Step S2, Hierarchical Buffer Management of Pulse Description Words: Set up three sets of first-in-first-out (FIFO) buffers: a first FIFO for storing PDWs to be processed, a second FIFO for storing PDWs that do not meet the fusion conditions in the current round of detection, and a third FIFO for storing newly input PDWs when the simultaneous diversity detection fusion module is processing data; according to the working status of the simultaneous diversity detection fusion module, the PDWs generated in real time in step S1 are buffered in a split manner: if the simultaneous diversity detection fusion module is processing data, the newly generated PDW is stored in the third FIFO; if the simultaneous diversity detection fusion module is idle, the newly generated PDW is stored in the first FIFO;

[0011] Step S3: Simultaneous diversity signal matching detection and fusion processing: When the first PDW is written into the first FIFO, the simultaneous diversity detection and fusion module remains idle and starts a buffer time counter. When the count reaches the preset buffer time Time0, the simultaneous diversity detection and fusion module is set to the data processing state and stops writing newly generated PDWs into the first FIFO. The preset buffer time Time0 is no greater than the arrival time tolerance of the simultaneous diversity signal, which is used to ensure that all sub-pulses of the same group of simultaneous diversity signals are buffered. Read all PDW data in the first FIFO, take the first read PDW as a fixed and unique reference PDW, and record the arrival time of the reference PDW as t0. Sequentially match all the remaining PDWs in the first FIFO with the reference PDW for fusion conditions. For PDWs that meet the fusion conditions, they are fused together with the reference PDW to generate the PDW corresponding to the simultaneous diversity signal and output it. For PDWs that do not meet the fusion conditions, they are stored in the second FIFO. This continues until all PDWs in the first FIFO have completed the fusion condition matching judgment with the reference PDW.

[0012] Step S4, Data Re-buffering and Detection Loop: After all PDWs in the first FIFO have been processed, all PDWs in the second FIFO are read sequentially and written to the first FIFO in the reading order. The arrival time of the first read PDW in the second FIFO is recorded as t1. After the second FIFO is cleared, all PDWs in the third FIFO are read sequentially and written to the first FIFO in the reading order. After both the second and third FIFOs are cleared, the simultaneous diversity detection and fusion module is set to an idle state, and the process jumps to step S3 to execute the next round of simultaneous diversity signal detection.

[0013] Preferably, the PDW generated in step S1 includes seven core parameters: carrier frequency RF, pulse width PW, time of arrival TOA, pulse amplitude PA, intra-pulse modulation method, modulation bandwidth BW, and angle of arrival AOA.

[0014] Preferably, the matching criterion for the fusion condition in step S3 is as follows: the difference in arrival time (TOA), pulse width (PW), pulse amplitude (PA), modulation bandwidth (BW), and angle of arrival (AOA) between the PDW to be matched and the reference PDW are all less than the independently preset tolerance thresholds for each parameter, and the intra-pulse modulation methods of the PDW to be matched and the reference PDW are completely consistent; a PDW that meets all of the above conditions is determined to meet the fusion condition.

[0015] Preferably, in step S3, the specific method for fusing the PDW that meets the fusion conditions with the reference PDW is as follows:

[0016] For the reference PDW participating in the fusion and all PDWs that meet the fusion conditions, the average values ​​of their time of arrival (TOA), pulse width (PW), pulse amplitude (PA), modulation bandwidth (BW), and angle of arrival (AOA) are calculated to generate the TOA, PW, PA, BW, and AOA parameters corresponding to the simultaneous diversity signal PDW.

[0017] The carrier frequency RF of all PDWs participating in the fusion is retained as the multi-carrier frequency parameter of the simultaneous diversity signal PDW;

[0018] Modify the intra-pulse modulation mode parameter to the simultaneous diversity signal type, and update the sub-pulse number parameter in the simultaneous diversity signal PDW according to the total number of PDWs participating in the fusion.

[0019] Preferably, in step S3, when the preset buffer time Time0 is reached, if there is only one PDW data in the first FIFO when it is read, the PDW data is directly output, and the simultaneous diversity detection and fusion module is set to idle state, and the process jumps to step S4 to execute the data re-buffering process.

[0020] Preferably, in step S4, when reading the PDW in the second FIFO, if there are multiple PDWs in the second FIFO, the difference Δt between the arrival time of each subsequent PDW and t1 is calculated; if there is only one PDW in the second FIFO, the difference between t1 and the arrival time t0 of the reference PDW in step S3 is used as Δt; when reading the PDW in the third FIFO, the difference Δt between the arrival time of each PDW in the third FIFO and t1 is calculated; the next round of buffer time counting is based on Δt as the starting basis for time offset.

[0021] Preferably, in the single fusion processing of step S3, the parameter width for recording the number of sub-pulses is 4 bits, and the maximum number of sub-pulses of the diversity signal that can be processed simultaneously is 16.

[0022] Preferably, the entire process of signal detection, parameter measurement, buffer management, fusion matching and cyclic scheduling logic of the method is implemented in parallel by field-programmable gate array (FPGA) hardware.

[0023] A real-time detection and measurement device for simultaneous diversity signals, applied to a digital channelized radar reconnaissance receiver, includes:

[0024] The full-channel detection module is used to sample and digitally channelize the radio frequency signals received by the radar reconnaissance receiver, perform signal detection and parameter measurement on the output data of each channel, and generate a pulse description word (PDW) corresponding to each single pulse signal.

[0025] The hierarchical caching module has three built-in first-in-first-out (FIFO) buffers: a first FIFO for storing PDWs to be processed, a second FIFO for storing PDWs that do not meet the fusion conditions in the current round of detection, and a third FIFO for storing newly input PDWs when the simultaneous diversity detection and fusion module is processing data. The hierarchical caching module also performs split-buffering of PDWs generated in real time by the full-channel detection module according to the operating status of the simultaneous diversity detection and fusion module: if the simultaneous diversity detection and fusion module is processing data, the newly generated PDW is stored in the third FIFO; if the simultaneous diversity detection and fusion module is idle, the newly generated PDW is stored in the first FIFO.

[0026] The simultaneous diversity detection and fusion module is used to maintain an idle state and start a buffer time counter when the first PDW is written to the first FIFO; when the count reaches the preset buffer time Time0, it is set to the data processing state and stops writing newly generated PDWs to the first FIFO; the preset buffer time Time0 is no greater than the arrival time tolerance of the simultaneous diversity signal, which is used to ensure that all sub-pulses of the same group of simultaneous diversity signals are buffered; all PDW data in the first FIFO are read, and the first read PDW is used as a fixed and unique reference PDW, and the arrival time of the reference PDW is recorded as t0; all the remaining PDWs in the first FIFO are sequentially matched with the reference PDW for fusion conditions; for PDWs that meet the fusion conditions, they are fused together with the reference PDW to generate the PDW corresponding to the simultaneous diversity signal and output it; for PDWs that do not meet the fusion conditions, they are stored in the second FIFO; until all PDWs in the first FIFO have completed the fusion condition matching judgment with the reference PDW.

[0027] The cyclic scheduling module is used to read all PDWs in the second FIFO sequentially and write them back to the first FIFO in the order of reading after all PDWs in the first FIFO have been processed, and to record the arrival time of the first read PDW in the second FIFO as t1; after the second FIFO is cleared, it reads all PDWs in the third FIFO sequentially and writes them back to the first FIFO in the order of reading; after both the second and third FIFOs are cleared, the simultaneous diversity detection and fusion module is set to an idle state and triggered to execute the next round of simultaneous diversity signal detection.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] (1) The simultaneous diversity signal real-time detection and measurement method proposed in this application addresses the technical pain point that traditional digital channelized radar reconnaissance receivers are unable to detect simultaneous diversity signals accurately and effectively in real time. Through hierarchical buffer management, the addition of fully utilizing the intra-pulse modulation style in PDW parameters, the matching and fusion of modulation parameters, and closed-loop cyclic detection, the method achieves accurate and real-time detection and parameter extraction of simultaneous diversity signals. It also has excellent engineering feasibility and scenario adaptability. It achieves breakthroughs in signal detection performance, real-time processing, hardware implementation, and engineering practicality, and greatly improves the signal processing capability of radar reconnaissance systems in complex electromagnetic environments.

[0030] (2) It breaks through the limitation of traditional radar reconnaissance receivers that can only process single-channel independent pulse signals. By using the fusion condition matching rules of a fixed and unique reference PDW, it can accurately identify simultaneous diversity signals from the same source in different channels. It can not only provide the existence of simultaneous diversity signals, but also extract key characteristic parameters such as the number of sub-pulses, multi-carrier frequency, and frequency difference. The averaging of parameters such as TOA, PW, and AOA during the fusion process further improves the measurement accuracy of signal parameters, providing accurate signal basis for radar jammers to formulate targeted jamming strategies. It effectively solves the problems of failure of simultaneous diversity signal detection and low jamming effectiveness of traditional methods.

[0031] (3) A hierarchical caching management strategy with three FIFOs is adopted to realize real-time diversion and caching of PDW data, avoiding the blocking problem of newly generated data during the detection process. Combined with the closed-loop logic of cache timing trigger and cyclic detection of unfused data, it can ensure that all sub-pulses of the same group of simultaneous diversity signals are cached by presetting Time0, and can also include PDWs that do not meet the fusion conditions in the current round into the next round of detection, without data loss. It is suitable for multi-pulse and high-dynamic signal reception scenarios in complex electromagnetic environments, and the stability and robustness of the detection process are significantly improved. The core detection and fusion algorithm of this scheme has low computational load and simple processing steps. It only implements the core functions through basic parameter difference judgment, average value calculation and data cache scheduling, without complex iterative calculations. At the same time, the whole process is implemented in parallel based on FPGA hardware, with short processing delay and high data interaction efficiency, which far meets the real-time requirements of modern radar reconnaissance for signal processing. It can achieve near real-time detection and parameter output of simultaneous diversity signals. Detailed Implementation

[0032] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0033] Example 1: Real-time Detection and Measurement Method for Simultaneous Diversity Signals

[0034] The simultaneous diversity signal real-time detection and measurement method disclosed in this embodiment is applied to a digital channelized radar reconnaissance receiver. It can solve the technical problems of traditional radar reconnaissance methods being unable to identify simultaneous diversity signals and having poor real-time processing performance. It realizes real-time detection, parameter fusion and output of simultaneous diversity radar signals, and specifically includes the following steps:

[0035] S1 Full-Channel Signal Detection and Parameter Measurement

[0036] After receiving the radio frequency signal emitted by the enemy radar, the radar reconnaissance receiver first performs high-speed analog-to-digital (A / D) sampling on the intermediate frequency signal after down-conversion of the radio frequency signal, converting the analog radio frequency intermediate frequency signal into a digital signal; then, it performs digital channelization processing on the digital signal, dividing the wide-band digital signal into multiple narrow-band channels to achieve full-band instantaneous bandwidth signal coverage reception.

[0037] For each narrowband channel output digital signal, signal detection operations such as energy detection and pulse extraction are performed sequentially, along with parameter measurement operations, to generate a pulse descriptor word (PDW) for each extracted single-pulse signal. In this embodiment, each PDW contains seven core parameters: carrier frequency (RF), pulse width (PW), time of arrival (TOA), pulse amplitude (PA), intra-pulse modulation method (such as linear frequency modulation, phase coding, etc.), modulation bandwidth (BW), and angle of arrival (AOA).

[0038] Example description: The PDW parameters of a certain pulse signal are: RF=10GHz, PW=8μs, TOA=156234500μs, PA=-20dBm, intra-pulse modulation mode=linear frequency modulation, BW=50MHz, AOA=10º.

[0039] Hierarchical caching management of S2 pulse descriptors

[0040] To achieve real-time splitting and caching of the PDW, this embodiment sets up three independent First-In-First-Out (FIFO) buffers. The functional division of each FIFO is as follows:

[0041] First FIFO: Dedicated to storing PDWs to be simultaneously diversity matching and detection;

[0042] Second FIFO: Dedicated to storing PDWs that do not meet the fusion conditions in the current round of detection and need to enter the next round of detection;

[0043] The third FIFO is dedicated to storing newly generated PDWs when the diversity detection fusion module is in the "processing data state".

[0044] Simultaneously, the diversity detection and fusion module has two working states: "idle state" and "data processing state". This step performs splitting and caching of the PDW generated in real time in S1 based on the current state of the simultaneous diversity detection and fusion module:

[0045] If the diversity detection fusion module is in "processing data status" at the same time, the newly generated PDW will be stored in the third FIFO;

[0046] If the diversity detection fusion module is in an "idle state" at the same time, the newly generated PDW will be stored in the first FIFO.

[0047] S3 Matching detection and fusion processing of simultaneous diversity signals

[0048] This step is the core of achieving simultaneous diversity signal detection, and specifically includes three sub-steps: buffer timing, fusion condition matching, and PDW fusion processing.

[0049] 3.1 Cache timing

[0050] When the first PDW is written into the first FIFO, the diversity detection and fusion module remains in an "idle state" and a high-precision cache time counter is started. When the counter value reaches the preset cache time Time0, the diversity detection and fusion module is set to "processing data state" and writing new PDWs into the first FIFO stops.

[0051] The preset buffer time Time0 is not greater than the arrival time tolerance of the simultaneous diversity signal (in this embodiment, Time0 is 80.2μs and the arrival time tolerance of the simultaneous diversity signal is 0.2μs), ensuring that all sub-pulses of the same group of simultaneous diversity signals can be buffered in the first FIFO.

[0052] 3.2 Fusion Condition Matching Detection

[0053] After the buffer timer expires, all PDW data in the first FIFO is read, and the first PDW read is selected as the "fixed and unique reference PDW," with its arrival time recorded as t0. The remaining PDWs in the first FIFO are then matched with the reference PDW according to the following fusion criteria:

[0054] The TOA difference between the PDW to be matched and the benchmark PDW is <0.2μs (TOA tolerance threshold).

[0055] The difference in PW between the PDW to be matched and the reference PDW is <0.2μs (PW tolerance threshold).

[0056] The PA difference between the PDW to be matched and the reference PDW is <3dBm (PA tolerance threshold).

[0057] The difference in BW between the PDW to be matched and the reference PDW is <0.2MHz (BW tolerance threshold).

[0058] The difference in AOA between the PDW to be matched and the benchmark PDW is <3º (AOA tolerance threshold).

[0059] The intra-pulse modulation scheme of the PDW to be matched is completely consistent with that of the reference PDW.

[0060] Only PDWs that simultaneously meet the above 6 conditions are deemed to meet the fusion conditions; if only 1 PDW exists when reading the first FIFO, then the PDW is directly output, the simultaneous diversity detection fusion module is set to "idle state", and the process jumps to step S4.

[0061] 3.3 PDW Fusion Processing

[0062] The PDW that meets the fusion criteria is fused with the reference PDW to generate a fused PDW representing the simultaneous diversity signal. The specific method is as follows:

[0063] For all PDWs participating in the fusion, calculate the average values ​​of TOA, PW, PA, and BW respectively, and use them as the corresponding parameters for the fused PDWs;

[0064] All RFs involved in the fused PDW are retained to form the multi-carrier frequency parameters of the fused PDW;

[0065] The intra-pulse modulation method is modified to "simultaneous diversity signal," and the "number of sub-pulses" parameter of the fused PDWs is updated according to the total number of PDWs participating in the fusion. In this embodiment, the number of sub-pulses parameter is stored in a 16-bit register, with 4 bits being valid. Therefore, the maximum number of sub-pulses that can be recorded in a single fusion process is [value missing]. One, which can cover the number of subpulses required for simultaneous diversity signals of mainstream radars.

[0066] Example description: After fusing the baseline PDW (RF=10GHz, TOA=156234500μs, PW=8μs, AOA=10º) with two qualified PDWs (PDW1: RF=10.1GHz, TOA=156234500.1μs, PW=8.05μs, AOA=11º; PDW2: RF=9.9GHz, TOA=156234499.9μs, PW=8.1μs, AOA=9º), the average TOA of the fused PDW is 156234500μs, the average PW is 8.05μs, the average AOA is 10º, the multi-carrier frequencies are 10GHz, 10.1GHz, and 9.9GHz, and the number of sub-pulses is 3.

[0067] After the PDWs that meet the fusion conditions are fused, the fused PDW is output. PDWs that do not meet the conditions are stored in the second FIFO until all PDWs in the first FIFO have been matched.

[0068] S4 Data Recaching and Detection Loop

[0069] After all PDWs in the first FIFO have been processed, perform the following operations:

[0070] Read all PDWs in the second FIFO sequentially and write them into the first FIFO in the order of reading. Record the arrival time of the first PDW read from the second FIFO as t1.

[0071] After the second FIFO is emptied, all PDWs in the third FIFO are read in sequence and written to the first FIFO in the order of reading.

[0072] After the second and third FIFOs are cleared, the simultaneous diversity detection fusion module is set to "idle state" and the process jumps to step S3 to start the next round of detection.

[0073] When reading from the second and third FIFOs, the time difference Δt needs to be calculated (used for the next round of buffer timing offset):

[0074] If the second FIFO has multiple PDWs, calculate the difference Δt between the TOA of the subsequent PDW and t1;

[0075] If the second FIFO has only one PDW, calculate the difference between t1 and the TOA(t0) of the reference PDW as Δt;

[0076] When reading the third FIFO, calculate the difference Δt between TOA and t1 for each PDW;

[0077] The next round of buffer timing will be based on Δt as the starting point of the time offset.

[0078] In this embodiment, the maximum number of simultaneous diversity signals compatible with a single fusion processing is 16. This value is limited by the 4-bit effective bit storage width of the sub-pulse number parameter in the FPGA, ensuring efficient utilization of parameter storage and hardware resources, while also adapting to the simultaneous diversity signal design requirements of mainstream radars. Furthermore, the entire method process (signal detection, buffer management, fusion matching, etc.) is implemented in parallel hardware using a Field Programmable Gate Array (FPGA), with an end-to-end signal processing delay ≤1000.5μs, meeting the real-time requirements of radar reconnaissance.

[0079] Example 2: Simultaneous diversity signal real-time detection and measurement device

[0080] Based on the same inventive concept as Embodiment 1, this embodiment discloses a device for real-time detection and measurement of simultaneous diversity signals, applied to a digital channelized radar reconnaissance receiver, which can realize the hardware implementation of the method described in Embodiment 1. The device includes the following functional modules:

[0081] 1. Full-channel detection module

[0082] The full-channel detection module is implemented by FPGA logic units. Its core functions are: to perform high-speed sampling and digital channelization processing on the radio frequency signals received by the radar reconnaissance receiver, to perform signal detection and parameter measurement on the output data of each channel, and to generate a PDW containing 7 types of core parameters.

[0083] The input of this module is the radio frequency digital signal from the radar receiver, and the output is a PDW data stream, which is directly transmitted to the hierarchical buffer module; the input of this module is the 16-bit radio frequency digital signal (sampling rate 2GSPS) from the radar receiver, and the output is a 32-bit wide PDW data stream, which is directly transmitted to the hierarchical buffer module through the internal AXI4 bus of the FPGA.

[0084] 2. Hierarchical caching module

[0085] The hierarchical caching module has three independent FIFO buffers (first FIFO, second FIFO, and third FIFO), with the same function as in Example 1. The core working logic is: to receive the PDW output by the full-channel detection module in real time, and to split and store the PDW into the corresponding FIFO according to the working status (idle / processing data) of the simultaneous diversity detection fusion module.

[0086] 3 Simultaneous diversity detection fusion module

[0087] The sub-pulse number parameter storage unit uses a 16-bit register, of which 4 bits are valid, and the maximum number of sub-pulses that can be recorded is 16, which is consistent with the upper limit of the single fusion processing capability. This hardware design directly determines the processing capacity of this device for simultaneous diversity signals.

[0088] Meanwhile, the diversity detection and fusion module is the core processing module of the device, and its function corresponds to step S3 in Embodiment 1:

[0089] Buffer timing: Receives the first FIFO write trigger signal, starts timing, and switches its own working state and stops writing to the first FIFO after Time0 is reached;

[0090] Matching detection: Read all PDWs in the first FIFO and complete the fusion condition matching based on the first PDW;

[0091] Fusion processing: PDWs that meet the conditions are merged and output, while PDWs that do not meet the conditions are written into the second FIFO.

[0092] 4. Loop Scheduling Module

[0093] The cyclic scheduling module function corresponds to step S4 in Example 1:

[0094] Data Re-caching: After the detection fusion module finishes processing the first FIFO, it reads the PDW of the second and third FIFOs in sequence and writes them into the first FIFO in order;

[0095] Status control: After the second and third FIFOs are cleared, the detection fusion module is set to "idle state" to trigger the next round of detection.

[0096] Time difference calculation and transmission: Simultaneously calculate the arrival time difference Δt of PDW in the second FIFO and the third FIFO, and transmit Δt to the simultaneous diversity detection fusion module as the starting basis for the time offset of the next round of buffer time counting. The calculation rule of Δt is the same as that in Example 1.

[0097] In this embodiment, the various modules of the device interact with each other through the high-speed internal bus of the FPGA, resulting in low overall resource consumption and low processing latency, making it suitable for application scenarios of miniaturized radar reconnaissance equipment.

[0098] Implementation effect

[0099] The method and apparatus of this application solve the technical problem that traditional radar reconnaissance methods cannot identify simultaneous diversity signals. Through core logic such as hierarchical buffering, fixed reference matching, and PDW fusion, real-time detection and parameter extraction of simultaneous diversity signals are achieved. The FPGA-based hardware implementation ensures real-time processing, and the compatibility with 16 sub-pulses covers mainstream application scenarios, possessing high engineering practical value. This solution is effective in complex electromagnetic environments (multiple signal superposition, high pulse density). At pulses / second, the end-to-end delay of signal processing is ≤1000.5μs, and the maximum number of simultaneous diversity signals that can be compatible with a single fusion processing is 16, covering the application requirements of simultaneous diversity signals of mainstream radars.

[0100] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for real-time detection of simultaneous diversity signals, characterized in that, Includes the following steps: S1. Full-channel signal detection and parameter measurement: The radio frequency signal received by the radar reconnaissance receiver is down-converted, sampled, and digitally channelized. The output data of each channel is subjected to signal detection and parameter measurement to generate a pulse descriptor word (PDW). S2. Hierarchical Buffer Management of Pulse Description Words: Three sets of first-in-first-out (FIFO) buffers are set up: a first FIFO for storing PDWs to be processed, a second FIFO for storing PDWs that do not meet the fusion conditions in the current round of detection, and a third FIFO for storing newly input PDWs when the simultaneous diversity detection fusion module is processing data; the real-time generated PDWs are buffered in a split manner according to the working status of the simultaneous diversity detection fusion module: if the simultaneous diversity detection fusion module is processing data, the newly generated PDWs are stored in the third FIFO; If the diversity detection fusion module is idle at the same time, the newly generated PDW will be stored in the first FIFO; S3. Simultaneous diversity signal matching detection and fusion processing: When the first PDW is written into the first FIFO, a buffer time counter is started; when the count reaches the preset buffer time Time0, the simultaneous diversity detection and fusion module is set to the data processing state, and writing PDWs to the first FIFO stops; wherein, the value of the preset buffer time Time0 is not greater than the arrival time tolerance of the simultaneous diversity signal; all PDW data in the first FIFO are read, and the first read PDW is used as a fixed and unique reference PDW, and the arrival time of the reference PDW is recorded as t0; all remaining PDWs in the first FIFO are sequentially matched with the reference PDW for fusion condition matching. The matching criteria for fusion conditions are as follows: the time of arrival (TOA), pulse width (PW), pulse amplitude (PA), modulation bandwidth (BW), and angle of arrival (AOA) differences between the PDW to be matched and the reference PDW are all less than the independently preset tolerance thresholds for each parameter, and the intra-pulse modulation methods of the PDW to be matched and the reference PDW are completely consistent; a PDW that meets all the above conditions is determined to meet the fusion conditions; for PDWs that meet the fusion conditions, they are fused together with the reference PDW to generate a PDW corresponding to the simultaneous diversity signal and output it; for PDWs that do not meet the fusion conditions, they are stored in the second FIFO; until all PDWs in the first FIFO have been judged. S4. Data Re-buffering and Detection Loop: After all PDWs in the first FIFO have been processed, all PDWs in the second FIFO are read sequentially and written to the first FIFO. The arrival time of the first read PDW in the second FIFO is recorded as t1. After the second FIFO is cleared, all PDWs in the third FIFO are read sequentially and written to the first FIFO. After both the second and third FIFOs are cleared, the simultaneous diversity detection and fusion module is set to an idle state, and the process jumps to step S3 to execute the next round of simultaneous diversity signal detection.

2. The method for real-time detection of simultaneous diversity signals according to claim 1, characterized in that: The PDW generated in step S1 includes seven core parameters: carrier frequency RF, pulse width PW, time of arrival TOA, pulse amplitude PA, intra-pulse modulation method, modulation bandwidth BW, and angle of arrival AOA.

3. The method for real-time detection of simultaneous diversity signals according to claim 1, characterized in that: In step S3, the specific method for fusing the PDW that meets the fusion conditions with the reference PDW is as follows: For the reference PDW participating in the fusion and all PDWs that meet the fusion conditions, the average values ​​of their time of arrival (TOA), pulse width (PW), pulse amplitude (PA), modulation bandwidth (BW), and angle of arrival (AOA) are calculated to generate the TOA, PW, PA, BW, and AOA parameters corresponding to the simultaneous diversity signal PDW. The carrier frequency RF of all PDWs participating in the fusion is retained as the multi-carrier frequency parameter of the simultaneous diversity signal PDW; Modify the intra-pulse modulation mode parameter to the simultaneous diversity signal type, and update the sub-pulse number parameter in the simultaneous diversity signal PDW according to the total number of PDWs participating in the fusion.

4. The method for real-time detection of simultaneous diversity signals according to claim 1, characterized in that: In step S3, when the preset buffer time Time0 is reached, if only one PDW data exists in the first FIFO when it is read, the PDW data is directly output, and the simultaneous diversity detection and fusion module is set to idle state, and the process jumps to step S4 to execute the data re-buffering process.

5. The method for real-time detection of simultaneous diversity signals according to claim 1, characterized in that: In step S4, when reading the PDW in the second FIFO, if there are multiple PDWs in the second FIFO, the difference Δt between the arrival time of each subsequent PDW and t1 is calculated; if there is only one PDW in the second FIFO, the difference between t1 and the arrival time t0 of the reference PDW mentioned in step S3 is used as Δt; when reading the PDW in the third FIFO, the difference Δt between the arrival time of each PDW in the third FIFO and t1 is calculated; the next round of buffer time counting is based on the time offset starting from Δt.

6. The method for real-time detection of simultaneous diversity signals according to claim 1, characterized in that: In the single fusion processing of step S3, the parameter width for recording the number of sub-pulses is 4 bits, and the maximum number of sub-pulses of the diversity signal that can be processed simultaneously is 16.

7. The method for real-time detection of simultaneous diversity signals according to claim 1, characterized in that: The entire process of signal detection, parameter measurement, buffer management, fusion matching, and cyclic scheduling logic of the method is implemented in parallel using a field-programmable gate array (FPGA).

8. A real-time detection and measurement device for simultaneous diversity signals, applied to a digital channelized radar reconnaissance receiver, characterized in that, include: The full-channel detection module is used to sample and digitally channelize the radio frequency signals received by the radar reconnaissance receiver, perform signal detection and parameter measurement on the output data of each channel, and generate a pulse description word (PDW) corresponding to each single pulse signal. The hierarchical caching module has three built-in first-in-first-out (FIFO) buffers: a first FIFO for storing PDWs to be processed, a second FIFO for storing PDWs that do not meet the fusion conditions in the current round of detection, and a third FIFO for storing newly input PDWs when the simultaneous diversity detection fusion module is processing data. The hierarchical caching module is also used to perform split caching of PDWs generated in real time by the full-channel detection module according to the working status of the simultaneous diversity detection fusion module: if the simultaneous diversity detection fusion module is processing data, the newly generated PDW is stored in the third FIFO. If the diversity detection fusion module is idle at the same time, the newly generated PDW will be stored in the first FIFO; The simultaneous diversity detection and fusion module is used to maintain an idle state and start a buffer time counter when the first PDW is written to the first FIFO; when the count reaches the preset buffer time Time0, it is set to the data processing state and stops writing newly generated PDWs to the first FIFO; wherein the value of the preset buffer time Time0 is not greater than the arrival time tolerance of the simultaneous diversity signal, and is used to ensure that all sub-pulses of the same group of simultaneous diversity signals are buffered; all PDW data in the first FIFO are read, and the first PDW read is used as a fixed and unique reference PDW, and the arrival time of the reference PDW is recorded as t0; all the remaining PDWs in the first FIFO are then conditionally matched with the reference PDW. The matching criteria for fusion conditions are as follows: the time of arrival (TOA), pulse width (PW), pulse amplitude (PA), modulation bandwidth (BW), and angle of arrival (AOA) differences between the PDW to be matched and the reference PDW are all less than the independently preset tolerance thresholds for each parameter, and the intra-pulse modulation methods of the PDW to be matched and the reference PDW are completely consistent; a PDW that meets all the above conditions is determined to meet the fusion conditions; for PDWs that meet the fusion conditions, they are fused together with the reference PDW to generate a PDW corresponding to the simultaneous diversity signal and output it; for PDWs that do not meet the fusion conditions, they are stored in the second FIFO; until all PDWs in the first FIFO have completed the fusion condition matching judgment with the reference PDW. The cyclic scheduling module is used to read all PDWs in the second FIFO sequentially and write them back to the first FIFO in the order of reading after all PDWs in the first FIFO have been processed, and to record the arrival time of the first read PDW in the second FIFO as t1; after the second FIFO is cleared, it reads all PDWs in the third FIFO sequentially and writes them back to the first FIFO in the order of reading; after both the second and third FIFOs are cleared, the simultaneous diversity detection and fusion module is set to an idle state and triggered to execute the next round of simultaneous diversity signal detection.