Processor, data processing method, chip, graphics card and electronic device

Abstract

The present disclosure provides a processor, a data processing method, a chip, a display card and an electronic device, and relates to the technical field of integrated circuits. The processor comprises an operation unit and a memory access channel. The operation unit is configured to send a data read-write request to the memory access channel. The data read-write request comprises data type conversion information. The memory access channel is configured to, in a case where it is determined according to the data type conversion information that data type conversion needs to be performed on original data, perform data type conversion on the original data according to the data type conversion information to obtain target data. The processor can perform corresponding data conversion processing on the memory access channel, and can reduce additional operations of the processor.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to a processor, a data processing method, a chip, a graphics card, and an electronic device. Background Technology

[0002] For hardware processors, data access to memory is performed through the data path. Since the bandwidth provided by the data path is fixed, the smaller the amount of data accessed, the less it occupies the hardware memory access path, and correspondingly, the more requests can be accessed in parallel. Summary of the Invention

[0003] This disclosure provides embodiments of a processor, a data processing method, a chip, a graphics card, and an electronic device.

[0004] In a first aspect, embodiments of this disclosure propose a processor, which includes an arithmetic unit and a memory access path. The arithmetic unit is used to send a data read / write request to the memory access path. The data read / write request includes data type conversion information. The memory access path is used to perform data type conversion on the original data according to the data type conversion information when it is determined that data type conversion is required based on the data type conversion information, thereby obtaining target data.

[0005] Secondly, this disclosure also provides a data processing method applied to a processor, the processor including an arithmetic unit and a memory access path, the method including: the arithmetic unit sending a data read / write request to the memory access path; wherein the data read / write request includes data type conversion information; and the memory access path, when determining that the original data needs to be converted according to the data type conversion information, converts the original data according to the data type conversion information to obtain target data.

[0006] Thirdly, embodiments of this disclosure provide a chip including the processor described in the first aspect above.

[0007] Fourthly, embodiments of this disclosure provide a graphics card including the chip described in the fourth aspect above.

[0008] Fifthly, embodiments of this disclosure provide an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to implement the data processing method described in the second aspect.

[0009] The processor provided in this disclosure, because the data read / write request sent by the arithmetic unit to the memory access path includes data type conversion information, allows the memory access path to convert the original data into target data based on the data type conversion information, and then read or write the target data to the corresponding address. Compared with related technologies, the processor of this disclosure eliminates the need for additional dedicated instructions to perform data type conversion on the original data, thus improving data read / write efficiency. Furthermore, the processor provided in this disclosure can perform data type conversion on the original data within the processor's internal memory access path, further enhancing data read / write efficiency. Attached Figure Description

[0010] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1a A structural block diagram of a processor provided in an embodiment of this disclosure; Figure 1b A structural block diagram of another processor provided in an embodiment of this disclosure; Figure 2 A structural block diagram of a memory access path provided in an embodiment of this disclosure; Figure 3 A schematic diagram of another memory access path provided in this embodiment of the present disclosure; Figure 4 A structural block diagram of another processor provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of a processor provided in accordance with an embodiment of the present disclosure and in a specific scenario; Figure 6 A flowchart of a data processing method provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0011] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding; these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0012] In large-scale model inference training scenarios, various data type conversions are frequently encountered. When reading data, the processor needs to first read the raw data from memory, then use specialized instructions to perform type conversion to obtain the target data. Similarly, when writing data, specialized instructions are needed to perform type conversion to obtain the target data, which is then written back to memory. Furthermore, the bit widths of the raw and target data types are often inconsistent, inevitably leading to bandwidth waste when transmitting raw data. For example, converting a half-precision floating-point (2-byte) data to a single-precision floating-point (4-byte) data type and writing it requires twice the amount of data compared to directly writing the half-precision type, resulting in wasted bandwidth.

[0013] Based on this, the present disclosure provides a processor that can improve data read and write efficiency.

[0014] Figure 1a This is a structural block diagram of a processor provided in an embodiment of the present disclosure.

[0015] like Figure 1a The processor 100 includes an arithmetic unit 101 and a memory access path 102.

[0016] The arithmetic unit 101 is used to send data read / write requests to the memory access path 102. The data read / write request includes data type conversion information; the memory access path 102 is used to perform data type conversion on the original data to obtain the target data if it determines, based on the data type conversion information, that data type conversion of the original data is required.

[0017] Specifically, this data type conversion information relates to data type conversion of the original data. For example, it describes and controls whether type conversion needs to be performed during data transfer in the memory access path 102, and provides configuration and instructions for data type conversion when necessary. The configuration and instructions for data type conversion can include the conversion method used and the timing of the conversion. The conversion method can refer to data type conversion, such as converting data type A to data type B; it can also refer to data format conversion, such as rounding or truncation. The timing of the conversion refers to where the data is converted within the memory access path 102, such as conversion after the data enters the memory access path 102, or conversion before output from the memory access path 102.

[0018] Furthermore, this data type conversion information can directly identify whether a conversion is needed and when the conversion should occur. For example, the data type conversion information can use one or more of binary data, string data, or other identifiers to identify whether a conversion is needed and / or when the conversion should occur. Furthermore, the specific data conversion method can be determined by combining the original data information and the target data type. For instance, 1 can be used to indicate that a conversion is needed, and 0 can be used to indicate that a conversion is not needed. Alternatively, 11 can be used to indicate that a conversion is needed and should be performed in the first-level cache of memory access path 102, and 10 can be used to indicate that a conversion is needed and should be performed in the last-level cache of memory access path 102, etc. This disclosure does not limit this.

[0019] Of course, the need for conversion and / or the timing of conversion can also be indirectly determined based on data type conversion information. For example, if the data type conversion information includes the original data type and the target data type, then the need for conversion and the timing of conversion can be determined based on the original data type and the target data type. This disclosure does not limit the specific content of the data type conversion information.

[0020] Specifically, the arithmetic unit 101 is responsible for initiating data read / write requests, along with data type conversion information, and then sending them to the memory access path 102. Upon receiving the data read / write request, the memory access path 102 can determine whether data type conversion is necessary based on the data type conversion information. If conversion is required, it will select an appropriate time to convert the original data, taking into account the data flow direction and the relative bit widths of the original and target data types, to reduce the bandwidth consumption of the memory access path 102 during data transmission.

[0021] The processor 100 provided in this disclosure, because the data read / write request sent by the arithmetic unit 101 to the memory access path 102 includes data type conversion information, allows the memory access path 102 to convert the original data into target data based on the data type conversion information, and then read or write the target data to the corresponding address. Compared with related technologies, the processor 100 of this disclosure does not require additional special instructions to perform data type conversion on the original data, thus improving the efficiency of data read / write. Moreover, the processor 100 provided in this disclosure can perform data type conversion on the original data within the memory access path 102 inside the processor 100, further improving the data read / write efficiency.

[0022] In some embodiments, the data type conversion information may include a target data type and the original data type. The memory access path 102 is further configured to determine that a data type conversion of the original data is required when the target data type and the original data type are inconsistent. Conversely, the memory access path 102 is also configured to determine that a data type conversion is not required when the target data type and the original data type are consistent.

[0023] Furthermore, based on the relative size of the bit widths of the target data type and the original data type, the timing of data conversion can be determined, and the original data can be converted from its original data type format to target data in the target data type format. For example, if the bit width corresponding to the original data type is greater than that corresponding to the target data type, the original data is first converted to the target data, and then the target data is transmitted, thereby better optimizing the bandwidth in the memory access path 102; conversely, if the bit width corresponding to the original data type is less than that corresponding to the target data type, the original data is transmitted first, and then the original data is converted to the target data, thus not increasing the bandwidth in the memory access path 102. At the same time, performing data type conversion in the memory access path 102 can reduce the processor's additional operations and improve data read and write efficiency.

[0024] In some embodiments, the memory access path 102 includes a multi-level cache for transmitting raw data and / or target data, and at least one level of the multi-level cache is provided with a data conversion unit. This data conversion unit is used to convert the raw data according to data type conversion information to obtain the target data.

[0025] In this application, the memory access path can determine whether the transmitted data is the original data or the target data based on the bit width of the original data and the target data. For example, the memory access path is used to transmit the data with the smaller bit width between the original data and the target data. For ease of understanding, this application uses the example of a multi-level cache where the cache connected to the arithmetic unit is the first-level cache and the cache connected to main memory is the last-level cache. It should be understood that this application does not limit the way the multi-level cache is divided. In this application, some or all levels of the cache in the multi-level cache can be equipped with data conversion units. For example, the first-level cache and the last-level cache are equipped with data conversion units. In response to receiving a data read / write request, the first-level cache or the last-level cache performs data type conversion on the original data. The specific cache that performs data type conversion is determined based on the type of the data read / write request and / or data type conversion information.

[0026] In some embodiments, when a hit occurs at any level in a multi-level cache, the cache of one of the hit levels, the first-level cache, and the last-level cache can perform data type conversion on the original data. For example, the hit level can perform data type conversion on the original data to obtain the target data and then transmit the target data.

[0027] Specifically, refer to Figure 1bThe memory access path 102 includes a multi-level cache 112 and a data conversion unit 122. The multi-level cache 112 is used for data transmission, including the transmission of raw data and / or target data. The data conversion unit 122 can be set within any one or more levels of the multi-level cache 112. For example, the data conversion unit 122 can be set in some levels of the cache, or in all levels of the cache. For instance, the data conversion unit 122 can be set within any one level of the multi-level cache 112, so that when data conversion is required, the raw data can be converted into target data when the raw data is transmitted to the cache level equipped with the data conversion unit 122.

[0028] For example, a data conversion unit 122 can be set in the first level cache of the multi-level cache 112, so that when data conversion is required, the original data can be converted into target data when the original data is transmitted to the first level cache; or a data conversion unit 122 can be set in the last level cache of the multi-level cache 112, so that when data conversion is required, the original data can be converted into target data when the original data is transmitted to the last level cache.

[0029] Of course, the processor provided in this disclosure may also include data conversion units 122 in multiple caches within the multi-level cache 112. For example, by including data conversion units 122 in each of the multi-level caches 112, a suitable cache can be selected as the target cache based on data type conversion information, and data conversion can be performed based on the data conversion units 122 in the target cache, thereby reducing the bandwidth occupied by the memory access path during data transmission.

[0030] like Figure 1b As shown, in some embodiments, the processor may also include target memory 103.

[0031] Specifically, when the bit width of the original data is greater than the bit width of the target data, the cache closest to the original data in the multi-level cache 112 can be used as the target cache to transform the original data. For example, for a data read request to the target memory 103, which requires reading the original data from the target memory 103, the last-level cache or the second-last-level cache close to the target memory 103, or other caches relatively far from the target memory 103, can be used as the target cache level. Similarly, for a data write request to the target memory 103, which requires writing the original data to the target memory 103, the first-level cache or the second-level cache close to the operation unit 101, or other caches close to the operation unit 101, can be used as the target cache. This can reduce the bandwidth consumption of the data on the path unit.

[0032] Conversely, when the bit width of the original data is smaller than the bit width of the target data, the cache level furthest from the original data in the multi-level cache 112 can be used as the target cache level. For example, for a data read request to the target memory 103, which requires reading the original data from the target memory 103, the first-level cache or second-level cache furthest from the target memory 103 can be used as the target cache. Similarly, for a data write request to the target memory 103, which requires writing the original data to the target memory 103, the last-level cache or a later cache furthest from the operation unit 101 can be used as the target cache. This can reduce the bandwidth usage of the multi-level cache.

[0033] Furthermore, this multi-level cache 112 can not only be used for data transmission, but also for data read / write operations, cache hit determination, etc., as needed, and this disclosure does not limit it. In some embodiments, in application scenarios where a cache hit occurs, the data may not need to access the last-level cache. This disclosure can utilize the data conversion unit 122 of the cache that has a cache hit to perform data type conversion on the original data.

[0034] The processor provided in this disclosure can, based on the original data type and the target data type in the data read / write request, first convert the original data into the target data and then transmit the target data; or first transmit the original data and then convert the original data into the target data, thereby completing the data read / write request.

[0035] The data conversion unit 122 can be located in the target cache, including in the first-level cache and / or the last-level cache, so that the data conversion unit 122 performs data conversion in the first-level cache or the last-level cache. Alternatively, the data conversion unit 122 can also be located in other caches in the multi-level cache 112, such as the secondary cache, the second-last-level cache, etc., so that the data type conversion of the original data is realized in the secondary cache or the second-last-level cache. Furthermore, the data conversion unit 122 can also be located in a module / layer / node specifically responsible for data aggregation / distribution in the memory access path, that is, data reading and writing must be performed through this module / layer / node. This approach can handle scenarios where multiple computing units share data or scenarios with dynamic bandwidth allocation; further details are omitted here.

[0036] In some embodiments, the arithmetic unit 101 is used to send data read / write requests for the target memory 103 to the memory access path 102. The multi-level cache 112 includes a first cache and a second cache. The first cache is connected to the arithmetic unit 101, and the second cache is connected to the target memory 103. The data conversion unit 122 of the target cache is used to convert the data type of the original data to obtain the target data. The target cache is either the first cache or the second cache. The target cache is determined based on the type of data read / write request and / or data type conversion information. The type of data read / write request includes data read requests and data write requests.

[0037] In this context, target memory 103 refers to any storage that the processing unit 101 can access or send data read / write requests to. For example, target memory 103 can be main memory, private memory connected to the processing unit 101, or shared memory shared by multiple processing units 101, etc., and this disclosure does not limit this. The target cache can be determined based on data type conversion information. For example, the data type conversion information directly instructs whether data conversion is performed in the first cache or the second cache. This data type conversion information can be determined in advance or dynamically based on the bit width of the original data and the target data, and the type of data read / write request. The target cache can also be determined based on the type of data read / write request, or it can be determined by combining the type of data read / write request and the data type conversion information; this disclosure does not limit this.

[0038] The arithmetic unit 101 sends data read / write requests to the multi-level cache 112. After receiving the data read / write request, the multi-level cache 112 can determine the relative bit width of the original data and the target data based on the data type conversion information (such as the original data type and the target data type) in the data read / write request. Since the data conversion unit 122 is located in the cache within the multi-level cache 112, the multi-level cache 112 can, based on the data type conversion information, first transmit the original data, or first send the original data to the data conversion unit 122 in the target cache for data conversion, and then transmit the data.

[0039] Specifically, when the bit width of the original data is greater than the bit width of the target data, the data conversion unit 122 of the multi-level cache 112 performs data conversion on the original data to obtain the target data with a smaller bit width, and then transmits the target data with a smaller bit width. This reduces the bandwidth usage of the multi-level cache 112. Conversely, when the bit width of the original data is less than the bit width of the target data, the multi-level cache 112 first transmits the original data with a smaller bit width, and then the data conversion unit 122 performs data conversion to obtain the target data with a larger bit width.

[0040] When the bit width of the original data is greater than the bit width of the target data, the cache closest to the original data in the multi-level cache 112 can be used as the target cache level to transform the original data. For example, for a data read request that needs to read the original data from the target memory 103, the second cache connected to the target memory 103 can be used as the target cache; similarly, for a data write request that needs to write the original data to the target memory 103, the first cache connected to the arithmetic unit 101 can be used as the target cache. This reduces the bandwidth consumption of the data on the path unit.

[0041] Conversely, when the bit width of the original data is smaller than the bit width of the target data, the cache level in the multi-level cache 112 that is far from the original data can be used as the target cache level. For example, for a data read request that needs to read the original data from the target memory 103, the first cache that is far from the target memory 103 and connected to the operation unit 101 can be used as the target cache. Similarly, for a data write request that needs to write the original data to the target memory 103, the second cache can be used as the target cache. This can reduce the bandwidth usage of the multi-level cache.

[0042] The processor provided in this disclosure can, based on the data read / write request and / or data type conversion information in the data read / write request, first convert the original data into target data and then transmit the target data; or first transmit the original data and then convert the original data into target data, thereby completing the data read / write request.

[0043] In some embodiments, the first cache and the second cache are caches at different levels or at the same level in a multi-level cache.

[0044] For example, when the target memory 103 is the main memory, during the process of the arithmetic unit 101 accessing the main memory, the arithmetic unit 101 and the main memory communicate data through the multi-level cache 112. The first cache and the second cache can be different caches in the multi-level cache 112, such as the first cache being the first level cache in the multi-level cache, the second cache being the last level cache in the multi-level cache, and so on.

[0045] For example, in a scenario where a processing unit 101 accesses other processing units 101, the target memory 103 is the memory within those other processing units. The first cache can be a first-level cache connected to the processing unit that sent the data access request, and the second cache can be a first-level cache connected to the accessed processing unit. In this case, both the first and second caches can be first-level caches, belonging to the same level of cache among multiple caches.

[0046] For data write requests, the following describes the specific implementation method for determining the target cache.

[0047] In some embodiments, when the type of the data read / write request is a data write request and the bit width of the target data type is smaller than the bit width of the original data type, the first cache is the target cache.

[0048] In some embodiments, when the type of the data read / write request is a data write request and the bit width of the target data type is greater than the bit width of the original data type, the second cache is the target cache.

[0049] Specifically, the memory access path 102 can determine the original data based on the write data information in the data read / write request; if the bit width of the target data type is smaller than the bit width of the original data type, the original data is converted into the target data in the first cache before data transmission through the internal caches at all levels; if the bit width of the target data type is larger than the bit width of the original data type, the original data is converted into the target data in the second cache after the original data is transmitted to the second cache through the internal caches at all levels.

[0050] The written data information refers to information related to the original data. The written data information may include the storage address of the original data, the length of the original data, or the original data itself. This disclosure does not limit this.

[0051] In some embodiments, when the data transfer request is a write request, the original data needs to be transferred through the memory access path and then written to the destination address (e.g., the address of the processor's main memory or another target memory address). That is, the data flow is from the first cache of the memory access path to the second cache, and finally to the destination. In this case, and when the bit width of the target data type is smaller than the bit width of the original data type, the original data with a larger bit width can be converted into target data with a smaller bit width first, and then the target data with a smaller bit width can be transferred through the memory access path 102 to reduce the bandwidth consumption of the memory access path during data transfer. Conversely, when the data transfer request is a write request and the bit width of the target data type is larger than the bit width of the original data type, the original data with a smaller bit width can be transferred through a multi-level cache first, then the original data can be converted into target data, and then the target data can be written to the destination address. In this way, the bandwidth consumption of the memory access path will not increase during data transfer.

[0052] In some embodiments, a first cache in the memory access path receives a data write request. The first cache can obtain the original data based on the data read / write request. The data read request may directly carry the original data or information related to the original data; this disclosure does not limit this. Simultaneously, the first cache can also determine the bit width of the original data type and the target data type based on the original data type and the target data type in the data read / write request. If the bit width of the target data type is smaller than the bit width of the original data type, the first cache is determined as the target cache for performing data type conversion. A data conversion unit set within the first cache converts the original data into the target data based on the original data type and the target data type. The first cache sends the target data to a second cache. Finally, the second cache writes the target data to the destination address (such as main memory), completing the data write request.

[0053] This embodiment of the disclosure determines the first cache as the target cache for performing data type conversion when the data read / write request is a data write request and the bit width of the target data type is smaller than the bit width of the original data type. The original data is first converted using the conversion unit corresponding to the first cache, and then the target data obtained after conversion and the data transmission request are transmitted. This can minimize the bandwidth consumption of data on multi-level caches.

[0054] In some embodiments, the first cache in the memory access path receives a data write request. The first cache obtains the original data based on the data read / write request, and determines the bit width of the original and target data types based on the original and target data types in the request. If the bit width of the target data type is greater than the bit width of the original data type, the second cache is designated as the target cache for data type conversion. The original data is then sent to the second cache, where data type conversion is performed to obtain the target data. Finally, the second cache writes the target data to the destination address (e.g., main memory), completing the data write request.

[0055] In this embodiment, when the data read / write request is a data write request and the bit width of the target data type is greater than the bit width of the original data type, the second cache is determined as the target cache level for performing data type conversion. The data transmission request is first transmitted to the second cache using the first cache, and then the original data is converted using the data conversion unit corresponding to the second cache. This does not increase the bandwidth usage of the data on the multi-level cache.

[0056] Furthermore, in some embodiments, the data read / write request also includes a target data address; the memory access path is also used to write the target data into the target memory according to the target data address. Here, the target data address refers to the address where the target data is written.

[0057] For data read requests, the following describes the specific implementation method for determining the target cache.

[0058] In some embodiments, when the type of the data read / write request is a data read request and the bit width of the target data type is smaller than the bit width of the original data type, the second cache is the target cache.

[0059] In some embodiments, when the type of the data read / write request is a data read request and the bit width of the target data type is greater than the bit width of the original data type, the first cache is the target cache.

[0060] Specifically, the original data is read from the target memory according to the data read request; if the bit width of the target data type is smaller than the bit width of the original data type, the original data is converted into target data in the second cache before data transmission through internal caches at all levels; if the bit width of the target data type is larger than the bit width of the original data type, the original data is converted into target data in the first cache after data transmission through internal caches at all levels.

[0061] In the case of a data read request, the original data needs to be read from the destination address (such as the address of the processor's main memory or the address of other target memory) and the original data is read out according to the target data type through the memory access path (that is, the target data is read out).

[0062] In some embodiments, after receiving a data read request, the first cache in the memory access path determines the bit width of the original data type and the target data type based on the original data type and the target data type in the data read request. If the bit width of the target data type is smaller than the bit width of the original data type, the second cache is determined as the target cache for data type conversion, and the data read request is sent to the second cache. The second cache reads the original data from the target memory according to the data read request and sends the original data to the data conversion unit set in the second cache. The data conversion unit converts the original data into the target data according to the original data type and the target data type. Then, the data conversion unit returns the target data to the second cache, and the second cache sends the target data to the first cache. Finally, the first cache reads the target data, completing the data read request.

[0063] In this embodiment, when the data read / write request is a data read request and the bit width of the target data type is smaller than the bit width of the original data type, the second cache is determined as the target cache level for performing data type conversion. The target memory first transmits the data transmission request to the second cache, then uses the data conversion unit corresponding to the second cache to convert the original data, and then sends the converted target data to the first cache and reads it out. This can reduce the bandwidth consumption of data on multi-level caches.

[0064] In some embodiments, after receiving a data read request, the first cache in the memory access path determines the bit width of the original data type and the target data type based on the original data type and the target data type in the data read request. If the bit width of the target data type is greater than the bit width of the original data type, the first cache is determined as the target cache level for data type conversion, and the data read request is sent to the second cache. The second cache reads the original data from the target memory according to the data read request. Further, if the bit width of the target data type is greater than the bit width of the original data type, the second cache sends the original data to the first cache, which then sends the original data to the data conversion unit located within the first cache. The data conversion unit converts the original data into the target data based on the original data type and the target data type. Afterward, the data conversion unit returns the target data to the first cache. Finally, the first cache reads the target data, completing the data read request.

[0065] In this embodiment, when the data read / write request is a data read request and the bit width of the target data type is greater than the bit width of the original data type, the first cache is determined as the target cache level for performing data type conversion. The data transmission request is first transmitted to the first cache using the second cache, and then the original data is converted using the data conversion unit corresponding to the first cache. This does not increase the bandwidth usage of the data on the multi-level cache.

[0066] Furthermore, in some embodiments, the type of data read / write request is a data read request, which also includes the original data address and the requested data length. The memory access path is also used to read the original data from the target memory according to the original data address and the requested data length.

[0067] Specifically, the original data address refers to the address where the original data is read; the requested data length refers to the length of data to be read. Based on the original data address and the requested data length, the original data can be read from main memory.

[0068] This disclosure provides a processor that, when the bit width of the original data type is greater than the bit width of the target data type, first converts the original data into target data before transmitting the target data; conversely, when the bit width of the original data type is less than the bit width of the target data type, it first transmits the original data and then converts it back into target data. This allows for better optimization of bandwidth in the memory access path. Furthermore, the ability to perform data type conversion within the memory access path reduces additional processor operations and improves data read / write efficiency.

[0069] The processor disclosed herein can combine data read / write requests with data type conversion, and perform corresponding data conversion processing on the memory access path, which can better optimize bandwidth and reduce the processor's additional operations.

[0070] The following example uses the target memory in the processor as the main memory, the first cache as the first level cache, and the second cache as the last level cache to illustrate the processor in detail.

[0071] In some embodiments, the processor further includes main memory, and the multi-level cache includes a first-level cache and a last-level cache. The target memory is the main memory, the first cache is the first-level cache, and the second cache is the last-level cache. A data conversion unit is provided within the first-level cache. The first-level cache is used to determine the original data based on the data read / write request when the data read / write request is a data write request. The data conversion unit within the first-level cache is used to convert the original data into target data when the bit width of the target data type is smaller than the bit width of the original data type. The first-level cache is also used to send the target data to the last-level cache. The last-level cache is used to write the target data into the main memory.

[0072] Figure 2 This is a structural block diagram of a memory access path provided in an embodiment of the present disclosure.

[0073] refer to Figure 1b-Figure 2 The memory access path 102 includes a multi-level cache 112 and a data translation unit 122. Figure 2 (Not marked) The multi-level cache 112 includes a first-level cache 201 and a last-level cache 202, and the data conversion unit 122 includes a first conversion unit 203, which is set in the first-level cache 201.

[0074] Specifically, the first-level cache 201 is used to determine the original data based on the data read / write request when the data read / write request is a data write request; the first conversion unit 203 is used to convert the original data into target data when the data read / write request is a data write request and the bit width of the target data type is smaller than the bit width of the original data type; the first-level cache 201 is also used to send the target data to the last-level cache 202; the last-level cache 202 is used to write the target data into the target memory 103.

[0075] Specifically, when the data read / write request is a data write request, the original data needs to be written to the target memory 103 (which can be the processor's main memory) through the memory access path 102.

[0076] Specifically, firstly, the arithmetic unit 101 sends a data write request to the first-level cache 201 in the memory access path 102. Then, the first-level cache 201 obtains the original data based on the data read / write request. The data read request may directly carry the original data or information related to the original data; this disclosure does not limit this. Simultaneously, the first-level cache 201 can also determine the bit width of the original and target data types based on the original and target data types in the data read / write request. If the bit width of the target data type is smaller than the bit width of the original data type, the first-level cache 201 sends the original data to the first conversion unit 203 located within the first-level cache 201. The first conversion unit 203 converts the original data into target data based on the original and target data types. Afterward, the first conversion unit 203 returns the target data to the first-level cache 201, which then sends the target data to the last-level cache 202. Finally, the last-level cache 202 writes the target data into the target memory 103, completing the data write request.

[0077] See also Figure 1b-Figure 2 In some embodiments, the data conversion unit 122 includes not only the first conversion unit 203, but also the second conversion unit 204, which is located in the last-level cache 202.

[0078] The first-level cache 201 is also used to send the original data to the last-level cache 202 when the data read / write request is a data write request and the bit width of the target data type is greater than the bit width of the original data type; the second conversion unit 204 is used to convert the original data into target data according to the target data type and the original data type.

[0079] Specifically, firstly, the arithmetic unit 101 sends a data write request to the first-level cache 201 in the memory access path 102. Then, the first-level cache 201 obtains the original data based on the data read / write request. Simultaneously, the first-level cache 201 determines the bit width of the original and target data types based on the original and target data types in the data read / write request. If the bit width of the target data type is greater than the bit width of the original data type, the first-level cache 201 directly sends the original data to the last-level cache 202. Then, the last-level cache 202 sends the original data to the second conversion unit 204 located within it. The second conversion unit 204 converts the original data into the target data based on the original and target data types. Afterward, the second conversion unit 204 returns the target data to the last-level cache 202, which then writes the target data into the target memory 103, completing the data write request.

[0080] In some embodiments, the data read / write request further includes a target data address and write data information; the first-level cache 201 is also used to determine the original data based on the write data information when the data read / write request is a data write request; the last-level cache 202 is also used to write the target data to the target memory 103 based on the target data address.

[0081] Specifically, the target data address refers to the address where the target data is written; the written data information refers to information related to the original data, which may include the storage address of the original data, the length of the original data, or the original data itself, and this disclosure does not limit this. The memory access path 102 can not only transmit the original data or the target data, but also transmit data read / write requests, so as to write the target data to the target memory 103 or read the original data from the target memory 103 according to the data read / write request.

[0082] Figure 3 This is a schematic diagram of another memory access path provided in an embodiment of the present disclosure.

[0083] refer to Figure 1b and Figure 3 As shown, the memory access path 102 includes a multi-level cache 112 and a data translation unit 122. Figure 3 (Not marked) The multi-level cache 112 includes a first-level cache 201 and a last-level cache 202, and the data conversion unit 122 includes a first conversion unit 203, which is set in the last-level cache 202.

[0084] The last-level cache 202 is used to read the original data from the target memory 103 according to the data read request when the data read / write request is a data read request; the first conversion unit 203 is used to convert the original data into target data when the data read / write request is a data read request and the bit width of the target data type is smaller than the bit width of the original data type; the last-level cache 202 is also used to send the target data to the first-level cache 201.

[0085] Specifically, when the data read / write request is a data read request, it is necessary to read the original data from the target memory 103 and read the original data out according to the target data type through the memory access path 102 (that is, to read out the target data).

[0086] Specifically, firstly, the arithmetic unit 101 sends a data read request to the first-level cache 201 in the memory access path 102. The first-level cache 201 then sends the data read request to the last-level cache 202, which reads the original data from the target memory 103 according to the data read request. Furthermore, the last-level cache 202 can also determine the bit width of the original and target data types based on the original and target data types in the data read request. If the bit width of the target data type is smaller than the bit width of the original data type, the last-level cache 202 sends the original data to the first conversion unit 203 located within the last-level cache 202. The first conversion unit 203 converts the original data into the target data based on the original and target data types. Then, the first conversion unit 203 returns the target data to the last-level cache 202, which then sends the target data to the first-level cache 201. Finally, the first-level cache 201 reads the target data, completing the data read request.

[0087] In some embodiments, the data conversion unit 122 includes not only the first conversion unit 203, but also a second conversion unit 204. The second conversion unit 204 is disposed within the first-level cache 201.

[0088] The last-level cache 202 is also used to send the original data to the first-level cache 201 when the data read / write request is a data read request and the bit width of the target data type is greater than the bit width of the original data type; the first-level cache 201 is used to convert the original data into target data according to the target data type and the original data type.

[0089] Specifically, firstly, the arithmetic unit 101 sends a data read request to the first-level cache 201 in the memory access path 102. The first-level cache 201 then sends the data read request to the last-level cache 202, which reads the original data from the target memory 103 according to the data read request. Furthermore, the last-level cache 202 can also determine the bit width of the original data type and the target data type based on the original data type and the target data type in the data read request. If the bit width of the target data type is greater than the bit width of the original data type, the last-level cache 202 sends the original data to the first-level cache 201, which then sends the original data to the second conversion unit 204 located within the first-level cache. The second conversion unit 204 converts the original data into the target data according to the original data type and the target data type. Afterward, the second conversion unit 204 returns the target data to the first-level cache 201. Finally, the first-level cache 201 reads the target data, completing the data read request.

[0090] In some embodiments, the data read / write request further includes the original data address and the requested data length; the last-level cache 202 is also used to read the original data from the target memory 103 according to the original data address and the requested data length when the data read / write request is a data read request; the first-level cache 201 is also used to read the target data.

[0091] Specifically, the original data address refers to the address where the original data is read; the requested data length refers to the length of data to be read. Based on the original data address and the requested data length, the original data can be read from the target memory 103.

[0092] The processor provided in this embodiment of the present disclosure provides conversion units (first conversion unit 203 or second conversion unit 204) in both the first-level cache 201 and the last-level cache 202. This allows the processor to convert the original data to the target data before transmitting it when the bit width of the original data type is greater than that of the target data type; conversely, when the bit width of the original data type is less than that of the target data type, the processor transmits the original data first and then converts it back to the target data. This better optimizes the bandwidth in the memory access path. Furthermore, the ability to perform data type conversion in the memory access path reduces additional operations by the processor and improves data read / write efficiency.

[0093] The processor disclosed herein combines data read / write requests with data type conversion, performing corresponding data conversion processing on the memory access path (Level 1 cache or Level 2 cache), which can better optimize bandwidth and reduce additional operations of the processor.

[0094] Figure 4 This is a structural block diagram of another processor provided in an embodiment of the present disclosure.

[0095] like Figure 4 As shown, with Figure 1b The processors in this series are similar, and the same parts will not be described again. Figure 4 and Figure 1b The difference is only that Figure 4 The processor includes multiple arithmetic units 101 and multiple level 1 caches 201, with each arithmetic unit 101 corresponding to a level 1 cache 201.

[0096] In some embodiments, the processor 100 also includes a bus, and a plurality of first-level caches 201 are connected to the last-level cache 202 via the bus.

[0097] Specifically, arithmetic units 101 typically have a private Level 1 cache (L1 cache, L1) 201. Multiple arithmetic units 101 then share a large Last Level cache 202, also known as the Last Level Cache (LLC). The LLC is directly connected to the target memory 103, which can be main memory, typically DDR (Double Data Rate Synchronous Dynamic Random-Access Memory). Multiple L1 caches access the LLC through a complex bus or other similar structure.

[0098] In addition, a second-level cache, a third-level cache, etc., may be included between L1 and LLC, but this disclosure does not limit this.

[0099] The process of L1 accessing LLC involves the bandwidth issue of the data request path. For hardware, the bandwidth that the data path can provide is fixed. Therefore, the less data is accessed, the less it occupies the hardware memory access path, and correspondingly, the more requests can be accessed in parallel. Table 1 is a comparison table of data conversion rules.

[0100] Table 1. Data Conversion Rule Comparison Table

[0101] See Table 1 and Figure 4 When the arithmetic unit 101 initiates a read request, since the data flows from the target memory 103 to the arithmetic unit 101, if the target data type is larger than the original data type, performing data conversion in the data conversion unit in L1 can reduce the bandwidth usage of the memory access path. Conversely, if the target data type is smaller than the original data type, performing data conversion in the data conversion unit in LLC is more appropriate.

[0102] For write requests, data flows from the arithmetic unit 101 to the target memory 103. Therefore, when the target data type is larger than the original data type, performing data conversion in the data conversion unit within the LLC can reduce the bandwidth usage of the memory access path. Conversely, when the target data type is smaller than the original data type, performing data conversion in the data conversion unit within L1 is more appropriate. The judgment conditions for write requests are exactly the opposite of those for read requests.

[0103] Figure 5 This is a schematic diagram of the structure of a processor provided in a specific scenario according to an embodiment of this disclosure.

[0104] See Figure 5 Assuming the data read / write request is a data read request, the data read request includes: Load addr=0, size=4byte, original data type=float, target data type=half. Here, Load addr refers to the address of the original data, size refers to the length of the requested data, float is a single-precision floating-point number, and half is a half-precision floating-point number.

[0105] First, the arithmetic unit 101 sends the data read request to the first-level cache 201. The first-level cache 201 then sends the data read request to the last-level cache 202. The last-level cache 202 first reads the corresponding float (raw data) according to the Load addr and size in the data read request. Then, the last-level cache 202 determines that the target data type has a smaller bit width based on the raw data type and the target data type in the data read request. Therefore, the last-level cache 202 needs to use its internal data conversion unit to convert the read float into half (target data), that is, to convert the 4-byte raw data into 2-byte target data. Thus, the last-level cache 202 only needs to return the 2-byte target data to the first-level cache 201, and the first-level cache 201 then reads the 2-byte target data.

[0106] Figure 5 In the corresponding embodiments, bandwidth usage can be reduced by half. The specific bandwidth savings of the processor provided in this disclosure vary depending on the original and target data types during data read and write operations. For example, if the original data type is fp8 (1 byte) and the target data type is float, bandwidth usage can be saved by 75%. Furthermore, this disclosure can also save the processor from requiring separate type conversion instructions.

[0107] The processor provided in this disclosure includes conversion units in both the first-level cache and / or the last-level cache. Furthermore, the data read / write requests processed by the processor carry both the target data type and the original data. This allows the processor to convert the original data to the target data before transmitting it, even when the bit width of the original data type is greater than that of the target data type. This optimizes bandwidth in the memory access path. Simultaneously, the ability to perform data type conversion within the memory access path reduces additional processor operations and improves data read / write efficiency. The processor in this disclosure combines data read / write requests with data type conversion, performing corresponding data conversion processing on the memory access path (first-level cache or last-level cache), thus optimizing bandwidth and reducing additional processor operations.

[0108] Based on the same inventive concept as the processors described above, this disclosure also provides a data processing method that can be applied to any of the processors described above.

[0109] Figure 6 This is a flowchart of a data processing method provided in an embodiment of the present disclosure.

[0110] Further reference Figure 6 As a method flow applied to the processors shown in the above figures, the method embodiments are similar to... Figure 1a The processor embodiment shown corresponds to this.

[0111] like Figure 6 As shown, process 600 may specifically include the following steps: Step 601: The arithmetic unit sends the data read / write request to the memory access path.

[0112] Data read / write requests include data type conversion information.

[0113] Step 602: If the memory access path determines that the original data needs to be converted based on the data type conversion information, it converts the original data according to the data type conversion information to obtain the target data.

[0114] In this embodiment, the specific processing procedures of steps 601 to 602 in process 600 and their resulting technical effects can be referred to respectively. Figure 1a The relevant descriptions of the arithmetic unit 101 and memory access path 102 in the corresponding embodiments will not be repeated here.

[0115] The data processing method provided in this disclosure includes data type conversion information carried in the data read / write request sent by the arithmetic unit to the memory access path. By utilizing the conversion units set in the first-level cache and / or the last-level cache in the memory access path, the processor can convert the original data into target data before transmitting it, even when the bit width of the original data type is smaller than that of the target data type. This optimizes the bandwidth in the memory access path. Furthermore, performing data type conversion within the memory access path reduces additional processor operations and improves data read / write efficiency. The data processing method provided in this disclosure combines data read / write requests with data type conversion, performing corresponding data conversion processing on the memory access path (such as the first-level cache or the last-level cache), which optimizes bandwidth and reduces additional processor operations.

[0116] In some embodiments, the memory access path includes a multi-level cache for transmitting raw data and / or target data. At least one level of the multi-level cache is provided with a data conversion unit, wherein the data conversion unit performs data type conversion on the raw data according to data type conversion information to obtain the target data.

[0117] In some embodiments, the arithmetic unit sends data read / write requests for the target memory to the memory access path. The multi-level cache includes a first cache and a second cache. The first cache is connected to the arithmetic unit, and the second cache is connected to the target memory. The data conversion unit of the target cache performs data type conversion on the original data to obtain the target data. The target cache is either the first cache or the second cache. The target cache is determined based on the type of data read / write request and / or data type conversion information. The type of data read / write request includes data read requests and data write requests.

[0118] In some embodiments, the data type conversion information includes the original data type and the target data type; wherein, when the original data type and the target data type are different, the memory access path determines that the original data needs to be converted.

[0119] In some embodiments, the first cache and the second cache are caches at different levels or at the same level in a multi-level cache.

[0120] In some embodiments, when the type of the data read / write request is a data write request and the bit width of the target data type is smaller than the bit width of the original data type, the first cache is the target cache.

[0121] In some embodiments, when the type of the data read / write request is a data write request and the bit width of the target data type is greater than the bit width of the original data type, the second cache is the target cache.

[0122] In some embodiments, the type of data read / write request is a data write request, and the data read / write request further includes a target data address; the memory access path is used to write the target data into the target memory according to the target data address.

[0123] In some embodiments, when the type of the data read / write request is a data read request and the bit width of the target data type is smaller than the bit width of the original data type, the second cache is the target cache.

[0124] In some embodiments, when the type of the data read / write request is a data read request and the bit width of the target data type is greater than the bit width of the original data type, the first cache is the target cache.

[0125] In some embodiments, the type of data read / write request is a data read request, which also includes the original data address and the requested data length; the memory access path reads the original data from the target memory according to the original data address and the requested data length.

[0126] In some embodiments, the target memory is the main memory, the first cache is the first-level cache, and the second cache is the last-level cache; and a data conversion unit is provided in the first-level cache; wherein, when the data read / write request is a data write request, the first-level cache determines the original data based on the data read / write request; when the bit width of the target data type is smaller than the bit width of the original data type, the data conversion unit in the first-level cache converts the original data into target data; the first-level cache sends the target data to the last-level cache; and the last-level cache writes the target data into the main memory.

[0127] In some embodiments, the processor further includes main memory, and a data conversion unit is provided in the last-level cache; wherein, when the data read / write request is a data read request, the last-level cache reads the original data from the main memory according to the data read request; when the bit width of the target data type is smaller than the bit width of the original data type, the data conversion unit in the last-level cache converts the original data into target data; the last-level cache is also used to send the target data to the first-level cache.

[0128] The specific implementation details and technical effects of the data processing method embodiments provided in this disclosure are the same as those of the implementation details and technical effects of the processor embodiments described above, and will not be repeated here.

[0129] This embodiment is a method embodiment corresponding to the processor embodiment described above. The data processing method provided in this disclosure sends a data read / write request from the arithmetic unit to the memory access path, carrying the target data type and the original data. By utilizing the conversion unit set in the first-level cache and / or the last-level cache in the memory access path, the processor can convert the original data into the target data first, even when the bit width of the original data type is greater than the bit width of the target data type, before transmitting the target data. This better optimizes the bandwidth in the memory access path. Simultaneously, performing data type conversion in the memory access path reduces additional processor operations and improves data read / write efficiency. The data processing method provided in this disclosure combines data read / write requests with data type conversion, performing corresponding data conversion processing on the memory access path (such as the first-level cache or the last-level cache), which can both better optimize bandwidth and reduce additional processor operations.

[0130] According to embodiments of this disclosure, this disclosure also provides a chip including any of the processors described in the above embodiments.

[0131] According to embodiments of this disclosure, this disclosure also provides a graphics card, including any of the chips described in the above embodiments.

[0132] According to embodiments of this disclosure, this disclosure also provides an electronic device, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to implement the data processing method described in any of the above embodiments.

[0133] Figure 7 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. For example... Figure 7 As shown, the electronic device 700 of this embodiment includes a processor 701 and a memory 702; wherein, the memory 702 is used to store computer execution instructions; the processor 701 is used to execute the computer execution instructions stored in the memory to implement the various steps performed by the electronic device in the above embodiment. For details, please refer to the relevant descriptions in the foregoing method embodiments. For example, the electronic device 700 can be a general-purpose processor, a graphics processing device, a neural network computing device, or a graph neural network computing device.

[0134] In some embodiments, the memory 702 can be either standalone or integrated with the processor 701.

[0135] When the memory 702 is set up independently, the electronic device also includes a bus 703 for connecting the memory 702 and the processor 701.

[0136] It should be understood that the processor 701 described above can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0137] The memory 702 may include high-speed RAM memory, and may also include non-volatile memory NVM, such as at least one disk storage device, and may also be a USB flash drive, portable hard drive, read-only memory, disk or optical disc, etc.

[0138] Bus 703 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0139] This disclosure also provides a computer storage medium storing computer execution instructions, which, when executed by a processor, implement the steps of the data processing method in any of the above method embodiments.

[0140] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the data processing method according to any of the above embodiments.

[0141] The solution provided in this disclosure, by setting conversion units in both the processor's L1 cache and / or L3 cache, and by including the target data type and the original data in the data read / write request, allows the processor to convert the original data to the target data before transmitting it, even when the bit width of the original data type is greater than that of the target data type. This better optimizes the bandwidth in the memory access path. Simultaneously, the ability to perform data type conversion within the memory access path reduces additional processor operations and improves data read / write efficiency. The solution provided in this disclosure combines data read / write requests with data type conversion, performing corresponding data conversion processing on the memory access path (such as the L1 cache or L3 cache), which both better optimizes bandwidth and reduces additional processor operations.

[0142] In the several embodiments provided by this invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0143] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to implement the solution of this embodiment according to actual needs.

[0144] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit composed of the above modules can be implemented in hardware or in the form of hardware plus software functional units.

[0145] The integrated modules described above, implemented as software functional modules, can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute partial steps of the methods in the various embodiments of this application.

[0146] The aforementioned storage medium can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium accessible to general-purpose or special-purpose computers.

[0147] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. Both the processor and the storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and storage medium can exist as discrete components in an electronic device or host device.

[0148] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0149] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0150] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0151] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A processor, characterized in that, The processor includes a processing unit and a memory access path. The memory access path includes a multi-level cache, and at least one level of the multi-level cache contains a data translation unit. The computing unit is used to send data read / write requests to the memory access path; wherein, the data read / write request includes data type conversion information; The data conversion unit of the target cache in the multi-level cache is used to perform data conversion on the original data in the target cache according to the data conversion information when it is determined that the original data needs to be converted according to the data conversion information, so as to obtain the target data. The target cache is determined based on the type of the data read / write request and / or the data conversion information. The multi-level cache is used to transmit the smaller bit width of the original data and the target data.

2. The processor according to claim 1, characterized in that, The computing unit is used to send data read / write requests for the target memory to the memory access path, wherein the multi-level cache includes a first cache and a second cache, the first cache is connected to the computing unit, and the second cache is connected to the target memory; The target cache is either the first cache or the second cache, and the types of data read / write requests include data read requests and data write requests.

3. The processor according to claim 2, characterized in that, The data type conversion information includes the original data type and the target data type; The memory access path is also used to determine whether the original data needs to be converted when the original data type and the target data type are different.

4. The processor according to claim 2, characterized in that, The first cache and the second cache are caches at different levels or at the same level in the multi-level cache.

5. The processor according to claim 3, characterized in that, When the type of the data read / write request is a data write request and the bit width of the target data type is smaller than the bit width of the original data type, the first cache is the target cache.

6. The processor according to claim 3, characterized in that, When the type of the data read / write request is a data write request and the bit width of the target data type is greater than the bit width of the original data type, the second cache is the target cache.

7. The processor according to claim 2, characterized in that, The data read / write request is of the type of data write request, and the data read / write request also includes the target data address; The memory access path is used to write the target data into the target memory according to the target data address.

8. The processor according to claim 3, characterized in that, When the type of the data read / write request is a data read request and the bit width of the target data type is smaller than the bit width of the original data type, the second cache is the target cache.

9. The processor according to claim 3, characterized in that, When the type of the data read / write request is a data read request and the bit width of the target data type is greater than the bit width of the original data type, the first cache is the target cache.

10. The processor according to claim 2, characterized in that, The data read / write request is of the type of data read request, and the data read / write request also includes the original data address and the requested data length; The memory access path is also used to read the original data from the target memory according to the original data address and the requested data length.

11. The processor according to claim 3, characterized in that, The processor further includes main memory, the target memory is the main memory, the first cache is a first-level cache, the second cache is a last-level cache, and a data translation unit is provided within the first-level cache; wherein... The first-level cache is used to determine the original data based on the data read / write request when the data read / write request is a data write request; The data conversion unit within the first-level cache is used to convert the original data into the target data when the bit width of the target data type is smaller than the bit width of the original data type. The first-level cache is also used to send the target data to the last-level cache; The last-level cache is used to write the target data into the main memory.

12. The processor according to claim 11, characterized in that, A data conversion unit is provided within the last-level cache; wherein, The last-level cache is used to read the original data from the main memory according to the data read request when the data read / write request is a data read request; The data conversion unit in the last-level cache is used to convert the original data into the target data when the bit width of the target data type is smaller than the bit width of the original data type. The last-level cache is also used to send the target data to the first-level cache.

13. A data processing method, characterized in that, Applied to a processor, the processor including a processing unit and a memory access path, the memory access path including a multi-level cache, and at least one level of the multi-level cache having a data translation unit, the method includes: The arithmetic unit sends a data read / write request to the memory access path; wherein, the data read / write request includes data type conversion information; When the target cache in the multi-level cache determines that the original data needs to be converted according to the data type conversion information, the data conversion unit of the target cache performs data type conversion on the original data within the target cache based on the data type conversion information to obtain the target data. The target cache is determined based on the type of the data read / write request and / or the data type conversion information. The multi-level cache is used to transmit the smaller bit width of the original data and the target data.

14. A chip, characterized in that, Includes the processor as described in any one of claims 1-12.

15. A graphics card, characterized in that, Includes the chip as described in claim 14.

16. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the data processing method of claim 13.

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