Floating point unordered add operation method and processor

Abstract

Embodiments of the present application disclose a floating-point unordered addition operation method and a processor. The method obtains a vector source operand, performs precision extension on each first floating-point element in the vector source operand to obtain a first vector operand composed of a plurality of second floating-point elements, writes the first vector operand into a logical vector register, performs vector-level unordered summation reduction, and obtains a vector reduction result of the vector source operand. Finally, the vector reduction result is accumulated with the lowest element in a scalar register to obtain an operation result of the vector source operand. The method can not only significantly improve the numerical stability of the reduction process, but also effectively solve the technical problem of the performance bottleneck of the vector reduction operation in the RISC-V vector extension instruction set, thereby providing a more optimal hardware implementation scheme for a high-performance, high-precision, and high-compatibility vector floating-point accelerator.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a floating-point unordered addition operation method and processor. Background Technology

[0002] In the field of parallel computing, vector reduction is a fundamental operation in high-performance computing, artificial intelligence, and scientific computing, and is widely used in matrix operations, statistical analysis, and neural network training. Vector reduction achieves efficient computation of operations such as addition, maximization, and minimization by merging multiple operands hierarchically according to a tree structure.

[0003] In the RISC-V Vector Extension instruction set (RVV), the `vfredusum.vs` instruction, as an unordered reduction summation instruction, allows the implementation of a reduction tree structure that does not guarantee the order of operations, thereby reducing computation depth and improving parallelism. However, using the `vfredusum.vs` instruction for unordered reduction summation requires complex hardware architecture, has long timing paths and poor scalability, and suffers from low computational accuracy, making it difficult to simultaneously meet the performance requirements of high throughput and low latency. Summary of the Invention

[0004] Based on this, this application provides a floating-point unordered addition operation method and processor, which can not only effectively solve the technical problem of the performance bottleneck of vector reduction operation in the RISC-V vector extension instruction set, but also improve the stability and accuracy of the calculation results.

[0005] Firstly, this application provides a floating-point unordered addition operation method, including:

[0006] Retrieve the vector source operands; the vector source operands include multiple first floating-point elements;

[0007] Each first floating-point element is precision extended to obtain a first vector operand; the first vector operand includes multiple second floating-point elements, and the ratio between the number of floating-point bits of the second floating-point elements and the number of floating-point bits of the first floating-point elements is an integer greater than or equal to 2.

[0008] Write the first vector operand into the logical vector register; the logical vector register includes at least one physical vector register.

[0009] Perform vector-level unordered summation and reduction on multiple second floating-point elements in the logic vector register to obtain the vector reduction result of the vector source operands;

[0010] The vector reduction result is accumulated with the least significant element in the scalar register to obtain the result of the vector source operand operation.

[0011] Furthermore, in the floating-point unordered addition method provided in this application, each first floating-point element is precision-expanded to obtain a first vector operand, including:

[0012] The exponent field of each first floating-point element is biased to obtain the expanded exponent field, and zero expansion is performed at the least significant bit of the mantissa of each first floating-point element to obtain the expanded mantissa.

[0013] The sign bit, the extended exponent field, and the extended number of bits of the first floating-point element are combined to form the second floating-point element.

[0014] Furthermore, in the floating-point unordered addition method provided in this application, before writing the first vector operand into the logic vector register, the method further includes:

[0015] The vector length ratio of the control logic vector register is determined based on the vector bit width of the first vector operand and the physical bit width of the physical vector register.

[0016] Based on the vector length ratio, at least one physical vector register is selected to form a logical vector register.

[0017] Furthermore, in the floating-point unordered addition method provided in this application, writing the first vector operand into the logic vector register includes:

[0018] If the vector length multiplier is less than the preset length multiplier threshold, the first vector operand is written to a physical vector register;

[0019] If the vector length multiplier is greater than or equal to the length multiplier threshold, the first vector operand is written to multiple physical vector registers.

[0020] Furthermore, in the floating-point unordered addition method provided in this application, the first vector operand is written to multiple physical vector registers, including:

[0021] Based on the vector length ratio, the first vector operand is split into multiple groups of floating-point numbers; each group of floating-point numbers includes multiple second floating-point elements;

[0022] Multiple sets of floating-point numbers are input into a single physical vector register; multiple sets of floating-point numbers correspond to one physical vector register.

[0023] Furthermore, in the floating-point unordered addition method provided in this application, the logic vector register includes a first physical vector register and a second physical vector register, and the physical bit width of the first physical vector register is equal to the physical bit width of the second physical vector register.

[0024] Perform vector-level unordered summation and reduction on multiple second floating-point elements in the logic vector register to obtain the vector reduction result of the vector source operands, including:

[0025] If the vector length multiplier is greater than or equal to the length multiplier threshold, perform vector-level unordered summation and reduction on the second floating-point elements in the first physical vector register and the second physical vector register respectively to obtain multiple third floating-point elements;

[0026] Each third floating-point element is written to the first buffer register, and the third floating-point elements in the first buffer register are then reduced by vector-level unordered summation to obtain the vector reduction result of the vector source operands.

[0027] Furthermore, in the floating-point unordered addition method provided in this application, the logic vector register includes a first physical vector register, a second physical vector register, and a third physical vector register. The physical bit width of the first physical vector register is twice the bit width of the second physical vector register, and the physical bit width of the second physical vector register is equal to the bit width of the third physical vector register.

[0028] Perform vector-level unordered summation and reduction on multiple second floating-point elements in the logic vector register to obtain the vector reduction result of the vector source operands, including:

[0029] If the vector length multiplier is greater than or equal to the length multiplier threshold, perform a floating-point unordered addition operation on the second floating-point element in the first physical vector register to obtain multiple fourth floating-point elements;

[0030] Each fourth floating-point element is written to the second buffer register; the physical bit width of the second buffer register is equal to the physical bit width of the second physical vector register;

[0031] Perform an out-of-order floating-point addition operation on the fourth floating-point element in the second buffer register and the second floating-point element in the second physical vector register to obtain multiple fifth floating-point elements;

[0032] Each fifth floating-point element is written to the third buffer register; the physical width of the third buffer register is equal to the physical width of the second buffer register.

[0033] The fifth floating-point element in the third buffer register and the second floating-point element in the third physical vector register are subjected to vector-level unordered summation and reduction to obtain the vector reduction result of the vector source operand.

[0034] Furthermore, in the floating-point unordered addition method provided in this application, multiple second floating-point elements in the logic vector register are subjected to vector-level unordered summation and reduction to obtain the vector reduction result of the vector source operands, including:

[0035] If the vector length ratio is less than the length ratio threshold, a multi-level parallel floating-point adder is used to perform vector-level unordered summation and reduction on multiple second floating-point elements in the logic vector register to obtain the vector reduction result.

[0036] Furthermore, in the floating-point unordered addition method provided in this application, before performing vector-level unordered summation and reduction on multiple second floating-point elements in the logic vector register to obtain the vector reduction result of the vector source operands, the method further includes:

[0037] The first vector operands are preprocessed to obtain the preprocessed first vector operands.

[0038] Secondly, this application also provides a floating-point unordered addition arithmetic device, comprising:

[0039] The acquisition unit is used to acquire vector source operands; the vector source operands include multiple first floating-point elements.

[0040] A precision expansion unit is used to expand the precision of each first floating-point element to obtain a first vector operand; the first vector operand includes multiple second floating-point elements, and the ratio between the number of floating-point bits of the second floating-point elements and the number of floating-point bits of the first floating-point elements is an integer greater than or equal to 2.

[0041] A write unit is used to write the first vector operand into a logical vector register; the logical vector register includes at least one physical vector register.

[0042] The reduction unit is used to perform vector-level unordered summation and reduction on multiple second floating-point elements in the logic vector register to obtain the vector reduction result of the vector source operands;

[0043] The accumulation unit is used to accumulate the vector reduction result with the least significant element in the scalar register to obtain the result of the vector source operand operation.

[0044] Thirdly, this application also provides a processor that uses RISC-V vector unordered reduction floating-point summation instructions to execute the floating-point unordered addition method provided in the first aspect.

[0045] The floating-point unordered addition method provided in this application obtains a vector source operand and extends the precision of each first floating-point element in the vector source operand to obtain a first vector operand composed of multiple second floating-point elements. Simultaneously, the first vector operand is written into a logic vector register for unordered summation and reduction at the vector level, thereby obtaining the vector reduction result of the vector source operand. Finally, the vector reduction result is accumulated with the least significant bit element in the scalar register to obtain the operation result of the vector source operand. This method not only significantly improves the numerical stability of the reduction process but also effectively solves the technical problem of the performance bottleneck of vector reduction operation in the RISC-V vector extension instruction set. Therefore, it provides a better hardware implementation scheme for high-performance, high-precision, and highly compatible vector floating-point accelerators. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic flowchart of a floating-point unordered addition operation method provided in an embodiment of this application;

[0048] Figure 2 This is a first scenario architecture diagram for floating-point unordered addition operations provided in an embodiment of this application;

[0049] Figure 3 This is a second scenario architecture diagram for floating-point unordered addition operations provided in an embodiment of this application;

[0050] Figure 4 This is a third scenario architecture diagram for floating-point unordered addition operations provided in an embodiment of this application;

[0051] Figure 5 A schematic block diagram of a floating-point unordered addition arithmetic device provided in an embodiment of this application. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0053] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0054] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0055] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0056] Furthermore, in this application, unless otherwise explicitly specified or limited in the embodiments, the terms "installation," "connection," "joining," and "fixing" appearing in the embodiments should be interpreted broadly. For example, a connection can be a fixed connection, a detachable connection, or an integral part; it can also be a mechanical connection, an electrical connection, etc. Of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication between two components, or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific implementation.

[0057] In related technologies, floating-point parallel addition tree structures are used to implement vector reduction operations. The core idea is to add N inputs pairwise to form a balanced binary tree. The parallel depth is log2N.

[0058] The floating-point parallel addition tree structure contains multiple levels of parallel floating-point addition units, connected by pipelined registers, for parallel reduction and summation of input floating-point operands. Each floating-point addition node contains submodules for exponent comparison, mantissa alignment, mantissa addition, normalization, and rounding. To comply with the IEEE 754 standard, it is typically designed with 3-5 pipelined stages. Furthermore, the floating-point parallel addition tree structure can be implemented using either an ordered addition tree (first sorted by exponent) or an unordered addition tree (direct pairwise addition) depending on requirements.

[0059] However, the unordered reduction summation process using the vfredusum.vs instruction requires complex hardware architecture, has a long timing path and poor scalability, and has low computational accuracy, making it difficult to meet the performance requirements of high throughput and low latency.

[0060] Taking 8-way floating-point summation as an example, the floating-point parallel addition tree structure has the characteristics of high parallelism, latency proportional to log2N, and area proportional to N. A single floating-point addition node includes sub-modules such as exponent comparison, mantissa alignment, mantissa addition, normalization, and rounding. Among them, exponent alignment determines the upper limit of latency, mantissa width determines hardware complexity, and rounding must conform to the IEEE 754 standard.

[0061] To improve frequency, practical designs typically employ multi-stage pipelines. For example, in an FP32 parallel adder tree, each adder contains 3-5 stages of pipeline, including input registers, exponent comparison and mantissa alignment, mantissa addition, normalization, rounding, and packing. However, in engineering practice, there are two main variants: ordered adder trees and unordered adder trees. Unordered adder trees directly add pairs of elements, resulting in minimal latency, but the result is order-dependent. They are commonly used in the RISC-V vfredusum instruction implementation.

[0062] However, in the RISC-V vector extension instruction set, the traditional floating-point parallel addition tree structure faces the problems of complex hardware implementation and poor scalability when implementing vector-widened unordered floating-point reduction instructions such as vfwredusum.vs. Not only does it require repeatedly designing dedicated reduction paths for different LMUL values, resulting in redundant control logic, large area overhead, and difficulty in pipelining, but also, because the original floating-point element bit width is low (such as FP16), directly performing unordered reduction at low bit width can easily cause the phenomenon of large numbers eating small numbers, resulting in serious loss of intermediate calculation precision, ultimately affecting the overall numerical stability and instruction semantic fidelity.

[0063] To address this, this application provides a floating-point unordered addition method. This method obtains a vector source operand and extends the precision of each first floating-point element in the vector source operand to obtain a first vector operand composed of multiple second floating-point elements. Simultaneously, the first vector operand is written into a logic vector register for unordered summation and reduction at the vector level, resulting in a vector reduction result for the vector source operand. Finally, the vector reduction result is accumulated with the least significant bit in the scalar register to obtain the operation result of the vector source operand. This method not only significantly improves the numerical stability of the reduction process but also effectively solves the technical problem of the performance bottleneck of vector reduction operations in the RISC-V vector extension instruction set. Therefore, it provides a better hardware implementation scheme for high-performance, high-precision, and highly compatible vector floating-point accelerators.

[0064] The instruction prefetching method provided in this application will be described in detail below.

[0065] like Figure 1 As shown, the method includes the following steps S110 to S150.

[0066] S110, Obtain the vector source operand; the vector source operand includes multiple first floating-point elements.

[0067] In this embodiment, the vector source operand is the input data in the vs2 register group specified by the RISC-V vector instruction vfwredusum.vs; the first floating-point element is a floating-point number in single-precision (FP32), half-precision (FP16), or BFloat16 format conforming to the IEEE 754 standard, and its bit width can be denoted as SEW; multiple first floating-point elements are organized into a vector form in logical order, and the number is determined by the vector length VL and LMUL; the acquisition of the vector source operand is completed by the vector execution unit reading from the vector register file without changing its original numerical representation and arrangement order.

[0068] As an example, this application can acquire all first floating-point elements from the vs2 register set in parallel from the vector register file by the vector execution unit.

[0069] As another example, this application can also trigger concurrent reading of multiple ports based on the instruction decoding result, and synchronously load each first floating-point element in VS2 into the preprocessing buffer queue to complete the acquisition.

[0070] Alternatively, this application can also achieve the acquisition by performing position alignment on the first floating-point element read across registers using a vector rearrangement unit before sending it to the subsequent precision extension module.

[0071] For example, when the vfwredusum.vs instruction is configured with SEW=32 and LMUL=2, vs2 corresponds to two consecutive 512-bit physical vector registers v2 and v3, which contain a total of 32 FP32 elements. The vector execution unit synchronously reads all 32 FP32 elements in v2 and v3 through dual parallel read ports to form vector source operands, which can then provide an input basis for subsequent precision expansion.

[0072] S120. Expand the precision of each first floating-point element to obtain a first vector operand; the first vector operand includes multiple second floating-point elements, and the ratio between the number of floating-point bits of the second floating-point elements and the number of floating-point bits of the first floating-point elements is an integer greater than or equal to 2.

[0073] In this embodiment, precision expansion can be understood as the process of losslessly mapping each first floating-point element from SEW-bit floating-point format to 2×SEW-bit floating-point format.

[0074] The number of floating-point bits of the second floating-point element (e.g., FP64, FP32, or FP16, depending on the SEW value) is an integer multiple of the number of floating-point bits of the first floating-point element. This integer multiple can be 2, 4, or higher, but at least 2.

[0075] At the same time, in the process of expanding the first floating-point element, the original floating-point value can be kept unchanged, that is, the mathematical equivalence constraint is satisfied.

[0076] The first vector operand can serve as the basic data carrier for all subsequent calculations. Its number of elements is the same as that of the vector source operand, only the data bit width is increased.

[0077] As an example, this application can obtain the second floating-point element by means of the combined effect of sign bit copying, exponent bias adjustment and mantissa zero extension.

[0078] As another example, this application can also obtain the second floating-point element by combining the floating-point number format conversion rules defined by the IEEE 754 standard with the means of hardware-specific extension paths.

[0079] In addition, this application can also obtain the second floating-point element by means of synchronously completing the expansion of all first floating-point elements within one clock cycle through a vector-level parallel floating-point format conversion unit.

[0080] For example, when the vector source operand is in FP32 format, SEW=32, and LMUL=2, vs2 corresponds to two consecutive 512-bit physical vector registers v2 and v3, containing a total of 32 FP32 elements. After precision expansion, each FP32 element is losslessly converted to FP64 format, forming the first vector operand composed of 32 FP64 elements, with a total bit width of 2048 bits, which can be mapped to the logical vector register.

[0081] The first floating-point element can be any one of 8 bits, 16 bits, 32 bits, and 64 bits; the second floating-point element can be any one of 16 bits, 32 bits, 64 bits, and 128 bits.

[0082] In some embodiments, precision expansion of each first floating-point element to obtain a first vector operand includes: biasing the exponent field of each first floating-point element to obtain an expanded exponent field, and performing zero expansion at the least significant bit of the mantissa of each first floating-point element to obtain an expanded mantissa; and combining the sign bit of the first floating-point element, the expanded exponent field, and the expanded bit length to form a second floating-point element.

[0083] In this embodiment, precision expansion can be understood as the process of losslessly mapping each first floating-point element from SEW bit floating-point format to 2×SEW bit floating-point format; the number of floating-point bits of the second floating-point element (e.g., FP64, FP32 or FP16, depending on the SEW value) is an integer multiple of the number of floating-point bits of the first floating-point element, and this integer multiple can be 2, 4 or higher, but at least 2.

[0084] During the expansion of the first floating-point element, the sign bit of each first floating-point element can be directly copied to form the sign bit of the second floating-point element; the exponent field of each first floating-point element is biased to make the values ​​before and after expansion equal; for example, when SEW=32 (FP32), the original exponent bias is 127 and the target exponent bias is 1023, so the new exponent = original exponent - 127 + 1023 = original exponent + 896; the mantissa of each first floating-point element is zero-extended, that is, the high bits of the original mantissa are aligned and filled into the high bit area of ​​the target mantissa, and the low bits are padded with zeros; for example, the mantissa of FP32 is 23 bits, so when it is expanded to FP64, it is placed in the high 23 bits and padded with zeros in the low 41 bits.

[0085] As an example, this application can obtain the second floating-point element by means of the combined effect of sign bit copying, exponent bias adjustment and mantissa zero extension.

[0086] As another example, this application can also obtain the second floating-point element by combining the floating-point number format conversion rules defined by the IEEE 754 standard with the means of hardware-specific extension paths.

[0087] In addition, this application can also obtain the second floating-point element by means of synchronously completing the expansion of all first floating-point elements within one clock cycle through a vector-level parallel floating-point format conversion unit.

[0088] For example, when the first floating-point element is in FP32 format, its sign bit occupies 1 bit, the exponent field occupies 8 bits (with an offset value of 127), and the mantissa field occupies 23 bits (with an implicit high-order 1); the target second floating-point element is in FP64 format, with a sign bit occupying 1 bit, the exponent field occupies 11 bits (with an offset value of 1023), and the mantissa field occupies 52 bits (with an implicit high-order 1); then the expansion process is as follows: the sign bit is directly copied; the exponent field is adjusted to the original exponent value. 127 + 1023 = original exponent value + 896; the mantissa field places the original 23-bit explicit mantissa into the high 23 bits of the FP64 mantissa, and pads the low 29 bits with zeros; finally, they are combined to form the second floating-point element in FP64 format.

[0089] In some embodiments, before writing the first vector operand into the logic vector register, the method further includes: determining the vector length multiplier of the control logic vector register based on the vector bit width of the first vector operand and the physical bit width of the physical vector register; and selecting at least one physical vector register to form the logic vector register based on the vector length multiplier.

[0090] In this embodiment, the Vector Length Multiplier (VLMM) can be understood as the ratio of the number of physical vector registers mapped by the logical vector registers to the number of physical vector registers in the baseline configuration. It characterizes the scaling of the current vector operands relative to the capacity of a single physical vector register. It is determined by the LMUL (Vector Length Multiplier) field in RISC-V Vector Extension (RVV) and has a value of 2. m (m is an integer, m∈[-3,3]), corresponding to LMUL=1 / 8, 1 / 4, 1 / 2, 1, 2, 4, 8.

[0091] In the RISC-V Vector Extension (RVV) architecture, the vector length multiplier is used to characterize the logical width configuration of the vector register set, and its value directly determines the number of physical vector registers required.

[0092] The vector width is equal to the product of the effective vector length (VL) and the standard element width (SEW). The physical width of the physical vector register is VLEN. Therefore, LMUL = (VL × SEW) / VLEN, where the ratio is an integer or a fraction and is encoded in the vtype control register in the RVV specification. The relationship between LMUL and the physical vector register is shown in Table 1.

[0093] Table 1

[0094]

[0095] Among them, LMUL can be determined during the instruction decoding stage and used as a pre-control signal for hardware resource configuration to drive subsequent register address generation, data path width configuration and reduction structure selection.

[0096] The vector bit width of the first vector operand is determined by the element bit width (Standard Element Width, SEW) of the vector source operand and the number of vector elements (VLMAX), i.e., vector bit width = SEW × VLMAX.

[0097] The physical bit width of the physical vector register is a fixed value, for example, 512 bits; therefore, the vector length multiplier = (SEW × VLMAX) / 512.

[0098] As an example, this application can calculate the vector length multiplier using a hardware decoding circuit based on the SEW and VLMAX parameters of the vector source operand.

[0099] As another example, this application can also read the current effective vector length multiplier based on the preset LMUL configuration register.

[0100] For example, in a RISC-V vector processor, when the instruction `vfwredusum.vs` is executed with `SEW=32` and `VLMAX=2048`, the vector width of the first vector operand is 32 × 2048 = 65536 bits; the physical vector register width is 512 bits; therefore, the vector length multiplier = [65536 / 512] = 128. However, since the RVV standard specifies that LMUL supports a maximum of 8, LMUL=8 is actually used, which requires the use of 8 512-bit physical vector registers (such as v2–v9) to form a logical vector register. Subsequently, the precision-extended 64-bit floating-point elements are sequentially distributed and written into all 8 physical vector registers mapped by this logical vector register, providing a data basis for subsequent vector-level unordered summation and reduction.

[0101] S130. Write the first vector operand into the logical vector register; the logical vector register includes at least one physical vector register.

[0102] In this embodiment, the logical vector register is an address-contiguous, bit-width-configurable data storage view abstracted from the vector execution unit, and its physical implementation consists of one or more 512-bit physical vector registers. The number of physical vector registers can be determined by the vector length multiplier LMUL and the total bit width of the first vector operand.

[0103] When LMUL=1, the logical vector register is mapped to a single physical vector register; when LMUL>1, the logical vector register is mapped to LMUL physical vector registers.

[0104] During the process of writing the first vector operand to the logical vector register, the first vector operand can be split into elements and allocated to the corresponding physical vector registers in element order, while keeping the logical index relationship of the elements unchanged.

[0105] As an example, this application can obtain the physical vector register allocation strategy by looking up a table based on the vector length multiplier LMUL, and complete the writing by routing each segment of the first vector operand to the corresponding physical vector register through a multiplexer.

[0106] As another example, this application can also complete the writing process by dynamically decoding the vector control field to generate a register write enable signal and address offset, and driving the parallel writing of each physical vector register.

[0107] In addition, this application can also use a register renaming mechanism to establish a mapping table between logical register names and physical vector register groups, and complete the writing by means of table lookup and update.

[0108] For example, when LMUL=2 and the first vector operand contains 32 FP64 elements, the logic vector register consists of two 512-bit registers, v2 and v3. The reduction process first performs pairwise addition of 16 FP64 elements in v2 to obtain 8 partial sums. At the same time, it performs pairwise addition of another 16 FP64 elements in v3 to obtain another 8 partial sums. Then, the 16 partial sums are paired up and output as a unique FP64 reduction result after three-stage parallel addition.

[0109] In some embodiments, writing the first vector operand into a logical vector register includes: if the vector length ratio is less than a preset length ratio threshold, writing the first vector operand into a physical vector register; if the vector length ratio is greater than or equal to the length ratio threshold, writing the first vector operand into multiple physical vector registers.

[0110] In this embodiment, the length multiplier threshold can be understood as a pre-set threshold value used to distinguish register allocation strategies, such as 1, 2, or 4. Its value is determined based on the target processor's physical vector register bit width (e.g., 512 bits), the maximum supported SEW (e.g., 64 bits), and the vector length distribution in typical application scenarios. The length multiplier threshold is fixed in the control logic during hardware initialization and does not change dynamically with runtime instructions. In this application, the length multiplier threshold is 2.

[0111] As an example, this application can generate a single register write enable signal by the control unit based on the comparison result of the vector length ratio and the length ratio threshold, and drive the data path to write the first vector operand completely into all valid bit fields of a physical vector register.

[0112] As another example, this application can also, based on the comparison result, trigger a single register address decoding path by the decoding unit to map the first vector operands to the low-order starting address space of the specified physical vector register in natural order.

[0113] For example, when the RISC-V instruction stream decodes the vfwredusum.vs instruction and the current LMUL=1, the control logic determines that the vector length multiplier is 1, which is less than the length multiplier threshold. The length multiplier threshold is 2. Therefore, the full-width write enable of the v2 register is activated, while the write paths of other vector registers such as v3 and v4 are blocked. At this time, the first vector operand (such as 8 FP32 elements) from memory or the previous pipeline is extended to form 8 FP64 elements, which are written continuously into the 0~511 bit range of the v2 register without the need for cross-register splitting or rearrangement.

[0114] In some embodiments, writing the first vector operand to multiple physical vector registers includes: splitting the first vector operand into multiple groups of floating-point numbers based on a vector length multiplier; each group of floating-point numbers includes multiple second floating-point elements; inputting the multiple groups of floating-point numbers into a physical vector register; and the multiple groups of floating-point numbers correspond to one physical vector register.

[0115] In this embodiment, the first vector operand is a widened vector data containing multiple second floating-point elements after precision expansion, and its total bit width is equal to the product of the number of vector elements and the bit width of a single second floating-point element.

[0116] Multiple sets of floating-point numbers can be understood as subsets of data obtained by dividing the first vector operands into continuous, non-overlapping, equal-length, or unequal-length segments along the element dimension, based on the vector length ratio and the physical bit width of each physical vector register. The number of second floating-point elements in each set depends on the ratio of the available bit width of the physical vector register allocated to that set to the bit width of a single second floating-point element.

[0117] As an example, this application can determine the number of second floating-point elements in each group based on the divisibility relationship between the vector length ratio and the physical vector register bit width, and sequentially extract the corresponding number of consecutive elements to form a group of floating-point numbers.

[0118] As another example, this application can also divide the total number of elements of the first vector operand into integers according to the vector length ratio, so that the sum of the number of elements in each group is equal to the total number, and the bit width of each group does not exceed the physical bit width of a single physical vector register.

[0119] For example, when the vector length multiplier is 2, the physical bit width of the physical vector register is 512 bits, and the second floating-point element is FP64 (i.e., 64 bits), each physical vector register can hold a maximum of 8 second floating-point elements; then the first 8 second floating-point elements in the first vector operand constitute the first group of floating-point numbers, and the last 8 second floating-point elements constitute the second group of floating-point numbers; the two groups are written into two different physical vector registers respectively.

[0120] S140. Perform vector-level unordered summation and reduction on multiple second floating-point elements in the logic vector register to obtain the vector reduction result of the vector source operands.

[0121] Specifically, this application can perform vector-level unordered summation and reduction on multiple second floating-point elements in the logic vector register based on LMUL to obtain the vector reduction result of the vector source operand.

[0122] In this embodiment, unordered summation reduction at the vector level can be understood as a reduction operation that does not depend on the order of input elements and uses pairwise parallel addition as its core mechanism.

[0123] Multiple second floating-point elements refer to all the second floating-point elements that have been written into the logical vector register, and their number is equal to the number of first floating-point elements in the vector source operand.

[0124] The vector reduction result is a single floating-point value with the same bit width as the second floating-point element.

[0125] Specifically, in the process of vector-level unordered summation and reduction of multiple second floating-point elements in the logic vector register, all second floating-point elements in the logic vector register can be divided into several pairs, and each pair of elements is input to a floating-point addition unit; each floating-point addition unit performs IEEE 754-compatible unordered floating-point addition operations in parallel and outputs a partial sum; the partial sums of the previous level are paired again and parallel addition is repeated until only one result remains; the reduction process adopts a balanced binary tree structure.

[0126] As an example, this application can reduce the number of floating-point elements by performing pairwise parallel additions on the second floating-point element level by level according to a balanced binary addition tree structure.

[0127] As another example, this application can also complete the reduction by first reducing local element subsets and then merging sub-results according to the hierarchical and segmented addition tree structure.

[0128] In addition, this application can also adopt a serial-parallel hybrid addition structure with pipeline stages to reduce single-stage latency while ensuring throughput.

[0129] For example, when LMUL=2 and the first vector operand contains 32 FP64 elements, the logic vector register consists of two 512-bit registers, v2 and v3. The reduction process first performs pairwise addition of 16 FP64 elements in v2 to obtain 8 partial sums. At the same time, it performs pairwise addition of another 16 FP64 elements in v3 to obtain another 8 partial sums. Then, the 16 partial sums are paired up and output as a unique FP64 reduction result after three levels of parallel addition.

[0130] In some embodiments, such as Figure 3As shown, the logical vector register includes a first physical vector register and a second physical vector register. The physical bit width of the first physical vector register is equal to the physical bit width of the second physical vector register. Multiple second floating-point elements in the logical vector register are subjected to vector-level unordered summation and reduction to obtain the vector reduction result of the vector source operand. This includes: if the vector length multiplier is greater than or equal to the length multiplier threshold, performing vector-level unordered summation and reduction on the second floating-point elements in the first and second physical vector registers respectively to obtain multiple third floating-point elements; writing each third floating-point element into a first buffer register, and performing vector-level unordered summation and reduction on the third floating-point elements in the first buffer register to obtain the vector reduction result of the vector source operand.

[0131] In this embodiment, the first physical vector register and the second physical vector register have the same physical bit width, which can be 512 bits; the second floating-point element is a floating-point number formed after precision expansion, and its floating-point number is an integer multiple of the floating-point number of the first floating-point element and not less than 2 times; the third floating-point element can be understood as a partial sum obtained by vector-level unordered summation and reduction of all the second floating-point elements in the first physical vector register or the second physical vector register, and its data type is consistent with the second floating-point element.

[0132] As an example, this application can perform parallel reduction of all second floating-point elements in the first physical vector register using a balanced binary addition tree structure based on the method of vector-level unordered summation reduction, to obtain a third floating-point element.

[0133] As another example, this application can also perform parallel reduction of all second floating-point elements in the second physical vector register using a hierarchical and segmented addition tree structure based on the method of vector-level unordered summation and reduction, to obtain another third floating-point element.

[0134] In addition, this application can also reduce the first physical vector register and the second physical vector register by using a pipelined serial-parallel hybrid addition structure, based on the method of vector-level unordered summation and reduction, and output a third floating-point element for each.

[0135] For example, when LMUL=2, the vector source operands are allocated to the first physical vector register v2 and the second physical vector register v3; vector-level unordered summation reduction is performed on all second floating-point elements in v2 to obtain the third floating-point element R1; at the same time, the same reduction operation is performed on all second floating-point elements in v3 to obtain the third floating-point element R2; R1 and R2 together constitute the first stage output of the two-level reduction.

[0136] In some embodiments, such as Figure 4As shown, the logical vector register includes a first physical vector register, a second physical vector register, and a third physical vector register. The physical bit width of the first physical vector register is twice the bit width of the second physical vector register, and the physical bit width of the second physical vector register is equal to the bit width of the third physical vector register. Multiple second floating-point elements in the logical vector register are subjected to vector-level unordered summation and reduction to obtain the vector reduction result of the vector source operands. This includes: if the vector length multiplier is greater than or equal to the length multiplier threshold, performing unordered floating-point addition on the second floating-point elements in the first physical vector register to obtain multiple fourth floating-point elements; and then... Four floating-point elements are written to the second buffer register; the physical bit width of the second buffer register is equal to the physical bit width of the second physical vector register; the fourth floating-point element in the second buffer register is added to the second floating-point element in the second physical vector register in an unordered floating-point addition operation to obtain multiple fifth floating-point elements; each fifth floating-point element is written to the third buffer register; the physical bit width of the third buffer register is equal to the physical bit width of the second buffer register; the fifth floating-point element in the third buffer register is reduced to the second floating-point element in the third physical vector register in an unordered vector-level summation to obtain the vector reduction result of the vector source operand.

[0137] In this embodiment, the first physical vector register can be understood as the one with the largest bit width among the three physical vector registers that constitute the logical vector register. Its physical bit width is twice that of the second and third physical vector registers. The first physical vector register is used to store a portion of the second floating-point elements after precision expansion, and its number of elements is greater than that of the other two physical vector registers.

[0138] The second floating-point element can be understood as a floating-point data unit with double the number of floating-point bits obtained according to the precision expansion operation in this application. Its format conforms to the IEEE 754 standard, and its numerical value is consistent with that of the original first floating-point element.

[0139] The fourth floating-point element can be understood as a new floating-point data unit generated by performing a pairwise unordered floating-point addition operation on all the second floating-point elements in the first physical vector register. Its bit width is the same as that of the second floating-point elements, but its value is the sum of the corresponding two elements.

[0140] As an example, this application can perform pairwise addition on the second floating-point elements with adjacent numbers in the first physical vector register according to the vector-level parallel floating-point addition tree structure to obtain the fourth floating-point element.

[0141] As another example, this application can also perform parallel addition on a subset of second floating-point elements in the first physical vector register, which is divided according to a preset grouping strategy, based on a segmented pipelined floating-point adder array, to obtain a fourth floating-point element.

[0142] In addition, this application can also use a floating-point addition path with a normalized delay hiding mechanism to immediately start mantissa addition and simultaneously perform exponent comparison after mantissa alignment is completed, so as to generate a fourth floating-point element.

[0143] For example, when LMUL=4 and SEW=32, the first physical vector register is 1024-bit wide and can hold 32 second floating-point elements in FP64 format; after performing pairwise addition on them, 16 fourth floating-point elements in FP64 format are generated; these 16 elements are organized into a continuous data stream and are ready to be written to the second buffer register.

[0144] In some embodiments, performing vector-level unordered summation and reduction on multiple second floating-point elements in the logical vector register to obtain the vector reduction result of the vector source operand includes: if the vector length ratio is less than the length ratio threshold, using a multi-level parallel floating-point adder to perform vector-level unordered summation and reduction on multiple second floating-point elements in the logical vector register to obtain the vector reduction result.

[0145] In this embodiment, the multi-stage parallel floating-point adder can be understood as a set of hardware adder units that support IEEE 754 standard floating-point operations and have a multi-stage pipeline structure, with the number of its input ports matching the number of second floating-point elements contained in the logic vector register.

[0146] Specifically, if the vector length ratio is less than the length ratio threshold, it means that the first vector operand can be fully contained in a single physical vector register. In this case, there is no need for cross-register scheduling and splitting. All second floating-point elements are located on the data path of the same physical vector register. Thus, all second floating-point elements can be synchronously loaded and processed in parallel with minimal data path jump overhead, thereby avoiding the additional latency and control complexity introduced by moving between registers.

[0147] like Figure 2 As shown, in the process of performing vector-level unordered summation and reduction on multiple second floating-point elements in the logic vector register, this application can use all second floating-point elements as initial leaf nodes to construct a balanced binary addition tree structure. Each level performs pairwise floating-point addition, and the output partial sum is used as the input of the next level until the root node outputs a unique reduction result.

[0148] As an example, this application can perform pairwise addition on multiple second floating-point elements in a logic vector register based on a multi-level parallel floating-point adder with a balanced binary tree structure, and merge partial sums level by level to obtain a vector reduction result.

[0149] As another example, this application can also divide multiple second floating-point elements in the logic vector register into several equal-length sub-segments according to a multi-level parallel floating-point adder with a hierarchical segmented addition tree structure, first complete the internal reduction within each sub-segment, and then perform cross-segment pairwise addition on the reduction results of each sub-segment to obtain the vector reduction result.

[0150] In addition, this application can also insert one or more pipeline registers after each addition node according to a multi-stage parallel floating-point adder with a pipelined serial-parallel hybrid addition structure, and perform multi-cycle pipelined pairwise addition on multiple second floating-point elements in the logic vector register to obtain vector reduction results.

[0151] For example, when SEW=32 and LMUL=1, the vector source operands are 16 FP32 elements, which are expanded to form 16 second floating-point elements in FP64 format. The length multiplier threshold is set to 2. Since LMUL=1<2, the condition that the vector length multiplier is less than the length multiplier threshold is met. The logic vector register is mapped to a single 512-bit physical vector register. All 16 FP64 elements are loaded in parallel to the input of a multi-stage parallel floating-point adder. The adder adopts a 4-stage pipelined balanced binary tree structure (stage 0 inputs 16 FP64s, stage 1 outputs 8 partial sums, stage 2 outputs 4, stage 3 outputs 2, and stage 4 outputs 1 final reduction result), and completes all reduction operations within 5 clock cycles, outputting a vector reduction result in a single FP64 format.

[0152] In some embodiments, before performing vector-level unordered summation and reduction on multiple second floating-point elements in the logical vector register to obtain the vector reduction result of the vector source operand, the method further includes: preprocessing the first vector operand to obtain the preprocessed first vector operand.

[0153] In this embodiment, the first vector operand can be preprocessed before the vector-level unordered summation and reduction is executed. Specifically, data validity checks and semantic alignment operations can be performed on each floating-point element in the first vector operand to ensure that all floating-point elements input to the subsequent reduction process meet the semantic constraints of the IEEE 754 floating-point arithmetic specification and the RISC-V vector instruction vfredusum.vs. This avoids errors in the reduction result, hardware anomalies, or unreproducible instruction behavior due to invalid data. Thus, without increasing the complexity of the reduction core, the robustness, specification compliance, and industrial usability of the entire floating-point unordered addition operation method in a real processor environment can be significantly improved.

[0154] As an example, this application can perform a zeroing operation on the floating-point elements at the corresponding positions in the first vector operand according to the mask bit state of the vector mask vmask, so as to mask the elements that are turned off by the mask.

[0155] As another example, this application can also perform a set addendum identity operation on the floating-point elements at the corresponding positions in the first vector operand according to the mask bit state of the vector mask vmask, replacing the masked elements with addendum identity (i.e., 0.0) in the floating-point format that matches the current SEW.

[0156] For example, when the first vector operand is v2 = {1.0, 2.0, 3.0, 4.0}, the vector mask is vmask = 4'b0111, VL = 4, and SEW = 32, the preprocessing process first sets v2[0] to 0.0 according to vmask to obtain the intermediate vector {0.0, 2.0, 3.0, 4.0}; then, according to VL, it is confirmed that all four elements are within the valid range and no truncation is required; then, it is checked that each element is a normalized FP32 number and no normalization conversion is required; finally, the preprocessed vector source operand is output as {0.0, 2.0, 3.0, 4.0}, which will be written into the logic vector register and used as the input for vector-level unordered summation and reduction of multiple floating-point elements in the logic vector register in this application.

[0157] S150. The vector reduction result is added to the least significant element in the scalar register to obtain the result of the vector source operand operation.

[0158] In this embodiment, the scalar register can be understood as a general-purpose register or a dedicated scalar vector register used to store vs1 operands in the RISC-V architecture.

[0159] The least significant element can be understood as the floating-point element with index 0 in the vs1 register (i.e., vs1[0]), whose bit width is the same as that of the second floating-point element.

[0160] Accumulation can be understood as performing an IEEE 754-compatible floating-point unordered addition operation; the result of the operation is the final output value, whose bit width is the same as the second floating-point element, and is written to the target vector register vd[0].

[0161] As an example, this application can obtain the final result by directly inputting the vector reduction result and vs1[0] into a scalar floating-point adder to complete the accumulation.

[0162] As another example, this application can also broadcast the vector reduction result into a single-element vector, and then perform vector-level floating-point addition with the single-element vector formed by vs1[0] to obtain the final result.

[0163] In addition, this application can also utilize the scalar fusion path in the vector execution unit to obtain the final result by embedding an addition operation at the end of the reduction path.

[0164] For example, when the vector reduction result is a numerical value R in FP64 format and vs1[0] is the initial accumulated value S in FP64 format, the floating-point addition R+S is performed, the result T is output, and T is written to vd[0] to complete the entire instruction execution process.

[0165] In one embodiment, the order of cross-register reduction can also be changed. For example, the reduction across multiple 512-bit physical vector registers can be implemented by accumulating the physical vector registers in order. Alternatively, different physical vector register reduction orders can be used. For example, multiple physical vector registers can be grouped and accumulated in parallel first, and then the intermediate results after grouping can be further reduced at the vector level. By changing the accumulation order between physical vector registers, the correctness of the final reduction result can be maintained, and performance and area can be balanced according to the specific hardware resource configuration.

[0166] In one embodiment, the storage location of intermediate results can also be changed. For example, the intermediate result vector generated by cross-register accumulation can be stored in a vector register, a dedicated reduction buffer register, a temporary result register inside the vector execution unit, or a reusable vector pipeline register. Thus, by changing the storage location of intermediate results, the pressure on register ports and the utilization of hardware resources can be flexibly balanced in different microarchitecture designs.

[0167] In one embodiment, this application can also modify the vector reduction structure. For example, unordered vector reduction can be implemented using a multi-level floating-point parallel addition tree.

[0168] In addition, vector reduction can employ at least one of the following structures: balanced binary addition tree structure, hierarchical segmented addition tree structure, and serial-parallel hybrid addition structure with pipeline. Thus, based on the different characteristics of different reduction structures in terms of delay, area, and power consumption, unordered reduction operations of vector elements can be achieved.

[0169] In one embodiment, the application may also change the scalar fusion position. The reduction result may be accumulated with the scalar source operand vs1[0] after all vector reductions are completed, or the scalar value may be broadcast as a vector form to participate in the inter-register accumulation.

[0170] In the floating-point unordered addition method provided in this application, the vector source operand is obtained, and each first floating-point element in the vector source operand is precision extended to obtain a first vector operand composed of multiple second floating-point elements. At the same time, the first vector operand is written into a logic vector register for unordered summation and reduction at the vector level, thereby obtaining the vector reduction result of the vector source operand. Finally, the vector reduction result is accumulated with the least significant bit element in the scalar register to obtain the operation result of the vector source operand. This method can not only significantly improve the numerical stability of the reduction process, but also effectively solve the technical problem of the performance bottleneck of vector reduction operation in the RISC-V vector extension instruction set. Thus, it can provide a better hardware implementation scheme for high-performance, high-precision, and highly compatible vector floating-point accelerators.

[0171] In some embodiments, such as Figure 5 As shown, this application also provides a floating-point unordered addition operation device 200, including: an acquisition unit 210, a precision expansion unit 220, a writing unit 230, a reduction unit 240, and an accumulation unit 250.

[0172] The acquisition unit 210 is used to acquire the vector source operand, which includes multiple first floating-point elements. The precision expansion unit 220 is used to expand the precision of each first floating-point element to obtain a first vector operand. The first vector operand includes multiple second floating-point elements, and the ratio between the number of floating-point bits of the second floating-point elements and the number of floating-point bits of the first floating-point elements is an integer greater than or equal to 2. The writing unit 230 is used to write the first vector operand into a logical vector register. The logical vector register includes at least one physical vector register. The reduction unit 240 is used to perform vector-level unordered summation and reduction on the multiple second floating-point elements in the logical vector register to obtain the vector reduction result of the vector source operand. The accumulation unit 250 is used to accumulate the vector reduction result with the least significant bit of the scalar register to obtain the operation result of the vector source operand.

[0173] In the floating-point unordered addition apparatus 200 provided in this application, the vector source operand is obtained, and each first floating-point element in the vector source operand is precision extended to obtain a first vector operand composed of multiple second floating-point elements. At the same time, the first vector operand is written into a logic vector register for vector-level unordered summation and reduction, thereby obtaining the vector reduction result of the vector source operand. Finally, the vector reduction result is accumulated with the least significant bit element in the scalar register to obtain the operation result of the vector source operand. This not only significantly improves the numerical stability of the reduction process, but also effectively solves the technical problem of the performance bottleneck of vector reduction operation in the RISC-V vector extension instruction set. Thus, it provides a better hardware implementation scheme for high-performance, high-precision, and highly compatible vector floating-point accelerators.

[0174] Each module in the aforementioned floating-point unordered addition device 200 can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0175] In some embodiments, this application also provides a processor that uses RISC-V vector unordered reduction floating-point summation instructions to execute the floating-point unordered addition method provided in this application.

[0176] In this application, the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0177] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A floating-point unordered addition operation method, characterized in that, include: Obtain the vector source operands; the vector source operands include multiple first floating-point elements; Each of the first floating-point elements is precision extended to obtain a first vector operand; the first vector operand includes a plurality of second floating-point elements, and the ratio between the number of floating-point bits of the second floating-point elements and the number of floating-point bits of the first floating-point elements is an integer greater than or equal to 2. Write the first vector operand into a logical vector register; the logical vector register includes at least one physical vector register. The multiple second floating-point elements in the logic vector register are subjected to vector-level unordered summation and reduction to obtain the vector reduction result of the vector source operand; the unordered summation and reduction is implemented in parallel. The vector reduction result is accumulated with the least significant element in the scalar register to obtain the result of the vector source operand operation; The step of writing the first vector operand into the logic vector register includes: If the vector length ratio of the logical vector register is less than a preset length ratio threshold, the first vector operand is written into one of the physical vector registers; If the vector length multiplier is greater than or equal to the length multiplier threshold, the first vector operand is written to one of the physical vector registers; The step of writing the first vector operand to the plurality of physical vector registers includes: Based on the vector length multiplier, the first vector operand is split into multiple groups of floating-point numbers; each group of floating-point numbers includes multiple second floating-point elements; Multiple sets of floating-point numbers are input into one of the physical vector registers; multiple sets of floating-point numbers correspond to one physical vector register, and the number of second floating-point elements contained in each set of floating-point numbers depends on the ratio of the available bit width of the physical vector register to which the set is allocated to the bit width of a single second floating-point element.

2. The floating-point unordered addition method according to claim 1, characterized in that, The step of precision-expanding each of the first floating-point elements to obtain the first vector operands includes: The exponent field of each of the first floating-point elements is biased to obtain the expanded exponent field, and zero expansion is performed at the least significant bit of the mantissa of each of the first floating-point elements to obtain the expanded mantissa. The sign bit, the extended exponent field, and the extended number of bits of the first floating-point element are combined to form the second floating-point element.

3. The floating-point unordered addition method according to claim 1, characterized in that, Before writing the first vector operand into the logic vector register, the method further includes: The vector length multiplier controlling the logic vector register is determined based on the vector bit width of the first vector operand and the physical bit width of the physical vector register. Based on the vector length multiplier, at least one of the physical vector registers is selected to form the logical vector register.

4. The floating-point unordered addition method according to claim 3, characterized in that, The logical vector register includes a first physical vector register and a second physical vector register, wherein the physical bit width of the first physical vector register is equal to the physical bit width of the second physical vector register; The step of performing vector-level unordered summation and reduction on multiple second floating-point elements in the logic vector register to obtain the vector reduction result of the vector source operand includes: If the vector length multiplier is greater than or equal to the length multiplier threshold, the second floating-point elements in the first physical vector register and the second physical vector register are subjected to vector-level unordered summation and reduction to obtain multiple third floating-point elements. Each of the third floating-point elements is written into the first buffer register, and the third floating-point elements in the first buffer register are subjected to vector-level unordered summation and reduction to obtain the vector reduction result of the vector source operand.

5. The floating-point unordered addition method according to claim 3, characterized in that, The logic vector register includes a first physical vector register, a second physical vector register, and a third physical vector register. The physical bit width of the first physical vector register is twice the bit width of the second physical vector register, and the physical bit width of the second physical vector register is equal to the bit width of the third physical vector register. The step of performing vector-level unordered summation and reduction on multiple second floating-point elements in the logic vector register to obtain the vector reduction result of the vector source operand includes: If the vector length multiplier is greater than or equal to the length multiplier threshold, perform a floating-point unordered addition operation on the second floating-point element in the first physical vector register to obtain multiple fourth floating-point elements; Each of the fourth floating-point elements is written to the second buffer register; the physical bit width of the second buffer register is equal to the physical bit width of the second physical vector register; A floating-point unordered addition operation is performed on the fourth floating-point element in the second buffer register and the second floating-point element in the second physical vector register to obtain multiple fifth floating-point elements; Each of the fifth floating-point elements is written to the third buffer register; the physical bit width of the third buffer register is equal to the physical bit width of the second buffer register; The fifth floating-point element in the third buffer register is combined with the second floating-point element in the third physical vector register to perform vector-level unordered summation and reduction, thereby obtaining the vector reduction result of the vector source operand.

6. The floating-point unordered addition method according to claim 3, characterized in that, The step of performing vector-level unordered summation and reduction on multiple second floating-point elements in the logic vector register to obtain the vector reduction result of the vector source operand includes: If the vector length multiplier is less than the length multiplier threshold, a multi-level parallel floating-point adder is used to perform vector-level unordered summation and reduction on multiple second floating-point elements in the logical vector register to obtain the vector reduction result.

7. The floating-point unordered addition method according to any one of claims 1-6, characterized in that, Before performing vector-level unordered summation and reduction on the plurality of second floating-point elements in the logical vector register to obtain the vector reduction result of the vector source operand, the method further includes: The first vector operands are preprocessed to obtain the preprocessed first vector operands.

8. A processor, characterized in that, The floating-point unordered addition operation method according to any one of claims 1-7 is executed using RISC-V vector unordered reduction floating-point summation instructions.

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