Branch prediction processing architecture, branch prediction method, chip and equipment

Abstract

The present application relates to the technical field of branch prediction of processors, and provides a branch prediction processing architecture, a branch prediction method, a chip and a device, the architecture comprising: a branch information buffer for storing a plurality of entries, at least one entry being an extended entry, the extended entry comprising branch information of a first prediction block, and branch information of at least one second prediction block related to an execution order of the first prediction block; a branch predictor for generating branch direction prediction information in parallel for a branch instruction in the first prediction block and a branch instruction in the second prediction block based on branch information acquired from the extension entry in a single branch prediction operation; and the prediction logic unit is used for generating branch prediction results of the first prediction block and the second prediction block according to the branch direction prediction information and address information in the branch information. According to the embodiment of the invention, the single-cycle prediction bandwidth of the branch predictor can be improved on the premise that the hardware overhead and the time sequence pressure are not obviously increased.

Description

Technical Field

[0001] This application relates to the field of branch prediction technology for processors, and in particular to a branch prediction processing architecture, branch prediction method, chip, and device. Background Technology

[0002] Branch prediction refers to predicting which branch will be executed before the execution of a branch instruction is completed, in order to prepare for the next branch to be executed in advance, thereby improving the performance of the processor's instruction pipeline.

[0003] In modern high-performance processors, the performance of the branch predictor is crucial, directly impacting the efficiency of the instruction pipeline. As processor instruction fetch widths continue to increase, the bandwidth requirements for the branch predictor also rise. Multi-step branch predictors have emerged to address this need, aiming to generate multiple consecutive prediction blocks (prediction blocks) within a single prediction cycle to improve prediction throughput.

[0004] However, traditional multi-step branch predictor schemes have significant limitations. For example, in one known implementation, the predictor associates information from adjacent prediction blocks by expanding the entries in the Branch Target Buffer (BTB), thereby generating two prediction blocks in a single prediction. However, this scheme typically strictly limits the second prediction block from containing conditional branch instructions or requires additional serial prediction queries. This is because high-precision direction prediction of conditional branches heavily relies on complex predictors (such as Tagged Geometric History Length Branch Predictors, TAGE), and performing multiple serial queries on such predictors significantly increases critical path latency, causing timing issues and making it difficult to meet the frequency requirements of high-performance processors. Another known multi-step branching scheme attempts to piece together multiple prediction blocks within a fixed prediction window; if a prediction block jumps out of the prediction window, multi-step prediction cannot continue.

[0005] Therefore, existing multi-step branch predictors struggle to efficiently support scenarios where multiple consecutive prediction blocks generated in a single prediction may contain conditional branches, while maintaining high clock frequency and low hardware overhead. This limits further improvements in branch predictor bandwidth, becoming a key issue restricting processor front-end performance. Summary of the Invention

[0006] The purpose of this application is to provide a branch prediction processing architecture, branch prediction method, chip, and device to improve the single-cycle prediction bandwidth of the branch predictor without significantly increasing hardware overhead and timing pressure.

[0007] To achieve the above objectives, in one aspect, embodiments of this application provide a branch prediction processing architecture, including:

[0008] A branch information buffer is used to store multiple entries, at least one of which is an extension entry. The extension entry contains branch information of a first prediction block and branch information of at least one second prediction block related to the execution order of the first prediction block.

[0009] A branch predictor is used to generate branch direction prediction information in parallel for branch instructions in the first prediction block and branch instructions in the second prediction block, based on branch information obtained from the extended entry, in a single branch prediction operation.

[0010] The prediction logic unit is used to generate branch prediction results for the first prediction block and the second prediction block based on the branch direction prediction information and the address information in the branch information.

[0011] In the branch prediction processing architecture of this application embodiment, the extended entries include:

[0012] The location, type, and jump target address of the branch instruction within the first prediction block; and

[0013] The location, type, and jump target address of the branch instruction within the second prediction block.

[0014] In the branch prediction processing architecture of this application embodiment, the branch information buffer includes a branch target cache.

[0015] In the branch prediction processing architecture of this application embodiment, the branch predictor includes a branch predictor based on global history.

[0016] In the branch prediction processing architecture of this application embodiment, the number of the second prediction blocks is one; the global history-based branch predictor is a labeled geometric history length branch predictor TAGE.

[0017] In the single branch prediction operation, based on the branch information obtained from the extended entry, branch direction prediction information is generated in parallel for the branch instructions in the first prediction block and the branch instructions in the second prediction block, including:

[0018] In a single query operation, the context information used to distinguish the prediction block to which the branch instruction belongs is combined with the program counter value and global history information to form an index, and the TAGE entries of the corresponding branch instructions in the first prediction block and the second prediction block are queried from multiple prediction tables of the TAGE according to the index.

[0019] In the branch prediction processing architecture of this application embodiment, the context information is a prediction block identifier, and the prediction block identifier, the program counter value, and the global history information form the input parameters of the hash calculation function of the TAGE entry label of the TAGE.

[0020] In the branch prediction processing architecture of this application embodiment, the width of the prediction block identifier is one bit.

[0021] In the branch prediction processing architecture of this application embodiment, the context information is the identifier field contained in the TAGE entry of the TAGE.

[0022] In the branch prediction processing architecture of this application embodiment, generating branch prediction results for the first prediction block and the second prediction block based on the branch direction prediction information and the address information in the branch information includes:

[0023] When the branch instruction in the first prediction block that corresponds to the current program counter value satisfies the first condition, the end address of the first prediction block is determined to be the current program counter value plus the length of the first prediction block, only the branch prediction result of the first prediction block is generated, and the branch information of the second prediction block is determined to be invalid information; the first condition includes: the branch instruction is a conditional branch and the branch direction is non-jump;

[0024] When the branch instruction in the first prediction block that corresponds to the current program counter value satisfies the second condition, the jump target address of the first prediction block is used to determine the starting address of the second prediction block; the second condition includes: the branch instruction is an unconditional branch, or the branch instruction is a conditional branch and the branch direction is a jump;

[0025] If the branch instruction corresponding to the current program counter value in the first prediction block satisfies the second condition, and the branch instruction corresponding to the current program counter value in the second prediction block satisfies the second condition, the end address of the second prediction block is determined as the start address of the second prediction block plus the offset of the second prediction block, and the branch prediction result of the first prediction block and the branch prediction result of the second prediction block are generated.

[0026] If the branch instruction corresponding to the current program counter value in the first prediction block satisfies the second condition, and the branch instruction corresponding to the current program counter value in the second prediction block satisfies the first condition, the end address of the second prediction block is determined as the start address of the second prediction block plus the length of the second prediction block, and the branch prediction result of the first prediction block and the branch prediction result of the second prediction block are generated.

[0027] The branch prediction result includes the start address, end address, jump identifier, and jump target address of the corresponding prediction block.

[0028] In the branch prediction processing architecture of this application embodiment, the branch prediction processing architecture further includes:

[0029] An update logic unit is used to update the extended entries of the branch information buffer and the TAGE entries of the TAGE.

[0030] In the branch prediction processing architecture of this application embodiment, updating the extended entries of the branch information buffer includes:

[0031] For the first and second prediction blocks that have completed fetching or executing branch instructions, when the branch instruction meets a predetermined condition, the branch information of the branch instruction in the second prediction block is updated to the corresponding extension entry of the first prediction block.

[0032] In the branch prediction processing architecture of this application embodiment, the predetermined conditions include:

[0033] The branch instruction in the first prediction block is not an indirect branch instruction;

[0034] The second prediction block contains no more than one conditional branch instruction; and

[0035] The branch instruction in the second prediction block is not an indirect jump instruction outside the return class.

[0036] In the branch prediction processing architecture of this application embodiment, updating the TAGE entry of the TAGE includes:

[0037] First, update the TAGE entry corresponding to the branch instruction in the first prediction block; when the first prediction block stores an extended entry of the branch instruction, update the TAGE entry corresponding to the branch instruction in the second prediction block.

[0038] In the branch prediction processing architecture of this application embodiment, updating the TAGE entry of the TAGE further includes:

[0039] When there are no free TAGE entries in the branch predictor, replace the TAGE entry in the second prediction block that meets the specified conditions corresponding to the branch instruction; the specified conditions are the minimum useful value and / or the minimum saturation counter value.

[0040] On the other hand, embodiments of this application also provide a branch prediction method, including:

[0041] Branch information is obtained from the extended entries of the branch information buffer; the extended entries contain branch information of the first prediction block and branch information of at least one second prediction block related to the execution order of the first prediction block.

[0042] The branch predictor performs a single branch prediction operation based on the acquired branch information, so as to generate branch direction prediction information in parallel for the branch instructions in the first prediction block and the branch instructions in the second prediction block.

[0043] The prediction logic unit generates branch prediction results for the first prediction block and the second prediction block based on the branch direction prediction information and the address information in the branch information.

[0044] In the branch prediction method of this application embodiment, the number of the second prediction blocks is one, and the branch predictor is a direction predictor based on global history; the direction predictor based on global history includes a labeled geometric history length branch predictor TAGE.

[0045] In the branch prediction method of this application embodiment, the step of performing a single branch prediction operation based on the acquired branch information to generate branch direction prediction information in parallel for the branch instructions in the first prediction block and the branch instructions in the second prediction block includes:

[0046] In a single branch prediction operation based on the acquired branch information, the context information used to distinguish the prediction block to which the branch instruction belongs is combined with the program counter value and global history information to form an index, and the TAGE entries of the corresponding branch instructions in the first prediction block and the second prediction block are queried from multiple prediction tables of the TAGE according to the index.

[0047] In the branch prediction method of this application embodiment, generating branch prediction results for the first prediction block and the second prediction block based on the branch direction prediction information and the address information in the branch information includes:

[0048] When the branch instruction in the first prediction block that corresponds to the current program counter value satisfies the first condition, the end address of the first prediction block is determined to be the current program counter value plus the length of the first prediction block, only the branch prediction result of the first prediction block is generated, and the branch information of the second prediction block is determined to be invalid information; the first condition includes: the branch instruction is a conditional branch and the branch direction is non-jump;

[0049] When the branch instruction in the first prediction block that corresponds to the current program counter value satisfies the second condition, the jump target address of the first prediction block is used to determine the starting address of the second prediction block; the second condition includes: the branch instruction is an unconditional branch, or the branch instruction is a conditional branch and the branch direction is a jump;

[0050] If the branch instruction corresponding to the current program counter value in the first prediction block satisfies the second condition, and the branch instruction corresponding to the current program counter value in the second prediction block satisfies the second condition, the end address of the second prediction block is determined as the start address of the second prediction block plus the offset of the second prediction block, and the branch prediction result of the first prediction block and the branch prediction result of the second prediction block are generated.

[0051] If the branch instruction corresponding to the current program counter value in the first prediction block satisfies the second condition, and the branch instruction corresponding to the current program counter value in the second prediction block satisfies the first condition, the end address of the second prediction block is determined as the start address of the second prediction block plus the length of the second prediction block, and the branch prediction result of the first prediction block and the branch prediction result of the second prediction block are generated.

[0052] The branch prediction result includes the start address, end address, jump identifier, and jump target address of the corresponding prediction block.

[0053] In the branch prediction method of this application embodiment, the branch prediction method further includes:

[0054] The update logic unit updates the extended entry of the branch information buffer and the TAGE entry of the TAGE.

[0055] In the branch prediction method of this application embodiment, updating the extended entries of the branch information buffer includes:

[0056] For the first and second prediction blocks that have completed fetching or executing branch instructions, when the branch instruction meets a predetermined condition, the branch information of the branch instruction in the second prediction block is updated to the corresponding extension entry of the first prediction block.

[0057] In the branch prediction method of this application embodiment, the predetermined conditions include:

[0058] The branch instruction in the first prediction block is not an indirect branch instruction;

[0059] The second prediction block contains no more than one conditional branch instruction; and

[0060] The branch instruction in the second prediction block is not an indirect jump instruction outside the return class.

[0061] In the branch prediction method of this application embodiment, updating the TAGE entry of the TAGE includes:

[0062] First, update the TAGE entry corresponding to the branch instruction in the first prediction block; when the first prediction block stores an extended entry of the branch instruction, update the TAGE entry corresponding to the branch instruction in the second prediction block.

[0063] In the branch prediction method of this application embodiment, updating the TAGE entry of the TAGE further includes:

[0064] When there are no free TAGE entries in the branch predictor, replace the TAGE entry in the second prediction block that meets the specified conditions corresponding to the branch instruction; the specified conditions are the minimum useful value and / or the minimum saturation counter value.

[0065] On the other hand, embodiments of this application also provide a chip that includes the branch prediction processing architecture described above.

[0066] On the other hand, embodiments of this application also provide a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the computer program, when run by the processor, executes instructions of the above-described method.

[0067] As can be seen from the technical solutions provided in the embodiments of this application above, in the embodiments of this application, by expanding the branch information buffer so that an entry stores the branch information of at least two consecutive prediction blocks, and by modifying the query (i.e. branch prediction) method of the branch predictor, the branch predictor can generate corresponding branch direction prediction information in parallel for the branch instructions of the at least two consecutive prediction blocks based on the branch information obtained from the expanded entry in a single branch prediction operation (i.e., one branch prediction operation or one branch prediction cycle). This achieves an increase in the single-cycle prediction bandwidth of the branch predictor without significantly increasing hardware overhead and timing pressure, and can support continuous conditional branch prediction. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0069] Figure 1 The following is a structural block diagram of the branch prediction processing architecture in some embodiments of this application;

[0070] Figure 2 This illustration shows a schematic diagram of the content of an expanded BTB entry in an exemplary embodiment of this application;

[0071] Figure 3 A schematic diagram illustrating the expanded BTB entry content and related descriptions in an exemplary embodiment of this application is shown;

[0072] Figure 4 This illustration shows a schematic diagram of how a single TAGE direction prediction operation generates two branch direction prediction results in some embodiments of this application;

[0073] Figure 5 The following diagram illustrates the application environment of the branch prediction processing architecture in some embodiments of this application;

[0074] Figure 6 Flowcharts of branch prediction methods in some embodiments of this application are shown;

[0075] Figure 7 A structural block diagram of a computer device in some embodiments of this application is shown.

[0076] [Explanation of Labels in the Attached Image]

[0077] 11. Branch information buffer;

[0078] 12. Branch predictor;

[0079] 13. Predictive logic unit;

[0080] 14. Update the logic unit;

[0081] 702. Computer equipment;

[0082] 704, Processor;

[0083] 706. Memory;

[0084] 708. Drive mechanism;

[0085] 710. Input / output interfaces;

[0086] 712. Input devices;

[0087] 714. Output devices;

[0088] 716. Presentation equipment;

[0089] 718. Graphical User Interface;

[0090] 720. Network interface;

[0091] 722. Communication link;

[0092] 724. Communication bus. Detailed Implementation

[0093] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0094] It should be noted that in the embodiments of this application, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved are all information and data authorized and agreed upon by the user and fully authorized by all parties. That is, the acquisition, transmission, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations.

[0095] Figure 1 The diagram illustrates a branch prediction processing architecture in some embodiments of this application, which can be integrated into the processor front end. This architecture includes a branch information buffer 11, a branch predictor 12, and a prediction logic unit 13. The branch information buffer 11 stores multiple entries, at least one of which is an extended entry containing branch information for a first prediction block and branch information for at least one second prediction block related to the execution order of the first prediction block. The branch predictor 12, in a single branch prediction operation, generates branch direction prediction information in parallel for branch instructions in the first prediction block and branch instructions in the second prediction block based on the branch information obtained from the extended entries. The prediction logic unit 13 generates branch prediction results for the first and second prediction blocks based on the branch direction prediction information and address information in the branch information.

[0096] In the branch prediction processing architecture of this application embodiment, by expanding the branch information buffer, an extended entry stores the branch information of at least two consecutive prediction blocks (corresponding between consecutive prediction blocks). By modifying the query (i.e. branch prediction) method of the branch predictor, the branch predictor can generate corresponding branch direction prediction information in parallel for the branch instructions of the at least two consecutive prediction blocks based on the branch information obtained from the extended entry in a single branch prediction operation (i.e., one branch prediction operation or one branch prediction cycle). This improves the single-cycle prediction bandwidth of the branch predictor without significantly increasing hardware overhead and timing pressure, and supports continuous conditional branch prediction.

[0097] The branch prediction implemented in this application is for direct branch instructions within conditional branch instructions and unconditional branch instructions, but does not involve branch prediction for indirect branch instructions within unconditional branch instructions. Direct branch instructions have only one jump destination address, while indirect branch instructions have multiple jump destination addresses.

[0098] In some embodiments of this application, a single branch prediction operation (or one single branch prediction operation) refers to the complete micro-operation of the branch predictor receiving a query request, accessing the internal prediction table, and returning the branch prediction result (including the branch direction); similarly, a branch prediction cycle refers to the fixed clock cycle allocated by the processor front end to the branch predictor to complete one branch prediction operation.

[0099] In some embodiments of this application, each extended entry in the branch information buffer stores branch information for at least two consecutive prediction blocks. The branch predictor can, in a single branch prediction operation, generate corresponding branch direction prediction information in parallel for the branch instructions of these at least two consecutive prediction blocks based on the branch information obtained from the extended entries. For ease of understanding, in the following embodiments of this application, two consecutive prediction blocks (i.e., adjacent or consecutive first and second prediction blocks) will be used as examples for description, combined with... Figure 2 As shown, in this scenario, the extended entry includes: the location of the branch instruction within the first prediction block (e.g., Figure 2 offset), type (e.g.) Figure 2 (type) and jump target address (e.g. Figure 2 The target_addr in the second prediction block); and the location of the branch instruction within the second prediction block (e.g., Figure 2 offset2), type (e.g.) Figure 2 (type 2 in the text) and the jump target address (such as...) Figure 2(target_addr2 in the example). Obviously, this exemplary description should not be construed as the only limitation of this application. Based on the inventive concept of two consecutive prediction blocks in this application, it can be easily extended to the case of three (or more) consecutive prediction blocks.

[0100] In some embodiments of this application, the prediction block (PB) is the result of branch prediction. It starts with the target address of the previously predicted branch jump (taken) or the sequential address of the non-taken branch, and ends with the predicted branch instruction or processor-defined boundary conditions (such as PB length, 32B / 64B alignment, etc.). The address of the next sequential instruction in the PB or the jump address of the predicted branch instruction becomes the starting address of the PB in the next clock cycle.

[0101] In some embodiments of this application, the branch information buffer can be a branch target buffer (BTB). In other embodiments, the branch information buffer can also be other address index storage structures that can return branch information in at least two consecutive instruction blocks through a single query.

[0102] In some embodiments of this application, the branch predictor can be a global history-based branch predictor, such as TAGE. TAGE can, in a single query operation, combine the context information used to distinguish the prediction block to which the branch instruction belongs with the program counter value and global history information to form an index, and then query the TAGE entries for the corresponding branch instructions in the first prediction block and the second prediction block from multiple prediction tables of the TAGE according to the index. In other embodiments, the branch predictor can also be other branch predictors capable of returning branch information from at least two consecutive instruction blocks in a single query.

[0103] In some embodiments of this application, the prediction logic unit can be a dedicated combinational logic and sequential logic circuit, which can be constructed by basic logic gates such as AND gate, OR gate, NOT gate, adder, comparator, and multiplexer. It receives the level signals of the branch information buffer and the branch predictor, and outputs the branch prediction result within a single branch prediction cycle after a series of Boolean operations and arithmetic operations.

[0104] In some of the following embodiments, the following examples illustrate the use of two consecutive instruction blocks (a first prediction block (PB1) and a second prediction block (PB2)), a branch information buffer (BTB), and a branch predictor (TAGE).

[0105] (a) BTB entry expansion

[0106] The Branch Predictor (BTB) stores information such as the instruction type, address, and target address of known branch instructions. The branch predictor, in conjunction with the BTB and the branch direction predictor, determines which branch instruction will be taken (or not taken) and its target address. A known branch instruction refers to a branch instruction that has already been executed and whose actual branch information has been confirmed.

[0107] Traditional BTB entries include the following:

[0108] Offset: The offset value identifies the relative position of the branch instruction to the instruction block header (or branch offset), that is, the offset of the branch instruction's address within the instruction block. The branch predictor typically predicts all known branch instructions within an instruction block, and different processors define this instruction block differently. For example, for a 32b / 64b instruction block, offset requires 5 / 6 bits to specify any one of these bytes.

[0109] Type: Represents the type of branch instruction, such as conditional, direct, indirect, call / return, etc. For example, a 3-bit type field can represent 8 different types of instructions.

[0110] Target_addr: Represents the target address for the jump. Modern high-performance processors often use 32-bit / 64-bit virtual addresses, so the size of this field can be between 32-bit and 64-bit.

[0111] Combination Figure 3 As shown, in some embodiments of this application, in order to support the generation of branch prediction results for two prediction blocks in a single branch prediction operation, the BTB entry is expanded so that branch information for two prediction blocks can be obtained by searching the BTB once. The expanded BTB entry (i.e., the expanded entry) may include:

[0112] Offset: Represents the offset of the instruction address of a branch instruction (such as a branch instruction) within the instruction block. In an extended entry, in addition to the offset (Offset_A) of the branch (instruction) within PB1, it also includes the offset (Offset_B) of the branch (instruction) within PB2, which is adjacent to PB1.

[0113] Type: Indicates the type of branch instruction. In an extended entry, in addition to the type of the branch (instruction) within PB1 (Type_A), it also includes the type of the branch (instruction) within PB2, which is adjacent to PB1 (Type_B).

[0114] Target_addr: Represents the jump target address. In an extended entry, in addition to the jump target address (Target_A) of the branch (instruction) within PB1, it also includes the jump target address (Target_B) of the branch (instruction) within PB2, which is adjacent to PB1. Target_A is the destination address of the branch within PB1, i.e., the starting address of PB2; Target_B is the destination address of the branch within PB2, i.e., the starting address of the next prediction block (e.g., PB3).

[0115] In addition, Figure 3 In the BTB entries shown, Valid indicates a valid entry.

[0116] (II) Improvement of TAGE query method

[0117] The core idea of ​​TAGE is to use multiple prediction tables based on global historical records of different lengths, and to automatically select the most suitable (longest and matching) historical length for branch direction prediction through a tag matching mechanism.

[0118] In traditional TAGE, entries or table items in the prediction table (hereinafter referred to as TAGE entries) may include the following:

[0119] Tag: Generated by the Global History Register (GHR) and the instruction PC hash (i.e., address hash); Tag is the index for querying TAGE entries. When viewing a TAGE, only TAGE entries with the same Tag are considered. The GHR is a shift register used to record recent branch jump results. Different prediction tables require different bit values ​​in the GHR to calculate the index of the corresponding TAGE table (i.e., TAGE prediction table or prediction table).

[0120] Useful: This value is typically 2 bits. It is incremented when a branch prediction is correct to indicate that the prediction result is useful. Therefore, the Useful value can be called a useful value. When a valid TAGE entry needs to be replaced, the TAGE entry with a Useful value of 0 is preferred for replacement, that is, the least useful TAGE entry is replaced first.

[0121] Confidence Counter: A saturation counter, typically 3 bits, used to predict whether a branch instruction will jump. When updating the TAGE entry, if a branch instruction jumps, the corresponding counter value is increased by 1; otherwise, it is decreased by 1. During prediction, if the counter value is greater than a branch jump threshold (e.g., 3), a jump is predicted; otherwise, no jump is predicted.

[0122] To support branch prediction results that generate two prediction blocks in a single branch prediction operation, the TAGE entry has been expanded in some embodiments of this application. The expanded TAGE entry may include:

[0123] Tag: Represents the index of a TAGE entry. In some embodiments, the Tag can be generated by hashing the Global History Register (GHR) value and the Program Counter (PC) value of the branch instruction. In other embodiments, the Tag can also be generated by hashing the GHR value (i.e., the GHR value) + the PC value (i.e., the PC value) + the prediction block identifier. That is, the GHR value + the PC value + the prediction block identifier are used as input parameters for the hash calculation function that generates the Tag.

[0124] The prediction block identifier is a specific implementation of context information used to distinguish the prediction block to which a branch instruction belongs. The prediction block identifier is one bit wide. When querying a TAGE, the tag calculation requires the offset and offset2 stored in the GHR and BTB entries. Optionally, tag calculation for other TAGE variants may use address information and other information besides offset. In either case, since offset and offset2 record the address offset values ​​within the prediction block, not the complete address, their values ​​may be the same. The same value means that the first and second prediction blocks each have a branch at the same address offset. Therefore, it is necessary to distinguish between the two during tag calculation, making their tag values ​​different, so that different TAGE entries can be hit, improving prediction accuracy. A one-bit prediction block identifier can be used to indicate whether the current branch is in the first or second prediction block. For example, 0 represents the first prediction block, and 1 represents the second prediction block. By incorporating this bit of information into the tag calculation, different tag values ​​can be calculated for branches at the same address offset in the first and second prediction blocks.

[0125] In some embodiments of this application, other information formats can also be used to distinguish branches in two prediction blocks. For example, the TAGE entry can be expanded by adding one bit of information (i.e., adding an identifier field to the TAGE entry) to identify whether the TAGE entry belongs to the first prediction block or the second prediction block. In this case, the tag calculation may not include the above information, but the information bit can be compared during subsequent tag comparison.

[0126] In some embodiments of this application, if the tag calculation method naturally includes other information that can distinguish the predicted blocks (such as using the complete address of the predicted block), then no additional information is needed to distinguish the predicted blocks.

[0127] Useful: No change.

[0128] Confidence Counter: No change.

[0129] Combination Figure 4 As shown, based on the above extensions or modifications, TAGE's branch direction prediction can include:

[0130] (1) Upon receiving a starting address (the current PC value is used as the starting address of the first prediction block PB1), the extended BTB (e.g., an extended entry in the BTB) can be queried based on the PC value. A hit entry simultaneously provides: the branch offset, type, and target address of the first prediction block (PB1), and the branch offset, type, and target address of the second prediction block (PB2). In some embodiments of this application, if the extended entry does not exist (missed), it can revert to the single-step prediction mode (i.e., one prediction generates the branch direction prediction information of one prediction block at a time).

[0131] (2) Then, using the current PC value, GHR, and branch information such as Offset and Offset2 obtained from BTB, a TAGE query is performed, and two direction predictions are performed in parallel during the TAGE query: that is, based on Figure 4 In query context 1, query the TAGE table (each TAGE table contains multiple TAGE entries) to obtain the direction prediction of the conditional branch at Offset_A in PB1 (e.g., Figure 4 Dir_A), and based on Figure 4 In the query context 2, query the TAGE table to obtain the predicted direction of the conditional branch at Offset_B in PB2 (e.g., Figure 4 Dir_B).

[0132] This allows for the acquisition of branch direction prediction information for two prediction blocks in a single TAGE query, thus solving the time-critical path problem caused by the need for two semi-serial BTB queries in existing technologies and improving the single-cycle throughput of the branch predictor. Furthermore, by fully utilizing the inherent bandwidth of a single TAGE query, PB2 can contain conditional branches, overcoming the limitation of traditional multi-step branch predictors requiring PB2 to be branchless or contain only unconditional branches, thereby enhancing the applicability and practicality of multi-step prediction.

[0133] In some embodiments of this application, the prediction logic unit generates branch prediction results for the first prediction block and the second prediction block based on the branch direction prediction information and the address information in the branch information, which may include the following cases:

[0134] (1) When the branch instruction in the first prediction block that corresponds to the current program counter value satisfies the first condition, the end address of the first prediction block is determined to be the current program counter value plus the length of the first prediction block, only the branch prediction result of the first prediction block is generated, and the branch information of the second prediction block is determined to be invalid information; the first condition includes: the branch instruction is a conditional branch and the branch direction is non-jump.

[0135] (2) When the branch instruction in the first prediction block that corresponds to the current program counter value satisfies the second condition, the jump target address of the first prediction block is used to determine the starting address of the second prediction block; the second condition includes: the branch instruction is an unconditional branch, or the branch instruction is a conditional branch and the branch direction is a jump.

[0136] (3) When the branch instruction corresponding to the current program counter value in the first prediction block satisfies the second condition, when the branch instruction corresponding to the current program counter value in the second prediction block satisfies the second condition, the end address of the second prediction block is determined as the start address of the second prediction block plus the offset of the second prediction block, and the branch prediction result of the first prediction block and the branch prediction result of the second prediction block are generated.

[0137] (4) When the branch instruction corresponding to the current program counter value in the first prediction block satisfies the second condition, when the branch instruction corresponding to the current program counter value in the second prediction block satisfies the first condition, the end address of the second prediction block is determined as the start address of the second prediction block plus the length of the second prediction block, and the branch prediction result of the first prediction block and the branch prediction result of the second prediction block are generated.

[0138] The branch prediction result includes the start address, end address, jump identifier, and jump target address of the corresponding prediction block.

[0139] For example, with Figure 4 The embodiment shown illustrates obtaining Dir_A and Dir_B as an example. The prediction logic unit generates branch prediction results for the first prediction block and the second prediction block in parallel based on the branch direction prediction information and the address information in the branch information. This may include:

[0140] I. Determine the branch prediction results of the first prediction block PB1

[0141] The starting address of PB1: Start_PB1 = PC; the address of the internal branch instruction of PB1: BrAddr_PB1 = Start_PB1 + Offset_A, and the branch direction of PB1 is determined by Type_A and Dir_A:

[0142] (1) If (Type_A is an unconditional branch) or (Type_A is a conditional branch and Dir_A is Taken), then: the end address of PB1 is BrAddr_PB1 (that is, the branch instruction itself ends PB1); the jump target address of PB1 is Target_A; the next address of PB1 is Target_A, which is the starting address of PB2; the branch direction prediction result of PB1 is "jump".

[0143] (2) If (Type_A is a conditional branch and Dir_A is Not Taken), then: the end address of PB1 is Start_PB1 + prediction block size (length of PB1) or other boundary conditions defined by the processor; PB1 does not jump and is executed sequentially. Since there is no jump, the starting address of PB2 should be the next sequential address (i.e., the end address of PB1), not Target_A. In this case, the PB2 information in the extended entry is invalid; the prediction logic unit only outputs the branch direction prediction result of PB1, and does not output the branch direction prediction result of PB2, which is equivalent to degenerating into single-step prediction.

[0144] II. Determine the branch prediction results of the second prediction block PB1

[0145] Prerequisites: PB1 is predicted as a jump, and the starting address of PB2 is Start_PB2 = Target_A; the address of the branch instruction inside PB2 is: BrAddr_PB2 = Start_PB2 + Offset_B, and the branch direction of PB2 is determined based on Type_B and Dir_B.

[0146] (1) If (Type_B is an unconditional branch) or (Type_B is a conditional branch and Dir_B is a Taken), then: the end address of PB2 is BrAddr_PB2, the jump target address of PB2 is Target_B, and the prediction result of PB2 is "jump".

[0147] (2) If (Type_B is a conditional branch and Dir_B is Not Taken), then: the end address of PB2 is Start_PB2 + the size of the prediction block (the length of PB2); PB2 does not jump, and is executed sequentially to the boundary.

[0148] 3. Generate the final output and pass it to the downstream module.

[0149] Package the following information as the prediction result and pass it to the downstream module (e.g.) Figure 5 Instruction fetch unit of the processor front end):

[0150] (1) Branch prediction results of PB1: starting address, ending address, whether to jump, jump target address (if jump), internal branch information, etc.

[0151] (2) Branch prediction results of PB2: starting address, ending address, whether to jump, jump target address (if jumping), internal branch information, etc. (Here, we take the case where there are branch prediction results of PB2 as an example).

[0152] refer to Figure 1 and Figure 5 As shown, in some embodiments of this application, in addition to the branch information buffer 11, the branch predictor 12, and the prediction logic unit 13, the branch prediction processing architecture also includes an update logic unit 14. The update logic unit 14 can be used to update the extended entries of the branch information buffer 11 and the prediction entries of the branch predictor. For example, consider two consecutive instruction blocks (a first prediction block (PB1) and a second prediction block (PB2)), a branch information buffer BTB, and a branch predictor TAGE.

[0153] I. Improvements to BTB update method

[0154] The expanded BTB entry includes branch information for the second prediction block. Accordingly, the BTB update method should be improved to accommodate this change.

[0155] (1) BTB update during the prediction phase

[0156] In some embodiments of this application, during the prediction phase, for two adjacent prediction blocks (PB1 and PB2) that have completed instruction fetching, the branch information of PB2 can be updated to the BTB entry of PB1 according to certain constraints. Since the prediction result may be incorrect, the constraints on updating the entry here should be relatively strong to avoid updating erroneous information to the BTB and affecting the accuracy of subsequent predictions. Optionally, the constraint can be that the branch instruction of PB1 must be an unconditional direct jump. This means that the jump condition of the branch of PB1 is always true, and its jump target address is also unique. Optionally, the constraint can allow the branch of PB1 to be a conditional branch, but its prediction result must come from TAGE and the confidence of the corresponding TAGE entry must be saturated, and it should be a direct jump. Optionally, the constraint can require that the branch of PB2, if it is a conditional branch, also meets similar conditions.

[0157] (2) BTB update during the instruction fetch phase

[0158] In some embodiments of this application, during the instruction fetching stage, for two adjacent prediction blocks (PB1 and PB2) that have already completed instruction fetching, the branch information of PB2 can be updated in the BTB entry of PB1 according to certain constraints. Since the instruction fetching stage performs a basic judgment on the instruction type, the instruction type prediction error has been corrected by the time instruction fetching is completed, further reducing the probability of error. At this stage, the branch information of PB2 in the BTB entry can also be updated according to constraints similar to those in the prediction stage.

[0159] (3) BTB update during the resolution phase

[0160] In some embodiments of this application, during the resolve phase, since the branches have already been executed, there is no longer a risk of prediction errors. Updating BTB entries at this phase is the most reliable. However, during the resolve phase, because execution is out of order, some caching and sorting may be needed to ensure that two adjacent prediction blocks that meet the update conditions can exist simultaneously and participate in the update. Therefore, the BTB entries can also be updated with reference to the aforementioned constraints.

[0161] Furthermore, in some embodiments of this application, the actual execution results of the branches in the resolve phase can be compared with the prediction results to determine whether the BTB entries need to be updated. Since the TAGE update also occurs in this phase, this means that after the BTB entries are updated in previous phases, the corresponding update of TAGE has not yet begun, and therefore TAGE cannot participate in the prediction of the conditional branch of PB2 in the updated BTB entries. The purpose of updating the BTB entries in advance in the aforementioned phase is to provide BTB entries that can predict PB1 and PB2 as quickly as possible, given a relatively high level of confidence.

[0162] In some embodiments of this application, regardless of the stage described above, there are some basic update constraints that can significantly increase the accuracy of BTB entries:

[0163] (1) The branch instruction in the first prediction block cannot be an indirect branch instruction. This is because the jump target address of an indirect branch instruction is not unique, and therefore the information in the second prediction block is also unreliable. Using the information from the first prediction to predict the next one, the address of the second prediction block is likely to be incorrect.

[0164] (2) The second prediction block contains no more than one conditional branch instruction. This is because if there is more than one branch, then the branch before the last branch of the prediction block must be a conditional branch, and the result in the current prediction is "no jump". If such a prediction block is updated in the BTB entry, the conditional branch will be predicted as "jump" in subsequent execution, which will cause the information of the second prediction block in the BTB entry to be incorrect.

[0165] (3) The branch instructions in the second prediction block are not indirect jump instructions outside the return class. This is because indirect jumps outside of return generally require querying ITTAGE (a predictor similar to TAGE structure, but whose function is not to predict whether the conditional branch will jump, but to predict the target address of the indirect branch). The query process is very time-consuming, making the advantage of two-step prediction not obvious.

[0166] II. Improvements to TAGE Update Method

[0167] Combination Figure 5 As shown, after the branch instruction is actually executed (i.e., the resolve phase), the update logic unit 14 can obtain the execution result from the resolve / retire unit at the back end of the processor and execute the TAGE entry update according to certain rules.

[0168] In some embodiments of this application, a single TAGE query uses the GHR value of the first prediction block, and the retrieved TAGE entry contains branches from both the first and second prediction blocks. Therefore, when updating the branches of the first and second prediction blocks in the TAGE during the resolve phase, it is important to ensure that the GHR value of the first prediction block is used consistently to guarantee consistency with subsequent queries.

[0169] In practice, for any conditional branch, its corresponding prediction block can be either the first or the second prediction block in a two-step prediction process. For the former, the branch updates TAGE using its own GHR value. For the latter, its update requires using the GHR value of the preceding prediction block.

[0170] The above situation also means that any conditional branch requires updating TAGE twice. This doubles the number of TAGE update requests, increasing the likelihood of conflicts with TAGE query requests. It may also prevent information from subsequent, truly important conditional branches from being updated in TAGE in a timely manner, thus reducing TAGE accuracy and negatively impacting performance. In some embodiments of this application, two updates are not always necessary.

[0171] First, TAGE updates can refer to the update status of BTB entries. This is because TAGE updates are only truly necessary when the branch information of the second prediction block exists in the BTB (i.e., the TAGE entries corresponding to the branch instructions in the first prediction block are updated first, and the TAGE entries corresponding to the branch instructions in the second prediction block are updated only when the first prediction block stores extended entries of the branch instructions).

[0172] Secondly, when there are many TAGE updates and the queue waiting for updates is nearing saturation, TAGE entries corresponding to branch instructions within the second prediction block can be prioritized for update. That is, when available TAGE entries are scarce, priority is given to updating TAGE entries corresponding to branch instructions within the first prediction block. In other words, when all available TAGE entries are used up, TAGE entries corresponding to branch instructions within the second prediction block are prioritized as replacement candidates. In more complex replacement algorithms, other information can be considered. For example, when the branch predictor has no free TAGE entries, TAGE entries corresponding to branch instructions in the second prediction block that meet specified conditions are replaced; these specified conditions are the minimum useful value and / or the minimum confidence value. Optionally, in more complex and optimized algorithms, more information can be considered, along with the corresponding entries in the BTB, to quantitatively calculate the replacement priority of each entry and select the entry that should be replaced most. Of course, to identify entries in the second prediction block during replacement, the TAGE entries need to be expanded by adding one bit of information to indicate that they correspond to a branch in the second prediction block.

[0173] This application also provides a chip that includes the branch prediction processing architecture described above. For example, in some embodiments of this application, the chip may be a central processing unit.

[0174] This application also provides a branch prediction method, which can be applied to the aforementioned chip side, see reference. Figure 6 As shown, in some embodiments of this application, the branch prediction method may include the following steps:

[0175] Step 601: Obtain branch information from the extended entries of the branch information buffer; the extended entries include branch information of the first prediction block and branch information of at least one second prediction block related to the execution order of the first prediction block.

[0176] Step 602: The branch predictor performs a single branch prediction operation based on the acquired branch information to generate branch direction prediction information in parallel for the branch instructions in the first prediction block and the branch instructions in the second prediction block.

[0177] Step 603: The prediction logic unit generates the branch prediction results of the first prediction block and the second prediction block based on the branch direction prediction information and the address information in the branch information.

[0178] In some embodiments of the branch prediction method of this application, the number of the second prediction blocks is one, and the branch predictor is a direction predictor based on global history; the direction predictor based on global history includes a labeled geometric history length branch predictor TAGE.

[0179] In some embodiments of the branch prediction method of this application, the step of performing a single branch prediction operation based on the acquired branch information to generate branch direction prediction information in parallel for the branch instructions in the first prediction block and the branch instructions in the second prediction block includes:

[0180] In a single branch prediction operation based on the acquired branch information, the context information used to distinguish the prediction block to which the branch instruction belongs is combined with the program counter value and global history information to form an index, and the TAGE entries of the corresponding branch instructions in the first prediction block and the second prediction block are queried from multiple prediction tables of the TAGE according to the index.

[0181] In some embodiments of the branch prediction method of this application, generating branch prediction results for the first prediction block and the second prediction block based on the branch direction prediction information and the address information in the branch information includes:

[0182] When the branch instruction in the first prediction block that corresponds to the current program counter value satisfies the first condition, the end address of the first prediction block is determined to be the current program counter value plus the length of the first prediction block, only the branch prediction result of the first prediction block is generated, and the branch information of the second prediction block is determined to be invalid information; the first condition includes: the branch instruction is a conditional branch and the branch direction is non-jump;

[0183] When the branch instruction in the first prediction block that corresponds to the current program counter value satisfies the second condition, the jump target address of the first prediction block is used to determine the starting address of the second prediction block; the second condition includes: the branch instruction is an unconditional branch, or the branch instruction is a conditional branch and the branch direction is a jump;

[0184] If the branch instruction corresponding to the current program counter value in the first prediction block satisfies the second condition, and the branch instruction corresponding to the current program counter value in the second prediction block satisfies the second condition, the end address of the second prediction block is determined as the start address of the second prediction block plus the offset of the second prediction block, and the branch prediction result of the first prediction block and the branch prediction result of the second prediction block are generated.

[0185] If the branch instruction corresponding to the current program counter value in the first prediction block satisfies the second condition, and the branch instruction corresponding to the current program counter value in the second prediction block satisfies the first condition, the end address of the second prediction block is determined as the start address of the second prediction block plus the length of the second prediction block, and the branch prediction result of the first prediction block and the branch prediction result of the second prediction block are generated.

[0186] The branch prediction result includes the start address, end address, jump identifier, and jump target address of the corresponding prediction block.

[0187] In some embodiments of the branch prediction method of this application, the branch prediction method further includes:

[0188] The update logic unit updates the extended entry of the branch information buffer and the TAGE entry of the TAGE.

[0189] In some embodiments of the branch prediction method of this application, updating the expanded entries of the branch information buffer includes:

[0190] For the first and second prediction blocks that have completed fetching or executing branch instructions, when the branch instruction meets a predetermined condition, the branch information of the branch instruction in the second prediction block is updated to the corresponding extension entry of the first prediction block.

[0191] In some embodiments of the branch prediction method of this application, the predetermined conditions include:

[0192] The branch instruction in the first prediction block is not an indirect branch instruction;

[0193] The second prediction block contains no more than one conditional branch instruction; and

[0194] The branch instruction in the second prediction block is not an indirect jump instruction outside the return class.

[0195] In the branch prediction method of some embodiments of this application, updating the TAGE entry of the TAGE includes:

[0196] First, update the TAGE entry corresponding to the branch instruction in the first prediction block; when the first prediction block stores an extended entry of the branch instruction, update the TAGE entry corresponding to the branch instruction in the second prediction block.

[0197] In some embodiments of the branch prediction method of this application, updating the TAGE entry of the TAGE further includes:

[0198] When there are no free TAGE entries in the branch predictor, replace the TAGE entry in the second prediction block that meets the specified conditions corresponding to the branch instruction; the specified conditions are the minimum useful value and / or the minimum saturation counter value.

[0199] Although the process described above includes multiple operations that occur in a specific order, it should be clearly understood that these processes may include more or fewer operations that can be executed sequentially or in parallel (e.g., using parallel processors or a multithreaded environment).

[0200] Embodiments of this application also provide a computer device. For example... Figure 7 As shown, in some embodiments of this application, the computer device 702 may include one or more processors 704, such as one or more central processing units (CPUs) or graphics processing units (GPUs), each of which may implement one or more hardware threads. The computer device 702 may also include any memory 706 for storing any kind of information such as code, settings, data, etc. In one specific embodiment, a computer program is stored on the memory 706 and can run on the processor 704. When the computer program is run by the processor 704, it can execute instructions of the branch prediction method described in any of the above embodiments. Non-limitingly, for example, the memory 706 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Further, any memory can provide volatile or non-volatile retention of information. Further, any memory may represent a fixed or removable component of the computer device 702. In one case, when the processor 704 executes associated instructions stored in any memory or combination of memories, the computer device 702 can perform any operation of the associated instructions. The computer device 702 also includes one or more drive mechanisms 708 for interacting with any memory, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0201] Computer device 702 may also include an input / output interface 710 (I / O) for receiving various inputs (via input device 712) and providing various outputs (via output device 714). A specific output mechanism may include a presentation device 716 and an associated graphical user interface 718 (GUI). In other embodiments, the input / output interface 710 (I / O), input device 712, and output device 714 may be omitted, and the device may function solely as a computer device within a network. Computer device 702 may also include one or more network interfaces 720 for exchanging data with other devices via one or more communication links 722. One or more communication buses 724 couple the components described above together.

[0202] Communication link 722 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 722 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0203] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), computer-readable storage media, and computer program products according to some embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processor to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processor, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0204] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processor to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0205] These computer program instructions may also be loaded onto a computer or other programmable data processor, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable device for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0206] In a typical configuration, a computer device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0207] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0208] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by computer equipment. As defined in this application, computer-readable media does not include transient media, such as modulated data signals and carrier waves.

[0209] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, embodiments of this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0210] The embodiments of this application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. The embodiments of this application can also be practiced in distributed computing environments where tasks are performed by remote processors connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0211] It should also be understood that, in the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0212] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the device embodiments, so the description is relatively simple; relevant parts can be referred to the description of the device embodiments.

[0213] In the description of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this application, as well as the features of different embodiments or examples.

[0214] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A branch prediction processing architecture, characterized in that, include: A branch information buffer is used to store multiple entries, at least one of which is an extension entry. The extension entry contains branch information of a first prediction block and branch information of at least one second prediction block related to the execution order of the first prediction block. A branch predictor is used to generate branch direction prediction information in parallel for branch instructions in the first prediction block and branch instructions in the second prediction block, based on branch information obtained from the extended entry, in a single branch prediction operation. The prediction logic unit is used to generate branch prediction results for the first prediction block and the second prediction block based on the branch direction prediction information and the address information in the branch information.

2. The branch prediction processing architecture as described in claim 1, characterized in that, The extended entry includes: The location, type, and jump target address of the branch instruction within the first prediction block; and The location, type, and jump target address of the branch instruction within the second prediction block.

3. The branch prediction processing architecture as described in claim 1, characterized in that, The branch information buffer includes a branch target cache.

4. The branch prediction processing architecture as described in claim 1, characterized in that, The branch predictor includes a branch predictor based on global history.

5. The branch prediction processing architecture as described in claim 4, characterized in that, The second prediction block has one unit; the global history-based branch predictor is a labeled geometric history length branch predictor (TAGE). In the single branch prediction operation, based on the branch information obtained from the extended entry, branch direction prediction information is generated in parallel for the branch instructions in the first prediction block and the branch instructions in the second prediction block, including: In a single query operation, the context information used to distinguish the prediction block to which the branch instruction belongs is combined with the program counter value and global history information to form an index, and the TAGE entries of the corresponding branch instructions in the first prediction block and the second prediction block are queried from multiple prediction tables of the TAGE according to the index.

6. The branch prediction processing architecture as described in claim 5, characterized in that, The context information is a prediction block identifier, and the prediction block identifier, the program counter value, and the global history information form the input parameters of the hash calculation function for the TAGE entry label of the TAGE.

7. The branch prediction processing architecture as described in claim 6, characterized in that, The width of the prediction block identifier is one bit.

8. The branch prediction processing architecture as described in claim 5, characterized in that, The context information is the identifier field contained in the TAGE entry of the TAGE.

9. The branch prediction processing architecture as described in claim 5, characterized in that, The step of generating branch prediction results for the first prediction block and the second prediction block based on the branch direction prediction information and the address information in the branch information includes: When the branch instruction in the first prediction block that corresponds to the current program counter value satisfies the first condition, the end address of the first prediction block is determined to be the current program counter value plus the length of the first prediction block, only the branch prediction result of the first prediction block is generated, and the branch information of the second prediction block is determined to be invalid information; the first condition includes: the branch instruction is a conditional branch and the branch direction is non-jump; When the branch instruction in the first prediction block that corresponds to the current program counter value satisfies the second condition, the jump target address of the first prediction block is used to determine the starting address of the second prediction block; the second condition includes: the branch instruction is an unconditional branch, or the branch instruction is a conditional branch and the branch direction is a jump; If the branch instruction corresponding to the current program counter value in the first prediction block satisfies the second condition, and the branch instruction corresponding to the current program counter value in the second prediction block satisfies the second condition, the end address of the second prediction block is determined as the start address of the second prediction block plus the offset of the second prediction block, and the branch prediction result of the first prediction block and the branch prediction result of the second prediction block are generated. If the branch instruction corresponding to the current program counter value in the first prediction block satisfies the second condition, and the branch instruction corresponding to the current program counter value in the second prediction block satisfies the first condition, the end address of the second prediction block is determined as the start address of the second prediction block plus the length of the second prediction block, and the branch prediction result of the first prediction block and the branch prediction result of the second prediction block are generated. The branch prediction result includes the start address, end address, jump identifier, and jump target address of the corresponding prediction block.

10. The branch prediction processing architecture as described in claim 5, characterized in that, The branch prediction processing architecture also includes: An update logic unit is used to update the extended entries of the branch information buffer and the TAGE entries of the TAGE.

11. The branch prediction processing architecture as described in claim 10, characterized in that, The update of the extended entries in the branch information buffer includes: For the first and second prediction blocks that have completed fetching or executing branch instructions, when the branch instruction meets a predetermined condition, the branch information of the branch instruction in the second prediction block is updated to the corresponding extension entry of the first prediction block.

12. The branch prediction processing architecture as described in claim 11, characterized in that, The predetermined conditions include: The branch instruction in the first prediction block is not an indirect branch instruction; The second prediction block contains no more than one conditional branch instruction; and The branch instruction in the second prediction block is not an indirect jump instruction outside the return class.

13. The branch prediction processing architecture as described in claim 10, characterized in that, The updating of the TAGE entry for the TAGE includes: First, update the TAGE entry corresponding to the branch instruction in the first prediction block; when the first prediction block stores an extended entry of the branch instruction, update the TAGE entry corresponding to the branch instruction in the second prediction block.

14. The branch prediction processing architecture as described in claim 13, characterized in that, The updating of the TAGE entry of the TAGE also includes: When there are no free TAGE entries in the branch predictor, replace the TAGE entry in the second prediction block that meets the specified conditions corresponding to the branch instruction; the specified conditions are the minimum useful value and / or the minimum saturation counter value.

15. A branch prediction method, characterized in that, include: Retrieve branch information from the extended entries in the branch information buffer; The extended entry includes branch information of the first prediction block and branch information of at least one second prediction block related to the execution order of the first prediction block. The branch predictor performs a single branch prediction operation based on the acquired branch information, so as to generate branch direction prediction information in parallel for the branch instructions in the first prediction block and the branch instructions in the second prediction block. The prediction logic unit generates branch prediction results for the first prediction block and the second prediction block based on the branch direction prediction information and the address information in the branch information.

16. The branch prediction method as described in claim 15, characterized in that, The second prediction block consists of one block, and the branch predictor is a global history-based direction predictor; the global history-based direction predictor includes a labeled geometric history length branch predictor (TAGE).

17. The branch prediction method as described in claim 16, characterized in that, The step of performing a single branch prediction operation based on the acquired branch information to generate branch direction prediction information in parallel for the branch instructions in the first prediction block and the branch instructions in the second prediction block includes: In a single branch prediction operation based on the acquired branch information, the context information used to distinguish the prediction block to which the branch instruction belongs is combined with the program counter value and global history information to form an index, and the TAGE entries of the corresponding branch instructions in the first prediction block and the second prediction block are queried from multiple prediction tables of the TAGE according to the index.

18. The branch prediction method as described in claim 16, characterized in that, The step of generating branch prediction results for the first prediction block and the second prediction block based on the branch direction prediction information and the address information in the branch information includes: When the branch instruction in the first prediction block that corresponds to the current program counter value satisfies the first condition, the end address of the first prediction block is determined to be the current program counter value plus the length of the first prediction block, only the branch prediction result of the first prediction block is generated, and the branch information of the second prediction block is determined to be invalid information; the first condition includes: the branch instruction is a conditional branch and the branch direction is non-jump; When the branch instruction in the first prediction block that corresponds to the current program counter value satisfies the second condition, the jump target address of the first prediction block is used to determine the starting address of the second prediction block; the second condition includes: the branch instruction is an unconditional branch, or the branch instruction is a conditional branch and the branch direction is a jump; If the branch instruction corresponding to the current program counter value in the first prediction block satisfies the second condition, and the branch instruction corresponding to the current program counter value in the second prediction block satisfies the second condition, the end address of the second prediction block is determined as the start address of the second prediction block plus the offset of the second prediction block, and the branch prediction result of the first prediction block and the branch prediction result of the second prediction block are generated. If the branch instruction corresponding to the current program counter value in the first prediction block satisfies the second condition, and the branch instruction corresponding to the current program counter value in the second prediction block satisfies the first condition, the end address of the second prediction block is determined as the start address of the second prediction block plus the length of the second prediction block, and the branch prediction result of the first prediction block and the branch prediction result of the second prediction block are generated. The branch prediction result includes the start address, end address, jump identifier, and jump target address of the corresponding prediction block.

19. The branch prediction method as described in claim 16, characterized in that, The branch prediction method further includes: The update logic unit updates the extended entry of the branch information buffer and the TAGE entry of the TAGE.

20. The branch prediction method as described in claim 19, characterized in that, The update of the extended entries in the branch information buffer includes: For the first and second prediction blocks that have completed fetching or executing branch instructions, when the branch instruction meets a predetermined condition, the branch information of the branch instruction in the second prediction block is updated to the corresponding extension entry of the first prediction block.

21. The branch prediction method as described in claim 20, characterized in that, The predetermined conditions include: The branch instruction in the first prediction block is not an indirect branch instruction; The second prediction block contains no more than one conditional branch instruction; and The branch instruction in the second prediction block is not an indirect jump instruction outside the return class.

22. The branch prediction method as described in claim 19, characterized in that, The updating of the TAGE entry for the TAGE includes: First, update the TAGE entry corresponding to the branch instruction in the first prediction block; when the first prediction block stores an extended entry of the branch instruction, update the TAGE entry corresponding to the branch instruction in the second prediction block.

23. The branch prediction method as described in claim 22, characterized in that, The updating of the TAGE entry of the TAGE also includes: When there are no free TAGE entries in the branch predictor, replace the TAGE entry in the second prediction block that meets the specified conditions corresponding to the branch instruction; the specified conditions are the minimum useful value and / or the minimum saturation counter value.

24. A chip, characterized in that, The chip comprises the branch prediction processing architecture as described in any one of claims 1-14.

25. A computer device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, When the computer program is run by the processor, it executes the instructions of the method according to any one of claims 15-23.

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