Method, device and storage medium for re-executing access instruction

Abstract

The application provides a memory access instruction re-execution method and device, equipment and a storage medium. The method applied to a processor comprises the following steps: determining a re-execution event of a memory access instruction; determining a target feedback port from at least one preset feedback port based on the re-execution event or a target pipeline level where the memory access instruction is located; and sending a retransmission request to a reservation station through the target feedback port, so that the reservation station retransmits the memory access instruction based on the retransmission request. Through the technical solution of the application, the efficiency of the memory access instruction re-execution can be improved, and the processor execution efficiency can be further improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, device and storage medium for re-executing memory access instructions. Background Technology

[0002] With the development of computer processor technology, the performance of the processor's memory access system has an increasingly significant impact on processor performance. The increase in processor memory access speed is not keeping pace with the increase in processor processing speed, severely limiting further improvements in processor performance. Therefore, reducing congestion events in the memory access pipeline and resuming execution of canceled memory access operations as soon as the cause of cancellation is resolved is crucial to minimizing pipeline congestion. Summary of the Invention

[0003] This application aims to at least partially address one of the technical problems in the related art.

[0004] In a first aspect, this application proposes a method for re-executing a memory access instruction, the method comprising: determining a memory access instruction re-executing event; determining a target feedback port from at least one preset feedback port based on the re-executing event or the target pipeline stage where the memory access instruction is located; and sending a retransmission request to a retention station through the target feedback port, so that the retention station retransmits the memory access instruction based on the retransmission request.

[0005] In one implementation, each feedback port corresponds to at least one pipeline stage, and different feedback ports correspond to different pipeline stages. Based on the target pipeline stage where the memory access instruction is located, a target feedback port is determined from multiple preset feedback ports, including: using the feedback port corresponding to the target pipeline stage as the target feedback port.

[0006] In one optional implementation, the memory access instruction is a fetch instruction, the fetch pipeline corresponding to the fetch instruction includes four pipeline stages, the feedback port includes a fast feedback port and a slow feedback port, the fast feedback port is set in pipeline stage 1 of the fetch pipeline, the slow feedback port is set in pipeline stage 3 of the fetch pipeline, and the step of using the feedback port corresponding to the target pipeline stage as the target feedback port includes: determining that the target pipeline stage is pipeline stage 0 or pipeline stage 1 of the fetch pipeline, and using the fast feedback port as the target feedback port; or, determining that the target pipeline stage is pipeline stage 2 or pipeline stage 3 of the fetch pipeline, and using the slow feedback port as the target feedback port.

[0007] In one optional implementation, the memory access instruction is a data storage instruction, the data storage pipeline corresponding to the data storage instruction includes four pipeline stages, the feedback port includes a data storage retransmission feedback port, the data storage retransmission feedback port is set in pipeline stage 1, and the step of determining the target feedback port from multiple preset feedback ports based on the target pipeline stage where the memory access instruction is located includes: determining the target pipeline stage as pipeline stage 0 or pipeline stage 1 of the data storage pipeline, and using the data storage retransmission feedback port as the target feedback port.

[0008] In one implementation, the re-execution event includes at least one of the following: translation back buffer failure; data cache access conflict; data cache memory access failure queue full; when the data fetch instruction corresponding to the data storage instruction is passed to the data fetch instruction, an address match is found but the data is not ready.

[0009] In one implementation, the step of having the reservation station resend the memory access instruction based on the retransmission request includes at least one of the following: having the reservation station resend the memory access instruction after a preset first time interval when the re-execution event is the failure of the translation backstop; having the reservation station immediately resend the memory access instruction when the memory access instruction is the fetch instruction and the re-execution event is a data cache access conflict; having the reservation station resend the memory access instruction when it is determined that there is an empty entry in the data cache access failure queue when the re-execution event is a full data cache access failure queue; having the reservation station immediately resend the memory access instruction when the re-execution event is a full data cache access failure queue; and having the reservation station, when the data access instruction corresponding to the fetch instruction is passed to the fetch instruction during the re-execution event and a matching address is found but the data is not ready, resend the memory access instruction after determining the corresponding data access data based on the found data access queue number. In one optional implementation, the feedback port includes at least one of a fast feedback port and a slow feedback port. The fast feedback port is located at pipeline stage 1 of the data fetch pipeline, and the slow feedback port is located at pipeline stage 3 of the data fetch pipeline. Based on the re-execution event, a target feedback port is determined from at least one preset feedback port, including at least one of the following: in response to the re-execution event being a translation backstop failure, the fast feedback port is designated as the target feedback port; in response to the memory access instruction being a data fetch instruction and the re-execution event being a data cache access conflict, the fast feedback port is designated as the target feedback port; in response to the memory access instruction being a data fetch instruction and the re-execution event being a data cache access failure queue allocation failure, the slow feedback port is designated as the target feedback port; in response to the memory access instruction being a data fetch instruction and the re-execution event being the data for the data fetch instruction not being ready, the slow feedback port is designated as the target feedback port.

[0010] In one implementation, the step of having the reservation station resend the memory access instruction based on the retransmission request includes at least one of the following: immediately retransmitting the memory access instruction if it is determined that re-execution of the memory access instruction will not trigger the re-execution event again; immediately retransmitting the memory access instruction if it is determined that the event causing the re-execution event can be resolved within a preset time period; or retransmitting the memory access instruction after the second time interval if it is determined that the event causing the re-execution event is resolved within a preset second time interval. In one implementation, the retransmission request includes at least one of the following information: a reservation station index field; a type field; and a memory queue number field.

[0011] Secondly, this application proposes a method for re-executing a memory access instruction, the method being applied to a reserved station, the method comprising: receiving a retransmission request; wherein the retransmission request is a request sent by the processor to the reserved station based on the processor determining that a memory access instruction re-execution event has occurred, determining a target feedback port from at least one preset feedback port based on the re-execution event or the target pipeline stage where the memory access instruction is located, and based on the target feedback port; and retransmitting the memory access instruction based on the retransmission request.

[0012] In one implementation, retransmitting the memory access instruction based on the retransmission request includes at least one of the following: retransmitting the memory access instruction after a preset first time interval when the re-execution event is the failure of the translation backstop; immediately retransmitting the memory access instruction when the memory access instruction is the fetch instruction and the re-execution event is a data cache access conflict; retransmitting the memory access instruction when it is determined that there is an empty entry in the data cache memory access failure queue when the re-execution event is a full data cache memory access failure queue; immediately retransmitting the memory access instruction when the re-execution event is a full data cache memory access failure queue; and retransmitting the memory access instruction after determining the corresponding stored data based on the retrieved stored data queue number when the re-execution event is a data storage instruction corresponding to the fetch instruction being passed to the fetch instruction.

[0013] In one implementation, retransmitting the memory access instruction based on the retransmission request includes at least one of the following: immediately retransmitting the memory access instruction if it is determined that the re-execution event will not be triggered again when the memory access instruction is executed again; immediately retransmitting the memory access instruction if it is determined that the event causing the re-execution can be resolved within a preset time period; and retransmitting the memory access instruction after the second time period if it is determined that the event causing the re-execution is resolved within a preset second time interval.

[0014] Thirdly, this application proposes a re-execution apparatus for memory access instructions, the apparatus comprising: a first processing module, configured to determine a re-execution event of a memory access instruction, and, based on the re-execution event or the target pipeline stage where the memory access instruction is located, determine a target feedback port from at least one preset feedback port; and a second processing module, configured to send a retransmission request to a retention station through the target feedback port, so that the retention station retransmits the memory access instruction based on the retransmission request.

[0015] In one implementation, each feedback port corresponds to at least one pipeline stage, and different feedback ports correspond to different pipeline stages. Based on the target pipeline stage where the memory access instruction is located, a target feedback port is determined from multiple preset feedback ports, including: using the feedback port corresponding to the target pipeline stage as the target feedback port.

[0016] In one optional implementation, the memory access instruction is a data fetch instruction, the data fetch pipeline corresponding to the data fetch instruction includes four pipeline stages, the feedback port includes a fast feedback port and a slow feedback port, the fast feedback port is set in pipeline stage 1 of the data fetch pipeline, and the slow feedback port is set in pipeline stage 3 of the data fetch pipeline. The first processing module can be used to: determine that the target pipeline stage is pipeline stage 0 or pipeline stage 1 of the data fetch pipeline, and use the fast feedback port as the target feedback port; or, determine that the target pipeline stage is pipeline stage 2 or pipeline stage 3 of the data fetch pipeline, and use the slow feedback port as the target feedback port.

[0017] In one optional implementation, the memory access instruction is a data storage instruction, the data storage pipeline corresponding to the data storage instruction includes four pipeline stages, the feedback port includes a data storage retransmission feedback port, the data storage retransmission feedback port is set in pipeline stage 1, and the first processing module can be used to: determine that the target pipeline stage is pipeline stage 0 or pipeline stage 1 of the data storage pipeline, and use the data storage retransmission feedback port as the target feedback port.

[0018] In one implementation, the re-execution event includes at least one of the following: translation back buffer failure; data cache access conflict; data cache memory access failure queue full; when the data fetch instruction corresponding to the data storage instruction is passed to the data fetch instruction, an address match is found but the data is not ready.

[0019] In one alternative implementation, the re-execution event is a data cache access conflict, and the first processing module can be used to: determine that a data cache access conflict has occurred in response to a data store operation and a data fetch operation acting on the same cache line.

[0020] In one optional implementation, the feedback port includes at least one of a fast feedback port and a slow feedback port, and the first processing module can be configured to: in response to the re-execution event being a failure of the translation backstop buffer, use the fast feedback port as the target feedback port; in response to the memory access instruction being a fetch instruction and the re-execution event being a data cache access conflict, use the fast feedback port as the target feedback port; in response to the memory access instruction being a fetch instruction and the re-execution event being a failure to allocate the data cache memory access invalidation queue, use the slow feedback port as the target feedback port; in response to the memory access instruction being a fetch instruction and the re-execution event being that the data for the memory access instruction is not ready, use the slow feedback port as the target feedback port.

[0021] In one optional implementation, the second processing module is configured to perform at least one of the following: when the re-execution event is the failure of the translation backstop, the reserved station resends the memory access instruction after a preset first time interval; when the memory access instruction is the fetch instruction and the re-execution event is a data cache access conflict, the reserved station immediately resends the memory access instruction; when the re-execution event is a full data cache access failure queue, the reserved station resends the memory access instruction when it is determined that there is an empty entry in the data cache access failure queue; when the re-execution event is a full data cache access failure queue, the reserved station immediately resends the memory access instruction; when the re-execution event is a full data cache access failure queue, the reserved station resends the memory access instruction after determining the corresponding stored data based on the found stored data queue number, if the stored data instruction corresponding to the fetch instruction is passed to the fetch instruction during the re-execution event and a matching address is found but the data is not ready.

[0022] In one implementation, the second processing module is configured to perform at least one of the following: immediately resend the memory access instruction if the re-execution event will not be triggered again when the memory access instruction is executed again; immediately resend the memory access instruction if the resend station determines that the event causing the re-execution can be resolved within a preset time period; and resend the memory access instruction after the second time interval if the resend station determines that the event causing the re-execution is resolved within a preset second time interval.

[0023] In one implementation, the retransmission request includes at least one of the following: a reservation station index field; a type field; and a storage queue number field.

[0024] Fourthly, this application proposes a re-execution apparatus for memory access instructions, the apparatus being applied to a retention station, the apparatus comprising: a receiving module for receiving a retransmission request; wherein the retransmission request is a request sent to the retention station based on the processor determining that a re-execution event of a memory access instruction has occurred, determining a target feedback port from at least one preset feedback port based on the re-execution event or the target pipeline stage where the memory access instruction is located; and a processing module for retransmitting the memory access instruction based on the retransmission request.

[0025] In one implementation, the processing module is configured to perform at least one of the following: resend the memory access instruction after a preset first time interval if the re-execution event is a failure of the translation backing buffer; immediately resend the memory access instruction if the memory access instruction is the fetch instruction and the re-execution event is a data cache access conflict; resend the memory access instruction when it is determined that there is an empty entry in the data cache memory access failure queue if the re-execution event is a full data cache memory access failure queue; immediately resend the memory access instruction if the re-execution event is a full data cache memory access failure queue; and resend the memory access instruction after determining the corresponding stored data based on the retrieved stored data queue number when the re-execution event is a data storage instruction corresponding to the fetch instruction being passed to the fetch instruction.

[0026] In one implementation, the processing module is configured to perform at least one of the following: if it is determined that the re-execution event will not be triggered again when the memory access instruction is executed again, immediately resend the memory access instruction; if it is determined that the re-execution event can be resolved within a preset time period, immediately resend the memory access instruction; if it is determined that the re-execution event is resolved within a preset second time interval, resend the memory access instruction after the second time interval.

[0027] Fifthly, this application provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a memory access instruction re-execution method as described in the first aspect.

[0028] In a sixth aspect, this application provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a memory access instruction re-execution method as described in the second aspect.

[0029] In a seventh aspect, this application provides a storage medium storing instructions that, when executed on an electronic device, cause the electronic device to perform the method described in the first aspect.

[0030] Eighthly, this application provides a storage medium storing instructions that, when executed on an electronic device, cause the electronic device to perform the method described in the second aspect.

[0031] In a ninth aspect, this application proposes a program product comprising at least one of a program and instructions, wherein when the program and instructions are executed by an electronic device, they implement the steps of the method described in the first aspect.

[0032] In a tenth aspect, this application proposes a program product comprising at least one of a program and instructions, wherein when the program and instructions are executed by an electronic device, they implement the steps of the method described in the second aspect.

[0033] The memory access instruction re-execution method, apparatus, device, and storage medium provided in this application can, upon determining that a memory access instruction re-execution event has occurred, determine a target feedback port from at least one preset feedback port based on the re-execution event or the target pipeline stage where the memory access instruction is located, and send a retransmission request to the reservation station based on the target feedback port, so that the reservation station retransmits the memory access instruction. This can improve the efficiency of memory access instruction re-execution, thereby further improving processor execution efficiency.

[0034] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0035] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0036] Figure 1 This is a flowchart illustrating a method for re-executing a memory access instruction provided in an embodiment of this application;

[0037] Figure 2 This is a flowchart illustrating another method for re-executing memory access instructions provided in an embodiment of this application;

[0038] Figure 3 This is a flowchart illustrating another method for re-executing memory access instructions provided in an embodiment of this application;

[0039] Figure 4 This is a flowchart illustrating another method for re-executing memory access instructions provided in an embodiment of this application;

[0040] Figure 5 This is a flowchart illustrating another method for re-executing memory access instructions provided in an embodiment of this application;

[0041] Figure 6 This is a schematic diagram of the architecture of a memory access system provided in an embodiment of this application;

[0042] Figure 7 This is a schematic diagram of the structure of a memory access instruction re-execution device provided in an embodiment of this application;

[0043] Figure 8 This is a schematic diagram of another memory access instruction re-execution device provided in an embodiment of this application;

[0044] Figure 9 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0045] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0046] The following description, with reference to the accompanying drawings, describes a method and apparatus for re-executing memory access instructions according to embodiments of this application.

[0047] Figure 1 This is a flowchart illustrating a method for re-executing memory access instructions provided in an embodiment of this application. This method can be applied to processors. Figure 1 As shown, the method may include, but is not limited to, the following steps:

[0048] S101: Determine the re-execution event of the memory access instruction, and determine the target feedback port from at least one preset feedback port based on the target pipeline stage where the re-execution event or the memory access instruction is located.

[0049] In the embodiments of this application, the memory access instructions include at least one of the following: a store instruction and a fetch instruction.

[0050] As an example, a re-execution event of a memory access instruction is identified, and a target feedback port is determined from at least one preset feedback port based on the specific type of the re-execution event.

[0051] For example, at least one feedback port can be pre-configured, and a corresponding re-execution event can be configured for each feedback port, so that the feedback port corresponding to the re-execution event of the memory access instruction is used as the target feedback port.

[0052] As another example, to determine the occurrence of a re-execution event of a memory access instruction, a target feedback port is determined from at least one preset feedback port based on the target pipeline stage where the memory access instruction is located.

[0053] For example, at least one feedback port can be pre-configured, and a corresponding pipeline stage can be configured for each feedback port, so that the target feedback port can be determined based on the pipeline stage where the memory access instruction is located when a re-execution event of the memory access instruction occurs.

[0054] In the embodiments of this application, the memory access instruction may include at least one of the following: a store instruction and a fetch instruction.

[0055] In the embodiments of this application, the aforementioned re-execution event includes at least one of the following: translation back buffer failure; data cache access conflict; data cache memory access failure queue full; when the data fetch instruction corresponding to the data storage instruction is passed to the data fetch instruction, it is found that the address matches but the data is not ready.

[0056] In one alternative implementation, the aforementioned re-execution event is a data cache access conflict. Determining that a memory access instruction re-execution event has occurred includes: determining that a data cache access conflict has occurred in response to a store operation and a fetch operation operating on the same cache line.

[0057] It's important to note that data cache access conflicts include bank conflicts between N fetch pipelines, as well as conflicts between fetch instruction pipeline accesses and store operations writing to cache lines. A store operation refers to a committed store instruction writing data from the committed store buffer into the data cache (DCache). For conflicts between fetch and store instructions, to optimize timing, only cache line checks are performed; a conflict occurs if both fetch and store operations operate on the same cache line.

[0058] S102: Send a retransmission request to the reserved station through the target feedback port so that the reserved station retransmits the memory access command based on the retransmission request.

[0059] It should be noted that the reservation station is a temporary storage and scheduling unit designed for memory access instructions. Its function is to temporarily store unread memory access instructions and their source operands, addresses, data and other dependency information. After the memory access instruction is issued from the reservation station, it will wait in the reservation station for a preset time. When the memory access instruction leaves the pipeline, it will send feedback to the reservation station to see if it needs to be resent.

[0060] In the embodiments of this application, the retransmission request includes at least one of the following information: a reservation station index field; a type field; and a storage queue number field.

[0061] The Reservation Station Index is used to index the location of the memory access instruction that needs to be resent in the reservation station; the source Type field is used to distinguish different reasons for resentment; and the Store Queue Index (sqIdx) provides an interface to provide feedback on the store queue index of the memory access instruction when the address of the previous memory access instruction is ready but the data is not ready.

[0062] In one implementation, the step of having the reservation station resend the memory access instruction based on the retransmission request includes at least one of the following: having the reservation station resend the memory access instruction after a preset first time interval when the re-execution event is the failure of the translation backstop; having the reservation station immediately resend the memory access instruction when the memory access instruction is the fetch instruction and the re-execution event is a data cache access conflict; having the reservation station resend the memory access instruction when it is determined that there is an empty entry in the data cache access failure queue when the re-execution event is a full data cache access failure queue; having the reservation station immediately resend the memory access instruction when the re-execution event is a full data cache access failure queue; and having the reservation station, when the data access instruction corresponding to the fetch instruction is passed to the fetch instruction during the re-execution event and a matching address is found but the data is not ready, resend the memory access instruction after determining the corresponding data access data based on the found data access queue number.

[0063] For example, taking the re-execution event as the translation backstop failure as an example, if the reservation station determines that the re-execution event is the translation backstop failure based on the type field in the retransmission request, it will retransmit the memory access instruction after a preset first time interval.

[0064] It's important to note that a Translation Lookaside Buffer (TLB Miss) event disappears after the Page Table Walk (PTW) completes the TLB refill. Instructions accessed via TLB Buses require a pre-defined retransmission delay before being retransmitted; memory access instructions wait in the holdout until this delay ends. This retransmission delay exists because TLB refilling takes time; retransmitting instructions before the TLB refill is complete will result in a TLB Miss, making immediate retransmission pointless. Both Load instruction pipelines and StoreAddr pipelines can experience TLB Misses.

[0065] For example, taking a data cache access conflict as an example of a re-execution event, if the memory access instruction is the data fetch instruction and the reserving station determines that the re-execution event is a data cache access conflict based on the type field in the resend request, it will immediately resend the memory access instruction.

[0066] For example, taking the case where the re-execution event is that the data cache memory access failure queue is full, the retention station determines, based on the type field in the resend request, that the re-execution event is that the data cache memory access failure queue is full, and if it is determined that there is an empty item in the data cache memory access failure queue, it resends the memory access instruction.

[0067] For example, if the re-execution event is that the data cache memory access invalidation queue is full, the reservation station determines that the re-execution event is that the data cache memory access invalidation queue is full based on the type field in the resend request, and immediately resends the memory access instruction.

[0068] It should be noted that if the data cache memory access invalidation queue (DCache MSHR) allocation fails, meaning the data cache memory access invalidation queue is full and cannot receive new data cache access invalidation requests, the reserved station can immediately resend the instruction upon receiving a DCache MSHR allocation failure resend request; alternatively, the reserved station can resend the memory access instruction if it determines that there is an empty entry in the data cache memory access invalidation queue.

[0069] For example, when a data retrieval instruction corresponding to a data retrieval instruction is forwarded to the data retrieval instruction, and it is found that the address matches but the data is not ready, during the data retrieval instruction-data retrieval instruction (Store-Load) forwarding check, the data retrieval instruction's storage queue number is also found and fed back to the holding station through the port. This allows the holding station to wait for the corresponding stored data to be generated before re-issuing the data retrieval instruction, based on the type field in the retransmission request, if it finds that the address matches but the data is not ready when the data retrieval instruction corresponding to the data retrieval instruction is forwarded to the data retrieval instruction.

[0070] It should be noted that when a store instruction forwards data to a fetch instruction, if their addresses match, but the store instruction's address is ready while the data is not, the fetch queue will not be updated, nor will a write-back operation be performed. Instead, a retransmission request will be sent through the slow feedback port at fetch pipeline stage 3 to notify the retention station that the instruction is waiting for data from a previous store instruction to be ready. During the store-load forwarding check, the store queue number field of the store instruction that the fetch instruction depends on will also be retrieved and fed back to the retention station through the slow feedback port. This retransmission has a non-fixed delay. The retention station can wait for the corresponding stored data to be generated based on the retrieved store queue number before retransmitting the fetch instruction.

[0071] In some embodiments, the retention station may determine the retransmission interval based on the target pipeline level where the re-execution event or memory access instruction is located.

[0072] For example, the retransmission request may include an event identifier corresponding to the re-execution event, so that the retention station can determine the re-execution event based on the event identifier. By implementing the embodiments of this application, after determining that a re-execution event of a memory access instruction has occurred, a target feedback port can be determined from at least one preset feedback port based on the target pipeline stage where the re-execution event or the memory access instruction is located, and a retransmission request can be sent to the retention station based on the target feedback port, so that the retention station retransmits the memory access instruction. This can improve the efficiency of memory access instruction re-execution, thereby further improving processor execution efficiency.

[0073] In some embodiments, the target feedback port can be determined based on the pipeline stage in which the memory access instruction that caused the re-execution event occurred. For an example, see [link to example]. Figure 2 , Figure 2 This is a flowchart illustrating another memory access instruction re-execution method provided in an embodiment of this application, which can be applied to a processor. Figure 2 As shown, the method may include, but is not limited to, the following steps:

[0074] S201: Determine if a memory access instruction re-execution event has occurred, and use the feedback port corresponding to the target pipeline stage where the memory access instruction is located as the target feedback port.

[0075] Each feedback port corresponds to at least one pipeline stage, and different feedback ports correspond to different pipeline stages.

[0076] In one optional implementation, the memory access instruction is a fetch instruction, and the fetch pipeline corresponding to the fetch instruction includes four pipeline stages. The feedback port includes a fast feedback port and a slow feedback port. The fast feedback port is set in pipeline stage 1 of the fetch pipeline, and the slow feedback port is set in pipeline stage 3 of the fetch pipeline. The feedback port corresponding to the target pipeline stage is used as the target feedback port, which includes: determining that the target pipeline stage is pipeline stage 0 or pipeline stage 1 of the fetch pipeline, and using the fast feedback port as the target feedback port; or, determining that the target pipeline stage is pipeline stage 2 or pipeline stage 3 of the fetch pipeline, and using the slow feedback port as the target feedback port.

[0077] As an example, the data fetch instruction execution pipeline is divided into the following stages:

[0078] The fetch pipeline stage 0 includes the following operations: instructions and operands, and immediate values ​​are read from the fetch reservation station; the address generation unit adder adds the operands and immediate values; the virtual address is calculated; the virtual address is sent to the TLB for TLB lookup; and the virtual address is sent to the data cache for tag lookup.

[0079] Stage 1 of the data retrieval pipeline includes at least one of the following operations: the TLB generates a physical address; it determines whether the data cache access has a hit; the physical address is sent to the data cache for data retrieval; the virtual / physical address is sent to the Store Queue / Committed Store Buffer to begin the forward operation from the store instruction to the load instruction; and a body conflict is checked.

[0080] Stage 2 includes at least one of the following operations: selecting data based on the data cache and the results returned from the forward pass; pruning the returned results according to the requirements of the data retrieval instruction (Load); updating the status of the corresponding item in the data retrieval queue (Load Queue); writing back the data retrieval results that have been hit in the data cache; and attempting to allocate an MSHR (Miss Status Holding Register) item if the data cache access fails.

[0081] Stage 3 includes at least one of the following operations: updating the state of the corresponding item in the Load Queue based on the feedback from the data cache.

[0082] For example, two ports can be set up in the data retrieval pipeline to provide feedback to the retention station on whether a retransmission instruction is needed. These ports are divided into fast and slow levels: a fast feedback port for data retrieval retransmission and a slow feedback port for data retrieval retransmission. The fast feedback port is set up in data retrieval pipeline stage 1, and the slow feedback port is set up in data retrieval pipeline stage 3. Instructions that need to be retransmitted and can be detected in data retrieval pipeline stages 0 and 1 will have their retransmission requests fed back to the retention station through the fast feedback port of data retrieval pipeline stage 1. Instructions that need to be retransmitted and can only be detected in data retrieval pipeline stages 2 (Load Stage 2) and 3 will have their retransmission requests fed back to the retention station through the slow feedback port of data retrieval pipeline stage 3.

[0083] It should be noted that if a data fetch instruction has already triggered a retransmission request at the fast feedback port, the instruction will not continue to flow in the pipeline, meaning the slow feedback port will not generate feedback for this instruction.

[0084] In one implementation, the memory access instruction is a store instruction, and the corresponding store pipeline includes four pipeline stages. The port includes a store retransmission feedback port, which is set in pipeline stage 1. Based on the target pipeline stage where the memory access instruction is located, a target feedback port is determined from multiple preset feedback ports. This includes determining either pipeline stage 0 or pipeline stage 1 of the target pipeline's store pipeline, and using the store retransmission feedback port as the target feedback port. The store retransmission feedback port is set in pipeline stage 1, which is also known as the fast feedback port.

[0085] As an example, the breakdown of each stage of the memory address pipeline is as follows:

[0086] Stage 0 includes at least one of the following operations: the instruction and operands, and the immediate value are read from the fetch reservation station; the address generation unit adder adds the operands and the immediate value to calculate the virtual address; the virtual address is sent to the TLB for TLB lookup.

[0087] Stage 1 includes at least one of the following operations: the TLB generates a physical address; memory access dependency checks are started; the physical address is sent to the Store Queue; if an event occurs at this stage that would cause the instruction to be resent from the reservation station, the reservation station is notified via the feedback port (rsFeedback) that the instruction needs to be resent.

[0088] Stage 2 includes the following operations: memory access dependency checking.

[0089] Stage 3 includes at least one of the following operations: completing memory access dependency checks; notifying the reorder buffer (ROB) that instructions can be submitted.

[0090] The Std Pipeline includes Stage 0, which includes at least one of the following operations: the store station provides store data; the store data is written to the store queue.

[0091] S202: Send a retransmission request to the reserved station through the target feedback port so that the reserved station retransmits the memory access command based on the retransmission request.

[0092] In the embodiments of this application, step S202 can be implemented in any of the ways described in the embodiments of this application. The embodiments of this application do not limit this, nor will they be described in detail.

[0093] By implementing the embodiments of this application, a target feedback port can be determined based on the pipeline stage where the memory access instruction that caused the re-execution event is located, and a retransmission request can be sent to the retention station based on the target feedback port, so that the retention station retransmits the memory access instruction. This enables multi-level re-execution of memory access instructions, thereby further improving the efficiency of memory access instruction re-execution.

[0094] In some embodiments, the target feedback port can be determined based on the re-execution event that occurs. As an example, see [link to example]. Figure 3 , Figure 3 This is a flowchart illustrating another memory access instruction re-execution method provided in an embodiment of this application. This method can be applied to processors. Figure 3 As shown, the method may include, but is not limited to, the following steps:

[0095] S301: Determines an event that triggers the re-execution of a memory access instruction.

[0096] In the embodiments of this application, step S301 can be implemented in any of the embodiments of this application. The embodiments of this application do not limit this and will not be described in detail.

[0097] S302: In response to a re-execution event that is a translation backstop failure, the fast feedback port is used as the target feedback port; or, in response to a memory access instruction that is a fetch instruction and a re-execution event that is a data cache access conflict, the fast feedback port is used as the target feedback port; or, in response to a memory access instruction that is a fetch instruction and a re-execution event that is a data cache access invalidation queue allocation failure, the slow feedback port is used as the target feedback port; or, in response to a memory access instruction that is a fetch instruction and a re-execution event that is a data store instruction with data not ready, the slow feedback port is used as the target feedback port.

[0098] It should be noted that both the data fetch pipeline and the data storage address pipeline may experience translation backup buffer failures. The handling methods for both are basically the same, namely, using the corresponding fast feedback port to send a retransmission request to the reserved station.

[0099] It should be noted that storage instructions do not need to be resent if the data cache memory access miss queue allocation fails. Since storage instructions merge write data within the commit storage instruction buffer, if the entire cache line is filled, it does not need to enter the data cache memory access miss queue. Only if the entire cache line is not filled is it sent from the commit storage instruction buffer to the data cache memory access miss queue. If the data cache memory access miss queue is full, it can wait in the commit storage instruction buffer, therefore it does not need to be resent from the reservation station.

[0100] S303: Send a retransmission request to the reserved station through the target feedback port so that the reserved station retransmits the memory access command based on the retransmission request.

[0101] By implementing the embodiments of this application, a target feedback port can be determined based on the re-execution event that occurs, and a retransmission request can be sent to the retention station based on the target feedback port, so that the retention station retransmits the memory access instruction. This enables multi-level re-execution of memory access instructions, thereby further improving the efficiency of memory access instruction re-execution.

[0102] Please see Figure 4 , Figure 4 This is a flowchart illustrating another memory access instruction re-execution method provided in an embodiment of this application. This method can be applied to processors. Figure 4 As shown, the method may include, but is not limited to, the following steps:

[0103] S401: Determine the re-execution event of the memory access instruction, and determine the target feedback port from at least one preset feedback port based on the target pipeline stage where the re-execution event or the memory access instruction is located.

[0104] In the embodiments of this application, step S401 can be implemented in any of the ways described in the embodiments of this application. The embodiments of this application do not limit this, nor will they be described in detail.

[0105] S402: Send a retransmission request to the retention station through the target feedback port, so that the retention station immediately retransmits the memory access instruction if it determines that the memory access instruction will not trigger a re-execution event again when it is executed again based on the retransmission request; or, so that the retention station immediately retransmits the memory access instruction if it determines that the event causing the re-execution can be resolved within a preset time period based on the retransmission request; or, so that the retention station retransmits the memory access instruction after the second time interval if it determines that the event causing the re-execution is resolved within a preset second time interval.

[0106] For example, a retransmission request is sent to the retention station through the target feedback port so that the retention station immediately retransmits the memory access instruction if it determines, based on the retransmission request, that the memory access instruction will not trigger a re-execution event again when it is executed again.

[0107] As an example, taking the data cache access conflict as a re-execution event, the reservation station can immediately resend the memory access instruction when it receives a resend request for a data cache access conflict.

[0108] It is understandable that the probability of a data cache access conflict is extremely low, and the probability of it occurring consecutively is even smaller. Therefore, when the re-execution event is a data cache access conflict, the memory access instruction can be resent immediately.

[0109] As an example, taking the re-execution event as the data cache memory access invalidation queue being full as an example, the reserved station can detect that there are free entries in the data cache memory access invalidation queue and determine that the invalidation queue will not be full again, and then immediately resend the memory access command.

[0110] As an example, when the re-execution event is a data fetch instruction corresponding to a data storage instruction being passed to the data fetch instruction, and it is found that the address matches but the data is not ready, the reservation station can determine that it will not trigger the data access instruction corresponding to the data fetch instruction again when it finds that the address matches but the data is not ready, by detecting that the data storage instruction matching the address of the data fetch instruction is ready.

[0111] For example, a retransmission request is sent to the retention station through the target feedback port, so that if the retention station determines, based on the retransmission request, that the event causing the re-execution can be resolved within a preset time, it immediately retransmits the memory access instruction.

[0112] For example, a retransmission request is sent to the retention station through the target feedback port, so that if the retention station determines that the event causing the re-execution is resolved within a preset second time interval, it retransmits the memory access instruction after the second time interval.

[0113] As an example, taking the re-execution event as a data cache access conflict, the access conflict of the target cache only lasts for the current cycle. The next clock cycle will not have an access conflict of the target cache. It is determined that the re-execution event can be resolved within a preset time, and the memory access instruction is immediately resent.

[0114] As an example, taking the case where the re-execution event is a data cache access failure queue full, the reserved station can detect that an existing entry in the failure queue is about to be processed and release space. If a free entry is available within a preset time, it can determine that the re-execution event can be resolved within the preset time and immediately resend the access command.

[0115] As an example, taking the re-execution event as a translation backup buffer, the reservation station can pre-set the TLB refill time for TLB failure, and after determining that the re-execution event is resolved after a preset time interval, the memory access instruction waits in the reservation station for the preset time interval before being resent.

[0116] Understandably, after the time interval required for TLB refilling, it can be considered that TLB refilling is complete, and the virtual address of the resent memory access instruction is accessed and hit in the TLB, and the TLB failure resentment event will not be triggered again.

[0117] By implementing the embodiments of this application, the memory access command can be resent immediately when the reserved station meets the preset conditions. This improves the re-execution efficiency of the memory access command.

[0118] The above embodiments describe the method for re-executing memory access instructions provided in this application from the perspective of the processor. Next, the method for re-executing memory access instructions provided in this application will be further described from the perspective of the reserved station.

[0119] Please see Figure 5 , Figure 5 This is a flowchart illustrating another memory access instruction re-execution method provided in an embodiment of this application. This method can be applied to reserved stations. For example... Figure 5 As shown, the method may include, but is not limited to, the following steps:

[0120] S501: Receive retransmission request.

[0121] The aforementioned retransmission request is a request sent by the processor to the reservation station based on the target pipeline stage where the re-execution event or memory access instruction is located, after determining that a re-execution event has occurred.

[0122] S502: Resend memory access instruction based on resend request.

[0123] In one implementation, the memory access instruction is a data fetch instruction, and the re-execution event is a data cache access conflict or a data cache memory access invalidation queue allocation failure. The memory access instruction is resent based on a resend request, including: immediately resending the memory access instruction based on a resend request.

[0124] For example, when the reservation station determines that the memory access instruction is a data fetch instruction based on the resend request, and the re-execution event is a data cache body access conflict or a data cache memory access invalidation queue allocation failure, it immediately resends the memory access instruction based on the resend request.

[0125] In one implementation, resending the memory access instruction based on a resend request includes: immediately resending the memory access instruction if it is determined based on the resend request that the re-execution event will not be triggered again when the memory access instruction is executed again; or immediately resending the memory access instruction if it is determined based on the resend request that the event causing the re-execution can be resolved within a preset time.

[0126] As an example, if the reserve station determines that the memory access instruction will not trigger a re-execution event again when it is executed again based on the resend request, it will immediately resend the memory access instruction.

[0127] As an example, if the reservation station determines, based on the resend request, that the event causing the re-execution can be resolved within a preset time, it will immediately resend the memory access instruction.

[0128] By implementing the embodiments of this application, the retention station can resend memory access instructions based on the resend request of the memory access instruction, so as to improve the efficiency of memory access instruction re-execution and thus improve the processor execution efficiency.

[0129] As an example, if the reservation station determines, based on the resend request, that the event causing the re-execution is resolved within a preset time interval, it will resend the memory access instruction after the preset time interval.

[0130] For example, if the re-execution event indicates that the translation backup buffer has failed, the reserved station waits for a preset time interval before resending the memory access instruction.

[0131] As an example, please see Figure 6 , Figure 6 This is a schematic diagram of the architecture of a memory access system provided in an embodiment of this application. Figure 6As shown, the memory access system contains N Load (fetch) pipelines, M separate Sta (StoreAddress) pipelines, and M Std (Store Data) pipelines. N and M are positive integers. The Load Queue and Store Queue are responsible for maintaining the order information of memory access instructions. The Load Queue is responsible for listening for subsequent refill results and performing write-back operations when a Load instruction is missing from the data cache. The Store Queue is responsible for temporarily storing Store data before instruction submission and providing data to the Load queue.

[0132] After a Store command is committed, the Store Queue moves the data to the Committed Store Buffer. The Committed Store Buffer merges Store write requests in units of cache lines, and when it is nearly full, it writes the merged Store write requests together into the data cache.

[0133] The data TLB is mainly responsible for translating virtual addresses into physical addresses, and then using these physical addresses to access memory.

[0134] Please see Figure 7 , Figure 7 This is a schematic diagram of a memory access instruction re-execution device provided in an embodiment of this application. This device 700 can be applied to a processor. Figure 7 As shown, the device 700 includes: a first processing module 701, configured to determine a re-execution event of a memory access instruction, and determine a target feedback port from at least one preset feedback port based on the target pipeline stage where the re-execution event or the memory access instruction is located; and a second processing module 701, configured to send a retransmission request to the retention station through the target feedback port, so that the retention station retransmits the memory access instruction based on the retransmission request.

[0135] In one implementation, each feedback port corresponds to at least one pipeline stage, and different feedback ports correspond to different pipeline stages. Based on the target pipeline stage where the memory access instruction is located, a target feedback port is determined from multiple preset feedback ports, including: taking the feedback port corresponding to the target pipeline stage as the target feedback port.

[0136] In one optional implementation, the memory access instruction is a fetch instruction, and the fetch pipeline corresponding to the fetch instruction includes four pipeline stages. The feedback port includes a fast feedback port and a slow feedback port. The fast feedback port is set in pipeline stage 1 of the fetch pipeline, and the slow feedback port is set in pipeline stage 3 of the fetch pipeline. The first processing module 701 can be used to: determine that the target pipeline stage is pipeline stage 0 or pipeline stage 1 of the fetch pipeline, and use the fast feedback port as the target feedback port; or, determine that the target pipeline stage is pipeline stage 2 or pipeline stage 3 of the fetch pipeline, and use the slow feedback port as the target feedback port.

[0137] In one optional implementation, the memory access instruction is a data storage instruction, and the data storage pipeline corresponding to the data storage instruction includes four pipeline stages. The feedback port includes a data storage retransmission feedback port, which is set in pipeline stage 1. The first processing module 701 can be used to: determine pipeline stage 0 or pipeline stage 1 of the target pipeline's data storage pipeline, and use the data storage retransmission feedback port as the target feedback port.

[0138] In one implementation, the re-execution event includes at least one of the following: translation back buffer failure; data cache access conflict; data cache memory access invalidation queue full; when the data fetch instruction is passed to the data fetch instruction, an address match is found but the data is not ready.

[0139] In one optional implementation, the feedback port includes at least one of a fast feedback port and a slow feedback port. The fast feedback port is located at pipeline stage 1 of the data fetch pipeline, and the slow feedback port is located at pipeline stage 3 of the data fetch pipeline. The first processing module 701 can be used to: use the fast feedback port as the target feedback port in response to a re-execution event that is a translation backstop buffer failure; use the fast feedback port as the target feedback port in response to a memory access instruction that is a data fetch instruction and a re-execution event that is a data cache access conflict; use the slow feedback port as the target feedback port in response to a memory access instruction that is a data fetch instruction and a re-execution event that is a data cache access failure queue allocation failure; and use the slow feedback port as the target feedback port in response to a memory access instruction that is a data fetch instruction and a re-execution event that is a data store instruction that is not ready.

[0140] In one implementation, the retransmission request includes at least one of the following: a reservation station index field; a type field; and a storage queue number field.

[0141] The apparatus of this application embodiment can, upon determining that a memory access instruction re-execution event has occurred, determine a target feedback port from at least one preset feedback port based on the target pipeline stage where the re-execution event or the memory access instruction is located, and send a retransmission request to the reservation station based on the target feedback port, so that the reservation station retransmits the memory access instruction. This can improve the efficiency of memory access instruction re-execution, thereby further improving processor execution efficiency.

[0142] Please see Figure 8 , Figure 8 This is a schematic diagram of a memory access instruction re-execution device provided in an embodiment of this application. This device 800 can be applied to a reserved station. Figure 8 As shown, the device 800 includes: a receiving module 801, configured to receive a retransmission request; wherein the retransmission request is a request sent by the processor to the reserved station based on the re-execution event of a memory access instruction or the target pipeline stage where the memory access instruction is located, after determining a target feedback port from at least one preset feedback port; and a processing module 802, configured to retransmit the memory access instruction based on the retransmission request.

[0143] In one implementation, the processing module 802 is configured to perform at least one of the following: if the re-execution event is a translation backstop failure, resend the memory access instruction after a preset first time interval; if the memory access instruction is a fetch instruction and the re-execution event is a data cache access conflict, immediately resend the memory access instruction; if the re-execution event is a full data cache access invalidation queue, resend the memory access instruction when it is determined that there is an empty entry in the data cache access invalidation queue; if the re-execution event is a full data cache access invalidation queue, immediately resend the memory access instruction; if the re-execution event is a fetch instruction corresponding to a store instruction being passed to the fetch instruction, and an address match is found but the data is not ready, resend the memory access instruction after determining that the corresponding store data has been generated based on the retrieved store queue number.

[0144] In one implementation, the processing module 802 is configured to perform at least one of the following: if it is determined that the re-execution event will not be triggered again when the memory access instruction is executed again, immediately resend the memory access instruction; if it is determined that the re-execution event can be resolved within a preset time period, immediately resend the memory access instruction; if it is determined that the re-execution event is resolved within a preset second time interval, resend the memory access instruction after the second time interval.

[0145] Through the apparatus of this application embodiment, the retention station can resend memory access instructions based on a memory access instruction retransmission request, thereby improving the efficiency of memory access instruction re-execution and thus improving processor execution efficiency. It should be noted that the foregoing explanation of the memory access instruction re-execution method embodiment also applies to the memory access instruction re-execution apparatus of this embodiment, and will not be repeated here.

[0146] To implement the above embodiments, this application also proposes an electronic device. Please see [link to relevant documentation]. Figure 9 , Figure 9 This is a schematic diagram of the structure of the electronic device provided in an embodiment of this application. For example... Figure 9 As shown, the electronic device 900 includes: a processor 901 and a memory 902 communicatively connected to the processor 901; the memory 902 stores computer-executable instructions; the processor 901 executes the computer-executable instructions stored in the memory to implement the method provided in the foregoing embodiments.

[0147] To implement the above embodiments, this application also proposes a storage medium storing instructions that, when executed on an electronic device, cause the electronic device to perform the methods provided in the foregoing embodiments.

[0148] To implement the above embodiments, this application also proposes a program product, including at least one of a program and instructions, wherein when the program and instructions are executed by an electronic device, they implement the steps of the method provided in the foregoing embodiments.

[0149] It should be noted that the acquisition, transmission, storage, use, and processing of data in this application comply with the relevant provisions of national laws and regulations and do not violate public order and good morals.

[0150] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0151] It is worth noting that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, they do not mean that the applicant has used or necessarily used the solution.

[0152] In the description of this application, unless otherwise stated, " / " means "or", for example, A / B can mean A or B; "and / or" in this document is merely a description of the relationship between related objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone.

[0153] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0154] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0155] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0156] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0157] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0158] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0159] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0160] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A method for re-execution of a memory access instruction, the method comprising: The method is applied to a processor, and the method includes: A re-execution event of a memory access instruction is determined, and a target feedback port is determined from at least one preset feedback port based on the re-execution event or the target pipeline stage where the memory access instruction is located; A retransmission request is sent to the retention station through the target feedback port, so that the retention station retransmits the memory access instruction based on the retransmission request; The re-execution event includes at least one of the following: Translation backup buffer failed; Data cache access conflict; The data cache access invalidation queue is full. When the data fetch instruction is passed to the data fetch instruction, the address is found to be matched but the data is not ready. The feedback port includes at least one of a fast feedback port and a slow feedback port. The fast feedback port is set in pipeline stage 1 of the data retrieval pipeline, and the slow feedback port is set in pipeline stage 3 of the data retrieval pipeline. Based on the re-execution event, a target feedback port is determined from at least one preset feedback port, including at least one of the following: In response to the re-execution event indicating that the translation backup buffer has failed, the fast feedback port is used as the target feedback port. In response to the memory access instruction being a fetch instruction and the re-execution event being a data cache access conflict, the fast feedback port is used as the target feedback port. In response to the memory access instruction being a fetch instruction and the re-execution event being the data cache memory access failure queue allocation failure, the slow feedback port is used as the target feedback port; In response to the memory access instruction being a fetch instruction and the re-execution event being that the data for the memory access instruction is not ready, the slow feedback port is designated as the target feedback port.

2. The method of claim 1, wherein, Each feedback port corresponds to at least one pipeline stage, and different feedback ports correspond to different pipeline stages. Based on the target pipeline stage where the memory access instruction is located, a target feedback port is determined from multiple preset feedback ports, including: The feedback port corresponding to the target flow stage is taken as the target feedback port.

3. The method of claim 2, wherein, The memory access instruction is a data fetch instruction, and the data fetch pipeline corresponding to the data fetch instruction includes four pipeline stages. The feedback port includes a fast feedback port and a slow feedback port. The fast feedback port is set in pipeline stage 1 of the data fetch pipeline, and the slow feedback port is set in pipeline stage 3 of the data fetch pipeline. The step of using the feedback port corresponding to the target pipeline stage as the target feedback port includes: The target pipeline stage is determined to be either pipeline stage 0 or pipeline stage 1 of the data retrieval pipeline, and the fast feedback port is used as the target feedback port; or... The target pipeline stage is determined to be pipeline stage 2 or pipeline stage 3 of the data retrieval pipeline, and the slow feedback port is used as the target feedback port.

4. The method of claim 2, wherein, The memory access instruction is a data storage instruction, and the data storage pipeline corresponding to the data storage instruction includes four pipeline stages. The feedback port includes a data storage retransmission feedback port, which is set in pipeline stage 1. The step of determining the target feedback port from multiple preset feedback ports based on the target pipeline stage where the memory access instruction is located includes: The target pipeline stage is determined to be either pipeline stage 0 or pipeline stage 1 of the data storage pipeline, and the data storage retransmission feedback port is used as the target feedback port.

5. The method of claim 1, wherein, The re-execution event is a data cache access conflict, and determining the re-execution event of the memory access instruction includes: In response to a data store operation and a data retrieval operation operating on the same cache line, a data cache access conflict is determined to have occurred.

6. The method of claim 1, wherein, The step of causing the reserved station to resend the memory access instruction based on the retransmission request includes at least one of the following: If the re-execution event is that the translation backup buffer fails, the reserved station will resend the memory access instruction after a preset first time interval; If the memory access instruction is the data fetch instruction and the re-execution event is a data cache access conflict, the memory access instruction will be resent immediately. If the reserved station determines that there is an empty entry in the data cache memory access invalidation queue when the re-execution event is that the data cache memory access invalidation queue is full, it will resend the memory access instruction. If the re-execution event is that the data cache memory access invalidation queue is full, the reserved station will immediately resend the memory access instruction; When the re-execution event is the storage instruction corresponding to the data retrieval instruction, if the storage station finds that the address matches but the data is not ready, it determines the corresponding storage data based on the retrieved storage queue number and then resends the memory access instruction.

7. The method of claim 1, wherein, The step of causing the reserved station to resend the memory access instruction based on the retransmission request includes at least one of the following: If the reserved station determines that the re-execution event will not be triggered again when the memory access instruction is executed again, it shall immediately resend the memory access instruction; If the reserved station determines that the event causing the re-execution can be resolved within a preset time period, it shall immediately resend the memory access instruction; If the reserved station determines that the event causing the re-execution is resolved within a preset second time interval, it resends the memory access instruction after the second time interval.

8. The method according to any one of claims 1-7, characterized in that, The retransmission request includes at least one of the following: Reserved site index fields; Type field; The queue number field for storing data.

9. A method for re-execution of a memory access instruction, the method comprising: The method is applied to a reserved station, and the method includes: Receive a retransmission request; wherein the retransmission request is a request sent by the processor to the reserved station based on the retransmission event or the target pipeline stage where the memory access instruction is located, after determining a target feedback port from at least one preset feedback port, and based on the target feedback port, wherein the retransmission event includes at least one of the following: Translation backup buffer failed; Data cache access conflict; The data cache access invalidation queue is full. When the data fetch instruction is passed to the data fetch instruction, the address is found to be matched but the data is not ready. The feedback port includes at least one of a fast feedback port and a slow feedback port. The fast feedback port is set in pipeline stage 1 of the data retrieval pipeline, and the slow feedback port is set in pipeline stage 3 of the data retrieval pipeline. Based on the re-execution event, a target feedback port is determined from at least one preset feedback port, including at least one of the following: In response to the re-execution event indicating that the translation backup buffer has failed, the fast feedback port is used as the target feedback port. In response to the memory access instruction being a fetch instruction and the re-execution event being a data cache access conflict, the fast feedback port is used as the target feedback port. In response to the memory access instruction being a fetch instruction and the re-execution event being the data cache memory access failure queue allocation failure, the slow feedback port is used as the target feedback port; In response to the memory access instruction being a fetch instruction and the re-execution event being that the data for the memory access instruction is not ready, the slow feedback port is used as the target feedback port. The memory access instruction is resent based on the resent request.

10. A re-execution apparatus of a memory access instruction, characterized by, The device is applied to a processor, and the device includes: A re-execution event of a memory access instruction is determined. Based on the re-execution event or the target pipeline stage where the memory access instruction is located, a target feedback port is determined from at least one preset feedback port, wherein the re-execution event includes at least one of the following: Translation backup buffer failed; Data cache access conflict; The data cache access invalidation queue is full. When the data fetch instruction is passed to the data fetch instruction, the address is found to be matched but the data is not ready. The feedback port includes at least one of a fast feedback port and a slow feedback port. The fast feedback port is set in pipeline stage 1 of the data retrieval pipeline, and the slow feedback port is set in pipeline stage 3 of the data retrieval pipeline. Based on the re-execution event, a target feedback port is determined from at least one preset feedback port, including at least one of the following: In response to the re-execution event indicating that the translation backup buffer has failed, the fast feedback port is used as the target feedback port. In response to the memory access instruction being a fetch instruction and the re-execution event being a data cache access conflict, the fast feedback port is used as the target feedback port. In response to the memory access instruction being a fetch instruction and the re-execution event being the data cache memory access failure queue allocation failure, the slow feedback port is used as the target feedback port; In response to the memory access instruction being a fetch instruction and the re-execution event being that the data for the memory access instruction is not ready, the slow feedback port is used as the target feedback port. A retransmission request is sent to the retention station through the target feedback port, so that the retention station retransmits the memory access instruction based on the retransmission request.

11. A re-execution apparatus of a memory access instruction, characterized by, The device is used at a retention station, and the device includes: A receiving module is configured to receive a retransmission request; wherein the retransmission request is a request sent by the processor to the reserved station based on the retransmission event or the target pipeline stage where the memory access instruction is located, after determining a re-execution event of a memory access instruction, identifying a target feedback port from at least one preset feedback port, and sending the request to the reserved station based on the target feedback port; wherein the re-execution event includes at least one of the following: Translation backup buffer failed; Data cache access conflict; The data cache access invalidation queue is full. When the data fetch instruction is passed to the data fetch instruction, the address is found to be matched but the data is not ready. The feedback port includes at least one of a fast feedback port and a slow feedback port. The fast feedback port is set in pipeline stage 1 of the data retrieval pipeline, and the slow feedback port is set in pipeline stage 3 of the data retrieval pipeline. Based on the re-execution event, a target feedback port is determined from at least one preset feedback port, including at least one of the following: In response to the re-execution event indicating that the translation backup buffer has failed, the fast feedback port is used as the target feedback port. In response to the memory access instruction being a fetch instruction and the re-execution event being a data cache access conflict, the fast feedback port is used as the target feedback port. In response to the memory access instruction being a fetch instruction and the re-execution event being the data cache memory access failure queue allocation failure, the slow feedback port is used as the target feedback port; In response to the memory access instruction being a fetch instruction and the re-execution event being that the data for the memory access instruction is not ready, the slow feedback port is used as the target feedback port. The processing module is used to resend the memory access instruction based on the resend request.

12. An electronic device, comprising: include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 8 and 9.

13. A storage medium having stored therein instructions, the instructions comprising: When the instructions are executed on an electronic device, the electronic device causes the electronic device to perform the method of any one of claims 1 to 8 and 9.

14. A program product comprising at least one of a program, instructions, characterized in that When at least one of the programs or instructions is executed by an electronic device, it implements the steps of the method according to any one of claims 1 to 8 and 9.

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