An FPGA device, test system and method

Abstract

This invention provides an FPGA device, a testing system, and a method. The FPGA device includes at least two signal acquisition modules that synchronously sample received input signals based on a synchronous sampling clock to obtain corresponding sampled data; a processing module that allocates storage addresses to the sampled data obtained by each signal acquisition module according to different storage address ranges of external storage chips; an interconnect module that receives sampled data and corresponding storage addresses transmitted from each signal acquisition module at different clock frequencies, and transmits the sampled data and corresponding storage addresses at the controller's operating clock frequency; and a controller that receives the sampled data and corresponding storage addresses transmitted from the interconnect module, and writes the sampled data to the external storage chips according to the storage addresses corresponding to the sampled data. The FPGA device of this invention can improve the bandwidth utilization and storage capacity utilization of written data.

Description

Technical Field

[0001] This invention relates to the field of static storage technology, and more particularly to an FPGA device, a testing system, and a method. Background Technology

[0002] Prototype verification of FPGA (Field Programmable Gate Array) refers to building a hardware model that can realistically simulate the operation of the chip by utilizing the reconfigurable characteristics of FPGA before the chip is officially taped out and put into production. Software and hardware co-verification and system-level testing are then carried out on this hardware model to discover and correct design defects in advance.

[0003] To expand the storage capacity of FPGA hardware models, a DDR controller can be instantiated internally and connected to high-capacity DDR (DDR SDRAM, Double Data Rate Synchronous Dynamic Random Access Memory) chips. However, with the increasing complexity of integrated circuits, the observable signals in the Design Under Test (DUT) often correspond to multiple asynchronous clock domains. If global asynchronous clock sampling is used, according to the sampling theorem, the sampling frequency of the global asynchronous clock must be twice the highest clock frequency among the multiple asynchronous clock domains. In this case, the sampling frequency of the global asynchronous clock may be much higher than the signal frequency of the lower-speed clock domains among the multiple asynchronous clock domains, resulting in a large amount of redundant sampling data. This wastes DDR write bandwidth, occupies storage capacity, and limits the width and depth of the observable signal. Therefore, there are areas for improvement. Summary of the Invention

[0004] This invention provides an FPGA device, a testing system, and a method to solve the technical problem that existing FPGA hardware models using global asynchronous clock sampling generate a large amount of redundant sampling data.

[0005] This invention proposes an FPGA device, comprising:

[0006] At least two signal acquisition modules are provided, each of which is used to receive input signals with different clock frequencies and is configured with a synchronous sampling clock with the same clock frequency as the corresponding input signal. The received input signals are synchronously sampled based on the synchronous sampling clock to obtain the corresponding sampling data. The processing module is used to allocate storage addresses to the sampled data obtained by each signal acquisition module according to the different storage address ranges of the external storage particles; The interconnect module is used to receive sampling data and corresponding storage addresses transmitted by each of the signal acquisition modules at different clock frequencies, and to transmit the sampling data and corresponding storage addresses at the controller's operating clock frequency; the interconnect module is also used to read the sampling data from external storage particles through its readback interface; The controller is used to receive the sampling data and the corresponding storage address transmitted by the interconnect module, and write the sampling data to the external storage chip according to the storage address corresponding to the sampling data.

[0007] In one embodiment of the present invention, the signal acquisition module is further configured to access the working clock corresponding to the input signal in the module to be observed, and use the working clock as its own synchronous sampling clock to synchronously sample the input signal.

[0008] In one embodiment of the present invention, the processing module is further configured to allocate corresponding storage addresses to the sampled data in the storage address range corresponding to the signal acquisition module, according to the generation order of the sampled data obtained by the signal acquisition module. The storage address range corresponding to the signal acquisition module is a fixed and continuous address range in the external storage particle, and the storage address ranges corresponding to different signal acquisition modules do not overlap with each other.

[0009] In one embodiment of the present invention, the processing module is further configured to allocate a corresponding storage address to the sampled data, compare the storage address with the last storage address of the corresponding storage address interval, and when the storage address is the same as the last storage address of the corresponding storage address interval, continue to allocate a storage address for the next sampled data using the first storage address of the storage address interval, thereby forming a continuous cyclic allocation of storage addresses for the sampled data.

[0010] In one embodiment of the present invention, the interconnection module is further configured to transmit the sampling data and its storage address corresponding to the multiple signal acquisition modules in sequence according to the preset priority order of the multiple signal acquisition modules when multiple signal acquisition modules have sampling data to be transmitted at the same time.

[0011] This invention also proposes a test system for FPGA devices, comprising: The FPGA device described above is used to receive signals to be observed transmitted by the module under test at different clock frequencies, sample the signals to be observed to obtain sampled data, and write the sampled data into an external storage chip. The host is used to read the sampled data stored in the external storage chip through the readback interface of the interconnect module in the FPGA device, and generate the actual waveform file from the read sampled data; The host computer is also used to compare the actual waveform file with the simulated waveform file of the signal to be observed, and generate test information for the FPGA device based on the comparison results.

[0012] In one embodiment of the present invention, the host is further configured to obtain the storage address range corresponding to the signal acquisition module in the FPGA device on the external storage chip, and to obtain the storage address allocated to the sampling data of the signal acquisition module. When the storage addresses of all sampled data are distributed in a continuously increasing manner within the storage address range, the sampled data are read out from the storage address range in sequence according to the storage address allocated to the sampled data. Otherwise, confirm the start and end addresses of the sampled data in the storage address range, and read the sampled data from the storage address range in sequence according to the start and end addresses of the sampled data.

[0013] In one embodiment of the present invention, the host is further configured to read sampled data from each storage address range of the external storage particle and generate independent actual waveform files respectively; wherein, the actual waveform file corresponding to the sampled data in each storage address range is used to compare with the simulation waveform file of the signal to be observed corresponding to the sampled data.

[0014] In one embodiment of the present invention, the host is further configured to use the common multiple of the clock frequencies of the sampled data in multiple signal acquisition modules as the global observation frequency, and calculate the ratio between the global observation frequency and the clock frequency of the sampled data in each signal acquisition module to obtain the interpolation multiple of the sampled data in each signal acquisition module. The host is also used to copy and interpolate the sampled data in each storage address range according to the corresponding interpolation multiple, and generate a unified actual waveform file based on all the copied and interpolated sampled data, so as to compare it with the simulation waveform files of all the signals to be observed.

[0015] This invention also proposes a testing method for FPGA devices, using any of the FPGA devices described above, comprising: The FPGA device receives signals of different clock frequencies transmitted by the module under test, samples the signals to be observed to obtain sampled data, and writes the sampled data into an external storage chip. The sampled data stored in the external memory chip is read out through the readback interface of the interconnect module in the FPGA device, and the read sampled data is used to generate an actual waveform file. The actual waveform file is compared with the simulated waveform file of the signal to be observed, and test information of the FPGA device is generated based on the comparison results.

[0016] The beneficial effects of this invention are as follows: The FPGA device, testing system, and method proposed in this invention, for input signals with different clock frequencies, utilize signal acquisition modules with corresponding clock frequencies for acquisition. This allows each signal acquisition module to synchronously sample the input signal based on a synchronous sampling clock, avoiding the bandwidth and storage capacity waste caused by using a unified global asynchronous oversampling clock. This significantly improves the total bandwidth of the observable signal with limited bandwidth resources. Furthermore, after receiving sampled data at different clock frequencies from each signal acquisition module, the interconnect module transmits the sampled data and its corresponding storage address at the controller's operating clock frequency. The clock frequencies corresponding to each signal acquisition module are converted to the controller's operating clock frequency, and the sampled data is transmitted at the controller's operating clock frequency. Therefore, the FPGA device of this invention can improve the bandwidth utilization and storage capacity utilization for written data. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] In the attached diagram: Figure 1 This is a structural block diagram of an FPGA device provided in an embodiment of the present invention.

[0019] Figure 2 This is a structural block diagram of a test system for an FPGA device provided in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram illustrating the steps of a testing method for an FPGA device provided in an embodiment of the present invention. Detailed Implementation

[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0022] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0023] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0024] During the debugging phase of FPGA (Field Programmable Gate Array) prototyping, when the hardware model experiences operational anomalies, a means is needed to capture internal signals in real time on the hardware model for triggering abnormal events and capturing related signals. This triggering and capture functionality can be achieved by embedding a logic analyzer in the hardware model. However, the logic analyzer will compete with the test module to be verified for the limited block RAM resources in the hardware model. Because the internal block RAM resources of existing commercial FPGAs have limited capacity (typically at most several hundred megabits), the number of observable signals and sampling depth are very limited.

[0025] To address the aforementioned issues, current FPGA hardware models internally instantiate a DDR (DDR SDRAM, Double Data Rate Synchronous Dynamic Random Memory) controller and externally connect large-capacity DDR chips. However, with increasing integrated circuit complexity, target designs often involve multiple clock domains, making globally synchronous clock sampling difficult. When using globally asynchronous clock sampling, according to the sampling theorem, the sampling clock must be twice the highest clock frequency component across multiple clock domains. Therefore, with globally asynchronous clock sampling, the globally asynchronous sampling clock may be several times the sampling signal frequency of the lowest clock domain, resulting in wasted DDR chip write bandwidth and multiple duplicate sample values ​​for each data point, further wasting DDR chip storage capacity.

[0026] Please see Figures 1 to 3This invention proposes an FPGA device, a testing system, and a method. The FPGA device 10 stores sampled data through an external storage chip 60, which improves storage capacity by at least several hundred times compared to the traditional method of embedding logic analyzers within the FPGA. Furthermore, the FPGA device 10 uses a synchronous clock to sample different input signals and writes the sampled data of the input signals in partitions within the external storage chip 60, thereby improving the bandwidth utilization and storage capacity utilization of the written data in the storage chip 60. Detailed descriptions are provided below using specific embodiments.

[0027] Please see Figure 1 The present invention proposes an FPGA device 10, which may include a signal acquisition module 20, a processing module 30, an interconnection module 40, and a controller 50.

[0028] Multiple signal acquisition modules 20 are used to receive multiple input signals with different clock frequencies. Each signal acquisition module 20's input terminal is connected to an external test excitation source to receive an input signal at a specific clock frequency. Simultaneously, each signal acquisition module 20 is configured with an independent synchronous sampling clock, the clock frequency of which is set to be the same as the clock frequency of the corresponding input signal. The signal acquisition module 20 uses this synchronous sampling clock to perform edge-aligned synchronous sampling of the received input signal, thereby generating sampled data consistent with the clock domain of the input signal. Since the clock frequencies of different input signals may be different, for example, one input signal is 40MHz and another is 30MHz, the corresponding signal acquisition module 20 uses synchronous sampling clocks of 40MHz and 30MHz respectively for sampling, avoiding the bandwidth waste and sampling redundancy caused by using a uniform global asynchronous oversampling clock. Furthermore, synchronous clock sampling avoids the situation where metastable sampled data is obtained by asynchronous clock sampling.

[0029] The processing module 30 is connected to each signal acquisition module 20 and is responsible for allocating storage addresses to the sampled data obtained by each signal acquisition module 20. The processing module 30 is pre-configured with address mapping information corresponding to the storage space of the external storage particles 60. This address mapping information divides the total storage space of the external storage particles 60 into multiple non-overlapping storage address ranges, each uniquely corresponding to one signal acquisition module 20. When a signal acquisition module 20 generates a piece of sampled data, the processing module 30 selects a currently available storage address from its corresponding storage address range based on the identifier of the signal acquisition module 20 and associates that storage address with the sampled data. In this way, the processing module 30 ensures that the sampled data of each signal acquisition module 20 is independently directed to its dedicated storage area, laying the foundation for subsequent multi-channel independent readback and data reconstruction.

[0030] Interconnect module 40 is connected to multiple signal acquisition modules 20 and controller 50. Interconnect module 40 integrates cross-clock domain processing logic and priority arbitration logic. Interconnect module 40 receives sampled data from different signal acquisition modules 20 and the corresponding storage addresses allocated to this sampled data by processing module 30. Since each signal acquisition module 20 operates at a different sampling clock frequency, while controller 50 operates in a fixed high-frequency clock domain, interconnect module 40 synchronizes the received sampled data at different clock frequencies and their storage addresses to the operating clock domain of controller 50.

[0031] The controller 50 is connected to the interconnect module 40 and to an external memory chip 60 located outside the FPGA device 10. The controller 50 is configured to conform to the interface protocol of the external memory chip 60, such as the DDR4 protocol, and is responsible for performing the actual write and read operations. The controller 50 may be a DDR controller, and the memory chip 60 may be a DDR memory chip.

[0032] The controller 50 receives a request from the interconnect module 40, which contains the sampled data to be written and its corresponding storage address. Based on this storage address, the controller 50 writes the sampled data to the specified location on the external storage chip 60 via the physical layer interface. During the data writing process, the controller 50 handles the low-level timing control of the storage chip 60, such as refresh, precharge, and activation, to ensure reliable data storage. Simultaneously, when a read request is received through the readback interface of the interconnect module 40, the controller 50 reads data from the corresponding address of the external storage chip 60 and returns the read data to the interconnect module 40, ultimately outputting it through the readback interface.

[0033] In a specific application example of this invention, a prototype verification of an ASIC design under test containing three clock domains (40MHz, 30MHz, and 10MHz) is performed using an FPGA board supporting 8GB DDR4 memory chips. To address the problem that traditional global asynchronous sampling methods require excessive bandwidth (80MHz × 1024bit × 3 = 245760Mbit / s), exceeding the total DDR bandwidth of 300MHz × 512bit = 153600Mbit / s, this embodiment employs a multi-clock domain independent sampling technique.

[0034] The FPGA device 10 internally instantiates three independent signal acquisition modules 20, corresponding to sampling clocks of 40MHz, 30MHz, and 10MHz, respectively. The total synchronous sampling bandwidth requirement of the three signal acquisition modules 20 is reduced to 40×1024+30×1024+10×1024=81920Mbit / s, which fully meets the DDR bandwidth limit. Accordingly, the processing module 30 divides the 8GB DDR capacity into three independent memory address ranges in a 4:3:1 ratio and allocates them to the three signal acquisition modules 20 respectively.

[0035] The interconnect module 40 is responsible for synchronizing the sampled data and their addresses from the three signal acquisition modules 20 across clock domains, and then writing them to the corresponding partitions of the external storage chip 60 via the controller 50. This process enables synchronous sampling and partitioned storage of signals from multiple clock domains in their respective clock domains, effectively avoiding bandwidth waste and metastability issues, and providing a foundation for subsequent independent data readback and waveform reconstruction.

[0036] Please see Figure 1 In one embodiment of the present invention, the signal acquisition module 20 is further configured to access the working clock corresponding to the input signal in the module to be observed, and use the working clock as its own synchronous sampling clock to synchronously sample the input signal.

[0037] Specifically, during operation, the input signal of the module under observation has a corresponding operating clock frequency. The signal acquisition module 20 is connected to the operating clock signal line of the module under observation, directly acquiring the operating clock of the module under observation. The signal acquisition module 20 configures its internal synchronous sampling clock to have the same frequency as the operating clock of the module under observation. Therefore, when the signal acquisition module 20 samples the input signal, the sampling clock and the clock frequency of the input signal remain strictly consistent, achieving synchronous sampling of the input signal and avoiding sampling distortion or data misjudgment caused by the asynchrony between the sampling clock and the signal clock.

[0038] Please see Figure 1 In one embodiment of the present invention, the processing module 30 is further configured to allocate corresponding storage addresses to the sampled data sequentially within the storage address range corresponding to the signal acquisition module 20, according to the generation order of the sampled data obtained by the signal acquisition module 20. The storage address range corresponding to the signal acquisition module 20 is a fixed and continuous address range in the external storage particle 60, and the storage address ranges corresponding to different signal acquisition modules 20 do not overlap.

[0039] Specifically, the processing module 30 internally maintains an address mapping table corresponding to the address space of the external storage chip 60. This address mapping table is pre-written by the host computer software during the FPGA device 10 configuration phase. Its core function is to divide the total storage capacity of the external storage chip 60 into multiple fixed and contiguous storage address ranges, and to uniquely bind each of these storage address ranges to a different signal acquisition module 20. The storage address ranges corresponding to different signal acquisition modules 20 strictly do not overlap in address space, ensuring that the sampling data of each signal acquisition module 20 has an independent physical storage area, and that data overwriting or address conflicts do not occur.

[0040] When a signal acquisition module 20 completes a signal acquisition and generates a sample data point based on its synchronous sampling clock, it sends a write request to the processing module 30. This request carries the sampled data content and the module's own identification information. Upon receiving the write request, the processing module 30 first looks up the address mapping table based on the module's identification to determine its dedicated storage address range. Then, within this address range, the processing module 30 allocates an incrementing storage address for each sample data point according to the order in which it was generated. Internally, the processing module 30 maintains an independent address counter for each signal acquisition module 20. Each time a data point is allocated, the corresponding address counter automatically increments by the address increment corresponding to the data bit width, ensuring that the storage address of the sampled data strictly matches its generation order. This provides an accurate address basis for subsequent sequential data reading and signal timing waveform reconstruction.

[0041] Please see Figure 1 In one embodiment of the present invention, the processing module 30 is further configured to allocate a corresponding storage address to the sampled data, compare the storage address with the last storage address of the corresponding storage address interval, and when the storage address is the same as the last storage address of the corresponding storage address interval, continue to allocate a storage address for the next sampled data using the first storage address of the storage address interval, thereby forming a continuous cyclic allocation of the storage address of the sampled data.

[0042] Specifically, the processing module 30 maintains an address counter for each signal acquisition module 20, which is used to sequentially allocate storage addresses within its dedicated fixed continuous address range. After allocating an address for each piece of sampled data, the processing module 30 immediately compares the address with the last address of the corresponding storage address range to determine whether the current write has reached the end of the storage address range.

[0043] If the currently allocated address has not yet reached the end of the storage address range, the address counter increments normally, preparing for the next data allocation. If the currently allocated address is exactly equal to the last address of the storage address range, the processing module 30 resets the address counter to the starting address of that storage address range and continues to allocate this starting address for the next sampled data. Through this mechanism, the processing module 30 ensures that newly generated sampled data automatically overwrites the oldest historical data within the storage address range corresponding to each signal acquisition module 20, achieving continuous monitoring of the continuous signal stream within limited storage capacity and ensuring that valid data before and after the trigger event is preserved.

[0044] Please see Figure 1 In one embodiment of the present invention, the interconnection module 40 is further configured to transmit the sampling data and its storage address corresponding to the multiple signal acquisition modules 20 in sequence according to the preset priority order of the multiple signal acquisition modules 20 when multiple signal acquisition modules 20 have sampling data to be transmitted at the same time.

[0045] Specifically, when multiple signal acquisition modules 20 simultaneously need to transmit sampled data, the interconnect module 40, according to a preset priority order, such as a polling mechanism or a fixed priority mechanism, sequentially combines the sampled data and addresses of each signal acquisition module 20 into a transaction request and sends it to the controller 50. Furthermore, the interconnect module 40 is also configured with a readback interface, which is used to respond to external read requests, read the sampled data within a specified storage address range from the external storage chip 60, and return it.

[0046] Please see Figure 2 In one embodiment of the present invention, the test system for the FPGA device may include the FPGA device 10 and the host 70 described above.

[0047] First, the FPGA device 10 is used to receive the observation signals transmitted by the module under test at different clock frequencies, sample the observation signals to obtain sampled data, and write the sampled data into the external storage chip 60.

[0048] The host 70 is used to read out the sampled data stored in the external storage chip 60 through the readback interface of the interconnect module 40 in the FPGA device 10, and generate an actual waveform file from the read sampled data.

[0049] The host 70 is also used to compare the actual waveform file with the simulated waveform file of the signal to be observed, and generate test information for the FPGA device 10 based on the comparison results.

[0050] Specifically, the test system for FPGA device 10 consists of a host 70 and FPGA device 10. In the test scenario of FPGA device 10, the module under test embedded in FPGA device 10 can generate multiple observation signals at different clock frequencies and send them to the corresponding signal acquisition module 20 of FPGA device 10 through physical connection channels. In actual test scenarios, the module under test can be a chip with a specific model number. These observation signals cover the multi-clock domain scenarios of the design under test in actual operation, providing an input basis for comprehensively verifying the functionality of FPGA device 10.

[0051] It should be understood here that the module under test can generate multiple input signals with different clock frequencies, which is used in the application scenario. The module under test can also generate multiple observation signals with different clock frequencies, which is used in the testing scenario.

[0052] After receiving the signal to be observed, the FPGA device 10 uses multiple signal acquisition modules 20 to sample the signal based on their respective configured synchronous sampling clocks, generating sampled data. The processing module 30 allocates a storage address for each sampled data within a dedicated address range of the external storage granularity 60. The interconnect module 40 synchronizes the sampled data and their addresses across clock domains and transmits them to the controller 50. The controller 50 then writes the sampled data into the external storage granularity 60. The entire acquisition process is completed automatically within the FPGA device 10, achieving efficient real-time acquisition of signals from multiple clock domains.

[0053] After sampling, the host 70 reads the sampled data from the external storage chip 60 through the readback interface of the interconnect module 40 and generates a visualized actual waveform file. Subsequently, the host 70 compares the actual waveform file with a pre-generated simulation waveform file generated by simulation software cycle by cycle, automatically marking all locations where differences exist. Based on the comparison results, the host 70 generates a detailed test information report, including whether the test passed, the specific time and value of the signal deviation, and possible fault location information, providing crucial information for developers to evaluate the correctness of the FPGA device 10 implementation and locate design defects.

[0054] Waveform files are files that graphically record the relationship between digital signals and time. They represent the high and low levels of signals at the physical level, such as high voltage representing logic 1 and low voltage representing logic 0, and arrange them continuously along a time axis to form a square wave pattern similar to that shown in the attached diagram. Through this visualization method, one can intuitively observe the signal transition moments, the timing relationships between multiple signals, and the specific values ​​transmitted on the data bus, thereby determining whether the acquired data is consistent with the design expectations.

[0055] Please see Figure 2In one embodiment of the present invention, the host 70 is also used to obtain the storage address range corresponding to the signal acquisition module 20 in the FPGA device 10 on the external storage chip 60, and to obtain the storage address allocated to the sampling data of the signal acquisition module 20.

[0056] When the storage addresses of all sampled data are distributed in a continuously increasing manner within the storage address range, the sampled data are read out from the storage address range in sequence according to the storage address allocated to the sampled data.

[0057] Otherwise, confirm the start and end addresses of the sampled data in the storage address range, and read the sampled data from the storage address range in sequence according to the start and end addresses of the sampled data.

[0058] Specifically, during the data readback phase, the host 70 first obtains the storage address range of each signal acquisition module 20 on the external storage chip 60, as well as the storage address allocated to the sampled data of that signal acquisition module 20. For example... Figure 2 As shown, the host 70 can obtain the storage address allocated to the sampling data of the signal acquisition module 20 through the readback interface and response interface of the interconnect module 40. The host 70 determines the distribution of the sampling data in the storage area based on this address information.

[0059] For example, if the analysis shows that the storage addresses of all sampled data are distributed in a continuously increasing manner within the storage address range, that is, the storage address range is not covered by a loop, the host 70 will directly start from the starting address allocated to the sampled data and read all the sampled data in ascending order of address.

[0060] If the analysis shows that the distribution of the storage addresses of the sampled data within the storage address range has looped, that is, new data has overwritten old data in the storage address range, then the host 70 needs to determine the actual (real) start and end positions of the sampled data in the storage address range based on the start write address, the last write address, and the storage address range allocated to the sampled data. Then, following the order of reading from the actual (real) start address to the last address of the storage address range, and then reading from the first address of the storage address range to the actual (real) end address, the sampled data in the storage address range will be completely reassembled and read out.

[0061] Please see Figure 2 In one embodiment of the present invention, the host 70 is further configured to read sampled data from each memory address range of the external storage particle 60 and generate independent actual waveform files for each. The actual waveform file corresponding to the sampled data in each memory address range is used to compare with the simulated waveform file of the signal to be observed corresponding to that sampled data.

[0062] Specifically, after the host 70 completes the readback of the sampled data, the host 70 also obtains an independent raw sampled dataset for each signal acquisition module 20, and generates an independent actual waveform file for each sampled dataset. Each actual waveform file accurately reproduces the actual level changes of all observed signals within a specific clock domain during actual hardware operation. The file name or metadata may contain the corresponding signal acquisition module 20 identifier and clock domain information for subsequent identification and management.

[0063] During functional verification, the host computer 70 invokes a waveform comparison tool to compare the actual waveform files with pre-generated simulation waveform files for the signals to be observed, each according to its clock domain. This allows for observation of whether the actual waveform and simulation waveform match in each clock domain, thus isolating complex issues across clock domains. When a signal deviation occurs in a clock domain, the host computer 70 can immediately locate the specific actual waveform file and its corresponding simulation waveform file, accurately pinpointing the clock domain and the exact time of the fault, greatly improving the efficiency and accuracy of problem localization during prototype verification.

[0064] Please see Figure 2 In one embodiment of the present invention, the host 70 is further configured to use the common multiple of the clock frequencies of the sampled data in the multiple signal acquisition modules 20 as the global observation frequency, and calculate the ratio between the global observation frequency and the clock frequency of the sampled data in each signal acquisition module 20 to obtain the interpolation multiple of the sampled data in each signal acquisition module 20.

[0065] The host 70 is also used to copy and interpolate the sampled data in each memory address range according to the corresponding interpolation multiple, and generate a unified actual waveform file based on all the copied and interpolated sampled data, so as to compare it with the simulation waveform files of all the signals to be observed.

[0066] Specifically, to improve the testing efficiency of the FPGA device 10, it is necessary to integrate the observed signals from all clock domains into a single waveform file for global timing analysis. To address this requirement, the host 70 first acquires the clock frequencies of the sampled data from all signal acquisition modules 20 and calculates the least common multiple of these clock frequencies as a unified global observation frequency. After determining the global observation frequency, the host 70 calculates the ratio of this global observation frequency to the clock frequency of the sampled data in each signal acquisition module 20, obtaining the interpolation multiple corresponding to the sampled data from each signal acquisition module 20.

[0067] The host 70 then reads the raw sampled data from each memory address range and performs copy interpolation on the sampled dataset in each memory address range according to the calculated interpolation factor, thereby expanding the sampled data density of each clock domain to match the global observation frequency. After completing the copy interpolation, the host 70 also aligns the copied interpolated sampled data along the time axis to generate a unified actual waveform file.

[0068] Finally, the host computer 70 merges all aligned interpolated data according to the time axis order of the global observation frequency to generate a unified actual waveform file. This unified actual waveform file can be compared with the simulation waveform file that has also undergone interpolation and alignment processing to intuitively analyze whether the timing relationship between signals across clock domains is correct.

[0069] Taking a specific verification scenario as an example, the design under test includes three clock domains: 40MHz, 30MHz, and 10MHz. The total bit width of the observed signal in each clock domain is 1024 bits, and the sampled data is stored in three independent address ranges of the external storage chip 60. The host 70 reads the sampled data from the three storage address ranges respectively, and each storage address range stores a continuous data segment before and after the trigger point.

[0070] To integrate the signals from the three clock domains into a single waveform file for global timing analysis, host 70 selected 120MHz as the global observation frequency, which is the least common multiple of 40MHz, 30MHz, and 10Hz. Host 70 calculated the interpolation factor for each clock domain: 40MHz data required 3x replication interpolation, 30MHz data required 4x replication interpolation, and 10MHz data required 12x replication interpolation. Host 70 performed the corresponding replication interpolation operation on each of the three datasets, ensuring that the sampling point density of all data was uniformly one point every 8.33 nanoseconds.

[0071] After interpolation, the host 70 precisely aligns the three interpolated sampled datasets on the time axis using their respective trigger point times (all three trigger points are the same and triggered by the same trigger signal across clock domains). Then, it merges all signals in 120MHz time axis order to generate a unified waveform file containing all observed signals. Opening this file allows simultaneous viewing of all signal waveforms from the 40MHz, 30MHz, and 10MHz clock domains, with all signal transitions displayed on the same 120MHz time grid, facilitating intuitive analysis of potential timing violations or logic errors in cross-clock domain interactions.

[0072] Please see Figure 3In one embodiment of the present invention, a testing method for an FPGA device 10 is proposed. The method using the FPGA device 10 described above may include the following steps.

[0073] Step S10: Receive the observation signals transmitted by the module under test at different clock frequencies through the FPGA device, sample the observation signals to obtain sampled data, and write the sampled data into an external storage chip.

[0074] Step S20: Read out the sampled data stored in the external storage chip through the readback interface of the interconnect module in the FPGA device, and generate an actual waveform file from the read sampled data.

[0075] Step S30: Compare the actual waveform file with the simulated waveform file of the signal to be observed, and generate test information for the FPGA device based on the comparison results.

[0076] Specifically, firstly, the FPGA device 10 receives the observation signals transmitted by the module under test at different clock frequencies, performs synchronous sampling through multiple internal signal acquisition modules 20, and writes the sampled data into the external storage chip 60.

[0077] After sampling, the host 70 reads the sampled data from the external storage chip 60 through the readback interface of the interconnect module 40 and generates an actual waveform file. Finally, the host 70 compares the actual waveform file with the simulated waveform file and generates test information based on the comparison results to evaluate the correctness of the FPGA device 10's functions.

[0078] In summary, this invention proposes an FPGA device, a testing system, and a method. For input signals with different clock frequencies, the FPGA device uses signal acquisition modules with corresponding clock frequencies for acquisition. This allows each signal acquisition module to synchronously sample the input signal based on a synchronous sampling clock, avoiding the bandwidth and storage capacity waste caused by using a unified global asynchronous oversampling clock. This significantly improves the total bandwidth of the observable signal with limited bandwidth resources. Furthermore, after receiving sampled data at different clock frequencies from each signal acquisition module, the interconnect module transmits the sampled data and its corresponding storage address at the controller's operating clock frequency. The clock frequencies of the sampled data corresponding to each signal acquisition module are converted to the controller's operating clock frequency, and the sampled data is transmitted at the controller's operating clock frequency. Therefore, the FPGA device of this invention can improve the bandwidth utilization and storage capacity utilization for written data.

[0079] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An FPGA device, characterized in that, include: At least two signal acquisition modules are provided, each of which is used to receive input signals with different clock frequencies and is configured with a synchronous sampling clock with the same clock frequency as the corresponding input signal. The received input signals are synchronously sampled based on the synchronous sampling clock to obtain the corresponding sampling data. The signal acquisition module uses a synchronous sampling clock to perform edge-aligned synchronous sampling of the received input signal to generate sampling data consistent with the clock domain of the input signal. The processing module is used to allocate storage addresses to the sampled data obtained by each of the signal acquisition modules according to the different storage address ranges of the external storage particles; The interconnect module is used to receive sampling data and corresponding storage addresses transmitted by each of the signal acquisition modules at different clock frequencies, and to transmit the sampling data and corresponding storage addresses at the controller's operating clock frequency; the interconnect module is also used to read the sampling data from external storage particles through its readback interface; The controller is used to receive the sampling data and the corresponding storage address transmitted by the interconnect module, and write the sampling data to the external storage chip according to the storage address corresponding to the sampling data.

2. The FPGA device according to claim 1, characterized in that, The signal acquisition module is also used to access the working clock corresponding to the input signal in the module to be observed, and to use the working clock as its own synchronous sampling clock to synchronously sample the input signal.

3. The FPGA device according to claim 1, characterized in that, The processing module is also used to allocate corresponding storage addresses to the sampled data in the storage address range corresponding to the signal acquisition module, according to the generation order of the sampled data obtained by the signal acquisition module. The storage address range corresponding to the signal acquisition module is a fixed and continuous address range in the external storage particle, and the storage address ranges corresponding to different signal acquisition modules do not overlap with each other.

4. The FPGA device according to claim 3, characterized in that, The processing module is further configured to allocate a corresponding storage address to the sampled data, compare the storage address with the last storage address in the corresponding storage address range, and when the storage address is the same as the last storage address in the corresponding storage address range, continue to allocate a storage address for the next sampled data using the first storage address in the storage address range, thus forming a continuous cyclic allocation of storage addresses for the sampled data.

5. The FPGA device according to claim 1, characterized in that, The interconnect module is also used to transmit the sampling data and its storage address corresponding to the multiple signal acquisition modules in sequence according to the preset priority order of the multiple signal acquisition modules when multiple signal acquisition modules have sampling data to be transmitted at the same time.

6. A test system for an FPGA device, characterized in that, include: The FPGA device according to any one of claims 1 to 5 is used to receive the observation signals transmitted by the module under test at different clock frequencies, sample the observation signals to obtain sampling data, and write the sampling data into an external storage chip. The host is used to read the sampled data stored in the external storage chip through the readback interface of the interconnect module in the FPGA device, and generate the actual waveform file from the read sampled data; The host computer is also used to compare the actual waveform file with the simulated waveform file of the signal to be observed, and generate test information for the FPGA device based on the comparison results.

7. The test system for FPGA devices according to claim 6, characterized in that, The host is also used to obtain the storage address range corresponding to the signal acquisition module in the FPGA device on the external storage chip, and to obtain the storage address allocated to the sampling data of the signal acquisition module. When the storage addresses of all sampled data are distributed in a continuously increasing manner within the storage address range, the sampled data are read out from the storage address range in sequence according to the storage address allocated to the sampled data. Otherwise, confirm the start and end addresses of the sampled data in the storage address range, and read the sampled data from the storage address range in sequence according to the start and end addresses of the sampled data.

8. The test system for FPGA devices according to claim 7, characterized in that, The host is also used to read sampled data from each storage address range of the external storage particle and generate independent actual waveform files respectively; wherein, the actual waveform file corresponding to the sampled data in each storage address range is used to compare with the simulation waveform file of the signal to be observed corresponding to the sampled data.

9. The test system for FPGA devices according to claim 7, characterized in that, The host is also used to take the common multiple of the clock frequencies of the sampled data in multiple signal acquisition modules as the global observation frequency, and calculate the ratio between the global observation frequency and the clock frequency of the sampled data in each signal acquisition module to obtain the interpolation multiple of the sampled data in each signal acquisition module. The host is also used to copy and interpolate the sampled data in each storage address range according to the corresponding interpolation multiple, and generate a unified actual waveform file based on all the copied and interpolated sampled data, so as to compare it with the simulation waveform files of all the signals to be observed.

10. A testing method for an FPGA device, using the FPGA device as described in any one of claims 1 to 5, characterized in that, include: The FPGA device receives signals of different clock frequencies transmitted by the module under test, samples the signals to be observed to obtain sampled data, and writes the sampled data into an external storage chip. The sampled data stored in the external memory chip is read out through the readback interface of the interconnect module in the FPGA device, and the read sampled data is used to generate an actual waveform file. The actual waveform file is compared with the simulated waveform file of the signal to be observed, and test information of the FPGA device is generated based on the comparison results.

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