Calculation power monitoring regulation and control method, device and equipment based on edge reasoning

Abstract

The invention provides a computing power monitoring regulation and control method, device and equipment based on edge reasoning, and the method comprises the steps: collecting the real-time monitoring data and stable state historical monitoring data of the start-stop transition state of a current computing power core board, and the start-stop transition state monitoring data of an adjacent computing power core board, and complementing a multi-source computing power monitoring data set; from the initial stage of the starting and stopping transition state of the current computing power core board to the stable state switching stage, the processing precision standard of the complemented transition state monitoring data is improved, computing power state analysis processing is performed on the complemented transition state monitoring data of each stage, computing power state analysis results of different stages of the transition state are obtained, and the computing power core board is obtained. And connecting with a computing power state analysis result corresponding to the current steady state historical monitoring data of the computing power core board in the multi-source computing power monitoring data set to obtain a full-cycle computing power state analysis result, and carrying out computing power regulation and control operation. According to the invention, smooth state switching of the computing power core board can be ensured.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a method, apparatus and equipment for monitoring and controlling computing power based on edge inference. Background Technology

[0002] Ruggedized edge inference laptops utilize multi-core boards as their hardware platform. Their core technology revolves around monitoring computing resources and dynamically adjusting inference tasks, aiming to maximize the computing potential of the core boards through precise computing power perception and task scheduling. Current mainstream solutions primarily collect operational data independently for each core board, allocating computing resources according to preset rules, or adjusting task load based on the historical stable state records of a single core board, using single-core state feedback to complete the adjustment. In actual operation, issues such as core board start-stop switching, fluctuations in operating conditions leading to poor state transitions, and mismatches in computing power scheduling rhythms can result in insufficient adaptability between computing power allocation and inference task requirements. This fails to fully unleash the computing power efficiency of multi-core collaboration and may even cause abnormal operation of edge inference tasks. Summary of the Invention

[0003] In view of this, the present invention provides a method, apparatus, and device for monitoring and controlling computing power based on edge inference. The technical solution of the embodiments of the present invention is implemented as follows: On one hand, embodiments of the present invention provide a computing power monitoring and control method based on edge inference. The method includes: collecting real-time monitoring data of the current computing power core board's start-stop transition state, historical monitoring data of the current computing power core board's stable state, and start-stop transition state monitoring data of adjacent computing power core boards to obtain a multi-source computing power monitoring data set; using the historical monitoring data of the current computing power core board's stable state and the start-stop transition state monitoring data of adjacent computing power core boards in the multi-source computing power monitoring data set, completing the broken data segments in the real-time monitoring data of the current computing power core board's start-stop transition state in the multi-source computing power monitoring data set, to obtain the completed transition state monitoring data; and from the current computing power core board... From the initial stage of the core board start-stop transition to the stable state switching stage, the processing accuracy standard of the completed transition state monitoring data is gradually improved. Computational power status analysis is performed on the completed transition state monitoring data of each stage to obtain the computational power status analysis results of different stages of the transition state. The computational power status analysis results of different stages of the transition state are then connected with the computational power status analysis results corresponding to the current computational power core board stable state historical monitoring data in the multi-source computational power monitoring data set to obtain the full-cycle computational power status analysis results. Based on the full-cycle computational power status analysis results, computational power regulation operations are performed to complete the connection between the current computational power core board start-stop transition state and stable state computational power regulation.

[0004] On the other hand, embodiments of the present invention provide a computing power monitoring and control device, comprising: The data acquisition module is used to collect real-time monitoring data of the current computing power core board's start-stop transition state, historical monitoring data of the current computing power core board's stable state, and start-stop transition state monitoring data of adjacent computing power core boards, to obtain a multi-source computing power monitoring data set. The data completion module is used to complete the broken data segments in the real-time monitoring data of the current computing core board's start-stop transition state in the multi-source computing power monitoring data set by using the current computing core board's stable state historical monitoring data and the start-stop transition state monitoring data of adjacent computing core boards in the multi-source computing power monitoring data set, so as to obtain the completed transition state monitoring data. The state analysis module is used to gradually improve the processing accuracy standard of the completed transition state monitoring data from the initial stage of the current computing core board start-stop transition state to the stable state switching stage. It performs computing power state analysis processing on the completed transition state monitoring data of each stage to obtain computing power state analysis results for different stages of the transition state. The result connection module is used to connect the computing power status analysis results of different stages of the transition state with the computing power status analysis results corresponding to the current computing power core board stable state historical monitoring data in the multi-source computing power monitoring data set to obtain the full-cycle computing power status analysis results. The computing power control module is used to perform computing power control operations based on the full-cycle computing power status analysis results, and to complete the connection between the current computing power core board start-stop transition state and stable state computing power control.

[0005] Thirdly, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the program to implement the steps in the above method.

[0006] This invention forms a multi-source dataset by collecting three types of cross-scenario computing power monitoring data. It employs cross-core board and cross-state data completion logic to accurately fill in the gaps in transition state monitoring data, ensuring data continuity and integrity. It adapts progressive processing precision to each stage of the transition state, improving the adaptability and accuracy of computing power status analysis at each stage. By connecting cross-state computing power analysis results, it forms a complete computing power status chain covering the entire start-up and shutdown process, providing a comprehensive basis for computing power regulation. Based on the full-cycle analysis results, it performs cross-state computing power regulation, achieving seamless connection between transition and stable states, and ensuring smooth state switching of the computing power core board. Attached Figure Description

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present invention and, together with the specification, serve to explain the technical solutions of the present invention.

[0008] Figure 1 This is a schematic diagram illustrating the implementation process of a computing power monitoring and control method based on edge inference, provided in an embodiment of the present invention.

[0009] Figure 2 This is a schematic diagram of the composition structure of a computing power monitoring and control device provided in an embodiment of the present invention.

[0010] Figure 3 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0011] This invention provides a method for monitoring and controlling computing power based on edge inference, which can be executed by the processor of a computer device. The computer device can refer to a ruggedized edge inference laptop. A ruggedized edge inference laptop is a portable computing power carrier designed for complex outdoor scenarios such as field operations and emergency response. It is equipped with multiple independent computing core boards, possessing both strong environmental adaptability and edge inference computing power output capabilities. This invention aims to maximize the computational potential of the computing core boards and ensure the continuous and stable operation of high-load edge inference tasks through precise perception and task scheduling of computing resources.

[0012] Figure 1 This is a schematic diagram illustrating the implementation process of a computing power monitoring and control method based on edge inference provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the method includes: Step S100: Collect real-time monitoring data of the current computing power core board's start-stop transition state, historical monitoring data of the current computing power core board's stable state, and start-stop transition state monitoring data of adjacent computing power core boards to obtain a multi-source computing power monitoring data set.

[0013] In the hardware platform of ruggedized edge inference laptops, the real-time monitoring data of the current computing core board's start-up and shutdown transition states is obtained by collecting data on its computing resource usage in real time during the transition phase of the core board's startup or shutdown. Specifically, for the CPU, the data collected includes its utilization rate, i.e., the proportion of time the CPU is busy at a certain moment out of the total time; the number of running threads, reflecting the number of tasks the CPU is processing simultaneously; and the load distribution of different cores, understanding the workload of each CPU core. Memory data collection includes memory usage, i.e., the amount of memory currently used by programs; memory read / write speed, reflecting the data exchange speed between memory and other components; and memory fragmentation, which relates to the effective utilization of memory. Network bandwidth data collection covers the network data transmission rate, i.e., the amount of data transmitted per unit time; the network connection packet loss rate, reflecting the reliability of network transmission; and network latency, reflecting the time it takes for data to travel from sending to receiving.

[0014] The current stable-state historical monitoring data of the computing core board consists of computing resource usage data continuously collected and stored over a period of time while the core board is operating stably. By conducting long-term statistical analysis of this data, we can identify the performance characteristics of the core board in a stable state, such as the fluctuation range of CPU utilization and the stable level of memory usage; summarize its operating patterns, such as peak and trough periods of resource usage within specific time periods; and establish common resource usage patterns.

[0015] The start-stop transition monitoring data of adjacent computing core boards refers to the computing resource usage data collected during the start-up or stop transition phase of other core boards that are physically adjacent to the current core board or logically closely related to it. Since the operating status of adjacent core boards may affect the current core board—for example, when adjacent core boards are running under high load, they may preempt shared system resources such as bus bandwidth and power supply—thereby indirectly affecting the performance of the current core board.

[0016] For CPU data acquisition, a high-precision clock mechanism can be used to sample various CPU parameters at preset time intervals, such as every 100 milliseconds. It records information such as CPU utilization and thread status at each sampling moment. For memory data acquisition, a memory monitoring chip can be connected to the memory module to monitor various memory states in real time and transmit relevant data to the data storage unit. For example, it can accurately measure the number of memory read / write operations and changes in memory usage. For network bandwidth data acquisition, network traffic monitoring devices, such as network traffic sensors, are used. This sensor captures and analyzes data packets from the network interface to obtain information such as network transmission rate and packet loss rate in real time. The collected data is stored in the laptop's local storage device using a structured database format. For example, when the laptop is running multiple complex inference tasks, for the current core board during startup, CPU, memory, and network-related data are collected at regular intervals using the above acquisition method. Simultaneously, historical data from the core board's stable operation and similar data from adjacent core boards during startup / shutdown transitions are collected, and these data are aggregated to form a multi-source computing power monitoring dataset.

[0017] Step S200: By using the historical stable state monitoring data of the current computing core board and the start-stop transition state monitoring data of adjacent computing core boards in the multi-source computing power monitoring data set, the broken data segments in the real-time start-stop transition state monitoring data of the current computing core board in the multi-source computing power monitoring data set are completed to obtain the completed transition state monitoring data.

[0018] During the collection of real-time monitoring data for the current computing power core board's start-up and shutdown transition states, various factors, such as sensor malfunctions, data transmission interruptions, or external interference, may lead to data gaps, resulting in fragmented data segments. These fragmented data segments can hinder subsequent accurate analysis of the core board's transition state performance. The current computing power core board's stable-state historical monitoring data reflects the patterns and characteristics of the core board under normal and stable operating conditions, while the start-up and shutdown transition state monitoring data of adjacent computing power core boards provides reference information under similar circumstances.

[0019] In one implementation, step S200 may specifically include the following steps S210 to S260: Step S210: Traverse the current computing power core board's stable state historical monitoring data in the multi-source computing power monitoring data set, filter the time period content of the corresponding start-stop transition process, arrange them in chronological order, mark the start-stop trigger node of each time period, and obtain the current core board's historical start-stop time period sequence.

[0020] Within the multi-source computing power monitoring dataset, the current stable-state historical monitoring data of the core board includes its operational information at different time periods. To filter out the time periods corresponding to the start-up or shutdown transition process, detailed data analysis is required. For example, key characteristics should be closely monitored, such as sudden changes in CPU utilization. A significant increase or decrease in CPU utilization within a short period likely indicates that the core board is in a start-up or shutdown transition process. Rapid increases or decreases in memory usage are also important indicators; a rapid increase or decrease in memory usage within a certain time period may also be related to the core board's start-up or shutdown transition. When these data periods that match the characteristics of a start-up or shutdown transition process are detected, they should be extracted.

[0021] The selected time periods need to be arranged in chronological order, which can be achieved using sorting algorithms, such as quicksort. The basic principle is to select a pivot element, divide the data into two parts such that all elements in the left part are less than or equal to the pivot element, and all elements in the right part are greater than or equal to the pivot element. Then, the left and right parts are recursively sorted. In this step, the sorting algorithm will sort the time period content from smallest to largest based on the timestamp information in the data, thus ensuring the data has temporal continuity.

[0022] After sorting, the start / stop trigger points for each time period need to be labeled, which can be determined through further analysis of data characteristics. For example, the point at which CPU utilization begins to rise is likely the trigger point for the core board to start; conversely, the point at which CPU utilization begins to fall is likely the trigger point for the core board to stop. Similarly, the point at which memory usage begins to change rapidly can also serve as a reference for determining start / stop trigger points. Labeling start / stop trigger points helps subsequent analysis and processing, making the data more readable and analyzable. Ultimately, these operations yield the current core board's historical start / stop time period sequence. For example, in the stable-state historical monitoring data of a laptop, by analyzing changes in CPU utilization and memory usage, all start and stop processes within the past month can be filtered out. Using a quicksort algorithm, these time periods are arranged chronologically, and the corresponding start / stop trigger points are labeled to obtain the current core board's historical start / stop time period sequence.

[0023] Step S220: Traverse the start-stop transition monitoring data of adjacent computing core boards in the multi-source computing power monitoring data set, filter the time period content of the corresponding start-stop transition process, and normalize it to eliminate the influence of hardware and load differences. Arrange them in chronological order, mark the start-stop trigger node of each time period, and obtain the normalized start-stop time period sequence of adjacent core boards.

[0024] Due to differences in hardware configuration and load conditions, adjacent computing core boards may exhibit significant data discrepancies. To eliminate the impact of these discrepancies on subsequent analysis, it is necessary to normalize the start-stop transition monitoring data of adjacent computing core boards.

[0025] First, iterate through the data and filter out the corresponding start-stop transition periods by analyzing the data's characteristics. Pay attention to abnormal changes in CPU utilization, such as large fluctuations within a short period; and drastic fluctuations in memory usage, such as sudden large increases or decreases. When these data periods that match the characteristics of the start-stop transition are detected, extract them. Normalization processing is then performed, for example, adjusting based on the maximum and minimum values ​​of the data. For each data metric, such as CPU utilization and memory usage, find its maximum and minimum values ​​among all adjacent core boards. Then, transform each data point according to the following rule: subtract the minimum value from the data point, and then divide by the difference between the maximum and minimum values. This transforms the data to a specific range, such as [0,1]. In this way, the data from different core boards are adjusted to the same scale, making them comparable.

[0026] After normalization, the filtered and normalized time period content is arranged in chronological order. Similarly, a quicksort algorithm can be used to sort the data from smallest to largest based on timestamp information. Finally, the start / stop trigger nodes for each time period are labeled, similar to step S210, by analyzing the characteristics of the data to determine these nodes. For example, when CPU utilization begins to rise and reaches a certain threshold, it is marked as a start trigger node; when CPU utilization begins to fall and falls below a certain threshold, it is marked as a stop trigger node. This yields a normalized sequence of start / stop time periods for adjacent core boards. For example, in a laptop, for the start / stop transition monitoring data of several adjacent core boards, the time periods of the start / stop transition process are filtered out, normalized, and then arranged in chronological order using a quicksort algorithm, with start / stop trigger nodes labeled to obtain a normalized sequence of start / stop time periods for adjacent core boards.

[0027] Step S230: Perform time-series alignment processing on the current core board's historical start-stop time period sequence and the adjacent core board's start-stop time period sequence to keep the start-stop node time period markers of the two sequences synchronized, align the record positions of the status change nodes, and generate a time-synchronized start-stop time period comparison sequence.

[0028] Although the current core board's historical start-stop time sequence and the adjacent core board's start-stop time sequence both contain information about the start-stop transition process, their timestamps may not be completely consistent. Time alignment processing is required to ensure that the start-stop node time markers of the two sequences can be synchronized and the recording positions of the state change nodes can be aligned.

[0029] In one implementation, step S230 may specifically include the following steps S231 to S236: Step S231: Extract the start-stop trigger node markers from the historical start-stop time sequence of the current core board, record the time position and action type corresponding to each marker, classify and arrange them according to action type, and obtain the start-stop trigger marker set of the current core board.

[0030] In the current core board's historical start / stop time sequence, the start / stop trigger node markers are key information identifying whether the core board starts or stops. By traversing this sequence and analyzing its data characteristics, nodes that meet the start / stop trigger conditions are identified, and the markers of these nodes are extracted.

[0031] For each extracted marker, its corresponding time period position and action type are recorded. The time period position can be determined by a timestamp, which precisely records the moment each event occurred. Action types are divided into start and stop. These markers are then categorized and arranged according to action type using a classification algorithm, such as bucket sort. The basic idea of ​​bucket sort is to divide the data into different buckets, each corresponding to an action type, and then sort the data within each bucket. In this way, start-type markers are grouped together, and stop-type markers are grouped together, making the data more organized and facilitating subsequent processing and analysis. This ultimately yields the current core board start / stop trigger marker set. For example, in the historical start / stop time period sequence of the current core board, by deeply analyzing the features in the data, all start and stop trigger node markers are extracted. Using the bucket sort algorithm, these markers are categorized and arranged according to action type, and the time period position and action type corresponding to each marker are recorded, resulting in the current core board start / stop trigger marker set.

[0032] Step S232: Extract the start-stop trigger node markers from the start-stop time sequence of adjacent core boards, record the time position and action type corresponding to each marker, classify and arrange them according to action type, and obtain the start-stop trigger marker set of adjacent core boards.

[0033] Similar to step S231, in the start-stop time sequence of adjacent core boards, the features in the data are analyzed by traversing the sequence to find the nodes that meet the start-stop trigger conditions and extract the labels of these nodes.

[0034] The time period position and action type corresponding to each marker are recorded. The time period position is also determined by a timestamp, and the action type is divided into start and stop. The bucket sort algorithm is used to classify and arrange these markers according to their action types, separating start and stop markers to obtain the start / stop trigger marker set for adjacent core boards. For example, in the start / stop time period sequence of adjacent core boards, detailed data analysis is performed to extract start / stop trigger node markers. These markers are then classified and arranged according to their action types using the bucket sort algorithm, and the time period position and action type of each marker are recorded to obtain the start / stop trigger marker set for adjacent core boards.

[0035] Step S233: Match the current core board start / stop trigger mark set with the normalized adjacent core board start / stop trigger mark set by action type, and calibrate the matching time period position based on the performance baseline of each core board so that the trigger marks of the same type of start / stop action correspond on the normalized time axis. Record the time period position of the calibrated matching pair to obtain the trigger mark matching pair set.

[0036] The current core board's start / stop trigger flag set is matched with the normalized start / stop trigger flag sets of adjacent core boards to determine the action type. In other words, flags with the same action type are matched between the two sets. For example, the start flag of the current core board is matched with the start flags of adjacent core boards, and the stop flag is matched with the stop flags.

[0037] During the matching process, the matching time period positions need to be calibrated based on the performance baseline of each core board. The performance baseline of each core board represents its performance under normal operating conditions. A performance baseline model is established by analyzing a large amount of data from core boards during stable operation. For example, this involves analyzing the time range required for CPU utilization to rise from its initial value to a stable value during the core board's startup process, as well as the trend of memory usage changes. Based on these performance baselines, the matching time period positions are adjusted. If a core board's startup time is found to be significantly earlier or later than other core boards, it needs to be reasonably calibrated based on its performance baseline so that the trigger markers for the same type of start / stop actions correspond on the normalized time axis. The calibrated matching time period positions need to be recorded, and these records are compiled to obtain the trigger marker matching pair set. For example, in a laptop, the start / stop trigger marker sets of the current core board and adjacent core boards are matched by action type, the matching time period positions are calibrated based on the performance baseline of each core board, and the calibrated matching time period positions are recorded to obtain the trigger marker matching pair set.

[0038] Step S234: Compare the time period position of each calibrated matching pair in the trigger marker matching pair set, calculate its relative time deviation on the normalized time axis, adjust the time period markers of the preliminary alignment sequence based on the relative time deviation, so that the relative time relationship of the matching marker pairs remains consistent, and obtain the adjusted alignment sequence.

[0039] In one implementation, step S234 may include the following steps S2341 to S2346: Step S2341: Extract the start and end time markers of each matching pair in the trigger marker matching pair set, calculate the time difference between the corresponding markers of the current core board and the adjacent core board, and organize them according to the action type to obtain the time period deviation value set.

[0040] In the set of trigger marker matching pairs, each pair contains the start and end markers for the time period of the current core board and its adjacent core board. By extracting the timestamp information of these markers, the time difference between the corresponding markers of the current core board and its adjacent core board is calculated. For example, for a matching pair of start actions, the difference between the start time of the start period of the current core board and the start time of the start period of its adjacent core board, as well as the difference between their end times, are calculated. These calculated time differences are then organized according to action type, with the time differences for start actions grouped into one category and the time differences for stop actions grouped into another, resulting in a set of time period deviation values. This set of values ​​reflects the time difference between the current core board and its adjacent core board during the start-stop transition process.

[0041] Step S2342: Traverse the adjacent time period entries of the current core board's historical start-stop time period sequence, calculate the time period interval between adjacent start-stop trigger markers, and organize them according to action type to obtain a time period interval reference value set.

[0042] The system iterates through adjacent time slot entries in the historical start-stop time slot sequence of the current core board, analyzing the data characteristics between adjacent start-stop trigger markers. The time slot interval between adjacent time slots is obtained by calculating the timestamp difference between adjacent start-stop trigger markers. For example, the time interval between the current core board start trigger marker and the next stop trigger marker is calculated. These calculated time slot intervals are then organized according to action type, grouping the time slot intervals for start actions into one group and the time slot intervals for stop actions into another group, resulting in a time slot interval reference value set. This reference value set reflects the time pattern of the current core board during normal start-stop transitions.

[0043] Step S2343: Based on the time period deviation value set and the time period interval reference value set, adjust the time period interval of adjacent trigger markers in the preliminary alignment sequence so that the adjusted interval is consistent with the reference value set, and obtain the preliminary adjusted alignment sequence.

[0044] Based on the time-period deviation value set and the time-period interval reference value set, the time-period interval of adjacent trigger markers in the initial alignment sequence is adjusted. First, the relationship between the time-period deviation value set and the time-period interval reference value set is analyzed. If the time-period deviation value set shows that the startup time of an adjacent core board is earlier than the current core board, and the time-period interval reference value set shows the normal startup time interval of the current core board, then the time-period interval of adjacent trigger markers in the initial alignment sequence needs to be appropriately adjusted. Specifically, based on the comparison results of the time-period deviation value and the time-period interval reference value, the timestamps of adjacent trigger markers are adjusted accordingly to ensure that the adjusted time-period interval is consistent with the reference value set. Through this adjustment, a preliminary adjusted alignment sequence is obtained, making the sequence more consistent with the normal operation pattern of the core board in terms of time-period intervals.

[0045] Step S2344: Traverse the initially adjusted alignment sequence, check the state change content corresponding to each start / stop trigger flag, correct entries where the state content does not match the time interval, and keep the state change related to the time interval to obtain the alignment sequence after content verification.

[0046] The initially adjusted alignment sequence is traversed, checking whether the state change content corresponding to each start / stop trigger flag matches the time interval. This is determined by analyzing the logical relationship between the state change content and the time interval. For example, if the state change content corresponding to a start trigger flag shows that the core board has fully started (i.e., CPU utilization has reached a stable high value and memory usage is also at a stable high level), but the time interval shows that the startup process has not yet ended, then the state content and time interval do not match. In this case, the state content or time interval needs to be corrected. This can be done by re-evaluating the time point of the state change or adjusting the length of the time interval to maintain a correlation between the state change and the time interval. After correction, a content-verified alignment sequence is obtained, which has better consistency between state changes and time intervals, improving the accuracy and reliability of the data.

[0047] Step S2345: Compare the content of the aligned sequence after content verification with the time period content of the start and stop time period sequence of the adjacent core board, adjust the time period marker of the sequence to improve the content matching degree, and obtain the aligned sequence with matching time period content.

[0048] The aligned sequence after content verification is compared with the time period content of the start / stop time period sequences of adjacent core boards. A comprehensive analysis of various characteristics in both sequences, such as CPU utilization, memory usage, and network bandwidth usage, is conducted. Mismatches in these characteristics between the two sequences are identified; for example, at a certain point in time, the CPU utilization of the current core board differs significantly from that of the adjacent core board. Based on the comparison results, the time period markers of the aligned sequence after content verification are adjusted. Specifically, the timestamp information of the time period markers is modified to make the two sequences exhibit more similar state changes at the same point in time. For example, if the CPU utilization of an adjacent core board begins to rise at a certain point in time, while the corresponding time period marker for the current core board shows no change, then the time period marker for the current core board is appropriately adjusted so that its CPU utilization rise time is closer to that of the adjacent core board. Through this adjustment, the matching degree of the time period content of the two sequences is improved, resulting in an aligned sequence with matching time period content.

[0049] Step S2346: Traverse the alignment sequence matching the content of the time period, check the overall continuity of the state changes, correct the conflicting content at the time period connection, and obtain the adjusted alignment sequence.

[0050] The alignment sequence matching the content of each time period is traversed to check the overall continuity of state changes. This continuity requires a smooth transition between adjacent time periods throughout the sequence, without sudden jumps or discontinuities. For example, CPU utilization should gradually increase or decrease, rather than experiencing abrupt changes between adjacent time periods. If conflicts are found at the transition points between time periods, such as sudden interruptions in state changes or data anomalies, corrections are necessary. These conflicts can be adjusted by analyzing the state changes of preceding and following time periods and considering the normal operating patterns of the core board. For instance, if at a certain time period transition point, CPU utilization suddenly drops from a high value to a low value without a reasonable transition, the state at that transition point can be interpolated based on the CPU utilization trends of preceding and following time periods to make the state change more continuous. After correction, the adjusted alignment sequence is obtained, which has more continuous state changes and more accurately reflects the start-up and shutdown transition process of the core board.

[0051] Step S235: Traverse the adjusted alignment sequence, check the continuity of state changes between adjacent start and stop trigger markers, correct the time period entries with abrupt state changes, so that the state changes of the entire sequence remain continuous, and obtain the verified alignment sequence.

[0052] The adjusted alignment sequence is traversed, with a focus on checking the continuity of state changes between adjacent start / stop trigger markers. During this process, it is observed whether the state changes conform to the normal operating patterns of the core board. If a sudden change in state is found between adjacent start / stop trigger markers, such as a significant increase or decrease in CPU utilization within a short period without a reasonable cause, then the entry for that time period needs to be corrected. Specifically, the abrupt state changes are adjusted based on the state changes in the preceding and following time periods, as well as the core board's performance baseline. Smoothing methods can be used, such as using a moving average to average the abrupt state values, making the state changes smoother. After correction, the state changes of the entire sequence remain continuous, resulting in a verified alignment sequence, which further improves the continuity of state changes.

[0053] Step S236: Associate the alignment sequence after verification with the start and stop action types of the time period marker set of the broken data segment, so that the sequence content matches the action requirements of the broken segment, and obtain a time-synchronized start and stop time period comparison sequence.

[0054] The validated alignment sequence is associated with the start and stop action types of the broken data segment time period marker set, that is, entries of the same action type in the two datasets are mapped together. For example, start entries in the validated alignment sequence are associated with start entries in the broken data segment time period marker set, and stop entries are associated with stop entries.

[0055] During the association process, it is crucial to ensure that the sequence content matches the action requirements of the broken segment. First, the action requirements of the broken data segment are analyzed to determine whether the segment is in a startup or shutdown process, and the required state changes of the core board during this process. Then, the associated entries are adjusted based on the content of the verified alignment sequence. If a startup entry in the verified alignment sequence is found to be mismatched with the startup action requirements of the broken data segment in terms of state changes—for example, if the startup entry in the sequence shows that the CPU utilization rate is rising too quickly, while the startup action requirements of the broken data segment require a smoother rise—then the entry needs to be adjusted. By adjusting the entry content, the sequence content is made to meet the action requirements of the broken segment. Finally, a timing-synchronized start-stop period comparison sequence is obtained, which is synchronized with the broken data segment in timing and matches the action requirements of the broken segment in content.

[0056] Step S240: Traverse the real-time monitoring data of the current computing core board start-stop transition state in the multi-source computing power monitoring data set, identify blank periods where all content is missing, record the start and end markers of each blank period, associate the corresponding start-stop action type, and obtain the fragmented data segment time period marker set.

[0057] The system iterates through the real-time monitoring data of the current computing power core board start-up and shutdown transition in the multi-source computing power monitoring dataset, identifying blank periods with missing content by checking the continuity of the data. During data acquisition, various reasons may cause data loss in certain periods; these periods are considered blank periods. Blank periods can be identified by analyzing the timestamp information and the continuity of data values. If data values ​​are suddenly interrupted or timestamps are discontinuous within a certain time period, then that time period is considered a blank period. For each identified blank period, its start and end markers are recorded. The start and end markers can be determined using timestamps, accurately recording the start and end times of the blank period. Simultaneously, the corresponding start-up and shutdown action type is associated, i.e., determining whether the blank period occurred during the core board startup or shutdown process. This can be determined by analyzing the data characteristics before and after the blank period. If the data before the blank period shows the core board in a low-load state, while the data after shows the core board starting to run at a high load, then it is very likely that the blank period occurred during the startup process. Organizing these records yields the set of fragmented data segment markers.

[0058] Step S250: Based on the start and stop time period comparison sequence of time synchronization, the time period content that matches the time period mark set of the broken data segment is filled in the blank interval covered by the time period mark set of the broken data segment one time period at a time, so that the filled content is continuous with the state changes of the preceding and following time periods, and the preliminary completed transition state monitoring data is obtained.

[0059] Based on the time period content matching the time period marker set of the broken data segment in the time-synchronized start-stop time period comparison sequence, the blank intervals covered by the time period marker set of the broken data segment are filled in time period by time. The matching time period content is the time period content with the same start-stop action type as the broken data segment. For example, if the broken data segment is a blank time period in the start-up process, then the time period content of the start-up process in the time-synchronized start-stop time period comparison sequence is selected for filling.

[0060] During the filling process, it's crucial to ensure continuity between the filled content and the state changes of the preceding and following time periods. Specifically, first analyze the state change trends of the preceding and following time periods, such as the upward or downward trend of CPU utilization and the trend of memory usage changes. Then, based on these trends, select appropriate time periods for filling from the time-synchronized start-stop time period comparison sequence. During filling, ensure that the timestamps of the filled content are consistent with the timestamps of the preceding and following time periods, so that the overall data after filling has continuity in both time and state. For example, if the CPU utilization of the preceding and following time periods shows a gradual upward trend, then the CPU utilization of the filled content should also be set reasonably according to this trend, and seamlessly connected in time with the preceding and following time periods. Through this time-by-time filling, preliminary complete transitional monitoring data is obtained, which to some extent compensates for the missing fragmented data segments.

[0061] Step S260: Traverse the initially completed transitional monitoring data, check the connection between state changes of adjacent time period entries, correct the content conflicts at the time period connection, so that the state changes of the entire transitional monitoring data remain continuous, and obtain the completed transitional monitoring data.

[0062] The initial completion of the transitional monitoring data is traversed to check the continuity of state changes between adjacent time periods. While the initial completion process strives to ensure continuity between the filled content and the preceding and following time periods, some minor issues may still exist, leading to less smooth state changes between adjacent time periods and content conflicts. For example, at a certain time period transition, CPU usage might suddenly jump from one value to another without a reasonable transition process; or memory usage might fluctuate unreasonably between adjacent time periods.

[0063] When content conflicts are found at the transition points between time periods, corrections are necessary. The correction method involves adjusting the conflicting portions by considering the state change trends of the preceding and following time periods and the normal operating patterns of the core board. Interpolation can be used to calculate a reasonable intermediate state value based on the state values ​​of the preceding and following time periods, resulting in a smoother state transition. For example, if the CPU utilization suddenly jumps from 20% to 50% at a certain time period transition, a reasonable CPU utilization value at the transition point can be calculated using linear interpolation, such as 30% or 35%, and then the state at that transition point can be corrected. After correcting the content conflicts at all time period transitions, the state changes of the entire transition monitoring data remain continuous, resulting in complete transition monitoring data.

[0064] Step S300: From the initial stage of the current computing core board start-stop transition state to the stable state switching stage, gradually improve the processing accuracy standard of the completed transition state monitoring data, and perform computing power status analysis processing on the completed transition state monitoring data of each stage to obtain the computing power status analysis results of different stages of the transition state.

[0065] The current startup / shutdown transition of the computing core board can be divided into an initial stage, an intermediate transition stage, and a stable state switching stage. At each stage, the core board's computing resource utilization and state changes exhibit different characteristics. Therefore, it is necessary to gradually improve the processing accuracy standards of the completed transition state monitoring data from the initial stage to the stable state switching stage.

[0066] In the initial stage, the core board is just starting up or stopping, and its state changes relatively slowly. At this time, the processing precision standards can be relatively low. For example, when collecting data, a relatively long sampling interval can be used, such as collecting data once every 1 second. When analyzing the data, the main focus is on the basic state change trends of the core board, such as whether the CPU utilization rate has started to rise or fall, and whether there are significant changes in memory usage.

[0067] As the transition process progresses and enters the intermediate conversion phase, the core board's state changes gradually accelerate. At this point, it's necessary to improve processing accuracy. Regarding data acquisition, the sampling interval should be shortened, such as collecting data every 0.5 seconds, to capture state changes more promptly. When analyzing data, it's crucial to focus not only on the trend of state changes but also on the frequency and magnitude of these changes. For example, calculating the frequency of CPU utilization changes over a short period and the magnitude of changes in memory usage.

[0068] During the steady-state transition phase, the core board is about to enter a stable state, and state changes become more drastic. Further improvements in processing accuracy are needed. The sampling interval can be shortened to collect data every 0.1 seconds to accurately record the details of state changes. When analyzing the data, it is crucial to thoroughly analyze whether the core board's various performance indicators have met the standards for a stable state, such as whether CPU utilization has stabilized within a specific range and whether memory usage no longer exhibits significant fluctuations.

[0069] The completed transition state monitoring data for each stage undergoes separate computing power status analysis. This means that different analysis methods and indicators are used to analyze the data based on the characteristics of each stage. For example, in the initial stage, the analysis can focus on the changing trend of CPU utilization and the initial state of memory usage; in the intermediate transition stage, the analysis can focus on the frequency and magnitude of state changes; and in the stable state transition stage, the analysis can focus on whether the core board's performance indicators have reached the standards for a stable state. Through these analyses, the computing power status analysis results for different stages of the transition state are obtained.

[0070] In one implementation, step S300 may include the following steps S310 to S360: Step S310: Divide the time intervals of the initial stage, intermediate transition stage and stable state switching stage of the current computing power core board start-stop transition state, mark the start and end point markers of each stage, associate the corresponding start-stop action type, and obtain the transition state stage time interval marker set.

[0071] To define the different stages of the current computing core board's startup and shutdown transition, it's necessary to make judgments based on certain characteristics in the data. The time intervals for different stages can be determined by analyzing changes in indicators such as CPU utilization and memory usage in the completed transition monitoring data. During startup, when CPU utilization begins to rise, but the rate of increase is slow, and memory usage also increases slowly, it can be considered the initial stage. For example, CPU utilization starts at 10%, but only rises to 20% in the first 10 seconds, and memory usage also increases slowly from a low value. When the rate of increase in CPU utilization accelerates and the state changes more drastically, such as when CPU utilization rises from 20% to 50% in the next 5 seconds, and memory usage also increases rapidly, the intermediate transition stage begins. When CPU utilization approaches a stable value, and various performance indicators tend to stabilize, such as CPU utilization stabilizing at around 80% for a period of time, and memory usage also stabilizing at a high level, the stable state transition stage begins.

[0072] The judgment method is similar during the stopping process. When CPU utilization begins to decrease, but the rate of decrease is slow, and memory usage also decreases slowly, it is the initial stage. When the rate of decrease in CPU utilization accelerates and the state changes drastically, it enters the intermediate transition stage. When CPU utilization approaches a stable low level and all performance indicators stabilize, it enters the steady-state switching stage.

[0073] For each defined stage, its start and end time markers are labeled. These markers can be determined using timestamps, accurately recording the start and end times of each stage. Simultaneously, the corresponding start / stop action type is associated, determining whether the stage occurs during startup or shutdown. These records are then compiled to obtain the transitional stage time period marker set. For example, in a laptop, based on changes in CPU usage and memory consumption in the completed transitional monitoring data, the time periods for the initial stage, intermediate transition stage, and stable state switching stage of the current core board's start / stop transition are divided. The start and end time markers for each stage are labeled, and the corresponding start / stop action type is associated to obtain the transitional stage time period marker set.

[0074] Step S320: Extract all contents of the corresponding transitional stage time period marker set from the completed transitional state monitoring data, classify and arrange them according to stage, record the state change content of each stage, and obtain the transitional state monitoring data subsequence for each stage.

[0075] Based on the transition phase time stamp set, extract all content corresponding to each phase from the completed transition monitoring data. Timestamp information can be used to determine which data belongs to which phase. For example, if the transition phase time stamp set shows the initial phase's start time as t1 and end time as t2, then extract the data with timestamps between t1 and t2 from the completed transition monitoring data; this data constitutes the initial phase content.

[0076] The extracted data needs to be categorized and arranged according to stages: data from the initial stage is grouped together, data from the intermediate transition stage is grouped together, and data from the stable state transition stage is grouped together. For each stage, the state changes are recorded. For example, in the initial stage, the upward trend of CPU utilization and the slow increase in memory usage are recorded; in the intermediate transition stage, the rapid rise or fall of CPU utilization and the drastic changes in memory usage are recorded; in the stable state transition stage, the stability of CPU utilization and memory usage is recorded. Through these operations, subsequences of transitional state monitoring data for each stage are obtained. For example, in a laptop, based on the transitional state stage time period marker set, the content corresponding to each stage is extracted from the completed transitional state monitoring data, categorized and arranged by stage, and the state changes for each stage are recorded to obtain subsequences of transitional state monitoring data for each stage.

[0077] Step S330: Analyze the state change frequency of the transition state monitoring data subsequences at each stage, and set the sampling interval rules for each stage accordingly, so that the sampling interval in the initial stage corresponds to low frequency change, the interval in the middle stage corresponds to gradual frequency change, and the interval in the switching stage corresponds to high frequency change, thus obtaining the stage sampling rule set.

[0078] Analyzing the frequency of state changes in the transition state monitoring data subsequences at each stage, that is, determining the frequency of state changes by analyzing the state changes in the data. For example, in the initial stage, state changes are relatively slow and the frequency is low; in the intermediate transition stage, state changes gradually accelerate and the frequency shows a gradual trend; in the steady-state transition stage, state changes are more drastic and the frequency is high.

[0079] Based on the frequency of state changes, sampling interval rules are set for each stage. In the initial stage, due to the low frequency of state changes, the sampling interval can be relatively large to reduce the workload of data collection. For example, a sampling interval of 1 second can be set, so that collecting data once every second can meet the monitoring needs of state changes in the initial stage. In the intermediate transition stage, the sampling interval needs to be adjusted according to the gradual frequency of state changes so that the sampling can capture the details of state changes. A dynamic adjustment method can be adopted, gradually shortening the sampling interval as the frequency of state changes increases. For example, initially setting the sampling interval to 0.8 seconds, as the frequency of state changes accelerates, the sampling interval is shortened to 0.6 seconds. In the steady-state transition stage, due to the high frequency of state changes, the sampling interval needs to be relatively small to record state changes more accurately. A sampling interval of 0.1 seconds can be set to ensure that rapid state changes can be captured in a timely manner. Through these settings, a stage sampling rule set is obtained. For example, in the notebook, the frequency of state changes in the transition state monitoring data subsequences of each stage is analyzed, and the sampling interval rules for each stage are set according to the frequency to obtain the stage sampling rule set.

[0080] In one implementation, step S330 may specifically include the following steps S331 to S336: Step S331: Traverse the initial stage transition state monitoring data subsequence, count the time interval between adjacent state change nodes, calculate the average length of the interval, analyze the low-frequency distribution characteristics of state changes, and obtain the initial stage state frequency distribution description.

[0081] The initial stage transition state monitoring data subsequence is traversed to identify state change nodes. State change nodes are points in time where certain characteristics of the data undergo significant changes, such as a sudden increase or decrease in CPU utilization or a rapid increase or decrease in memory usage. The time interval between adjacent state change nodes is calculated, i.e., the time difference between two adjacent state change nodes. For example, if the timestamp of the first state change node is t1 and the timestamp of the second state change node is t2, then the time interval between them is t2-t1. These time intervals are summarized, and their average length is calculated. By analyzing the distribution of these time intervals, the low-frequency distribution characteristics of state changes can be understood. For example, if the time intervals are long and relatively uniform, it indicates that the state change frequency is low and relatively stable. These analysis results are then organized to obtain a description of the initial stage state frequency distribution.

[0082] Step S332: Based on the initial stage state frequency distribution description, set a sampling rule with an interval length equal to the average interval so that the sampling entries cover the main state change nodes in the initial stage, thus obtaining the initial stage sampling rule.

[0083] Because the frequency of state changes is low in the initial stage, and the average interval can reflect the general pattern of state changes, a sampling rule can be set where the interval length is equal to the average interval. For example, if the initial stage state frequency distribution shows that the average time interval between adjacent state change nodes is 3 seconds, then the sampling interval is set to 3 seconds. Such a sampling rule ensures that the sampling entries cover the main state change nodes in the initial stage. During the sampling process, data is sampled according to the set interval length to ensure that key information about state changes is captured.

[0084] Step S333: Traverse the transition state monitoring data subsequence of the intermediate transition stage, count the time interval between adjacent state change nodes, calculate the gradual shrinking trend of the interval, analyze the gradual frequency characteristics of state changes, and obtain the state frequency distribution description of the intermediate stage.

[0085] Traverse the transition state monitoring data subsequences during the intermediate transition phase to identify state change nodes. Statistically analyze the time intervals between adjacent state change nodes and their changing trends. During the intermediate transition phase, state changes gradually accelerate, and the time intervals typically show a gradual decreasing trend. For example, initially, the time interval between adjacent state change nodes is 2 seconds, but over time, the time interval gradually decreases to 1 second, 0.8 seconds, and so on. By analyzing the gradual decreasing trend of the time intervals, we can understand the gradual frequency characteristics of state changes, such as the rate and magnitude of the time interval decrease. Organize these analysis results to obtain a description of the intermediate phase state frequency distribution.

[0086] Step S334: Based on the description of the intermediate stage state frequency distribution, set a sampling rule in which the interval length gradually decreases as the frequency increases, so that the sampling entries cover the detailed state changes of the intermediate stage, and obtain the sampling rule for the intermediate transition stage.

[0087] In one implementation, step S334 may specifically include the following steps S3341 to S3346: Step S3341: Traverse the transition state monitoring data subsequence of the intermediate transition stage, mark the time period position of all state change nodes, arrange them in chronological order, record the state type corresponding to each node, and obtain the intermediate stage state change node set.

[0088] The process involves traversing the transitional monitoring data subsequence of the intermediate transition phase to identify state change nodes. By analyzing data characteristics such as sudden changes in CPU utilization and rapid changes in memory usage, the location of these state change nodes is determined. The time period positions of these nodes are marked, which can be determined using timestamps. The marked nodes are then arranged in chronological order using a sorting algorithm, such as bubble sort, based on the timestamp information, sorting the nodes from smallest to largest. The basic principle of bubble sort is to compare adjacent elements; if they are in the wrong order, they are swapped, and this process is repeated until the entire sequence is ordered. After sorting, the state type corresponding to each node is recorded. The state type can be determined based on data characteristics, such as an increase or decrease in CPU utilization or an increase or decrease in memory usage. These records are then compiled to obtain the set of state change nodes for the intermediate phase. For example, in the transitional monitoring data subsequence of the intermediate transition phase, by analyzing the data to identify state change nodes, using bubble sort to arrange them in chronological order, and recording the state type of each node, the set of state change nodes for the intermediate phase is obtained.

[0089] Step S3342: Calculate the time interval between adjacent nodes in the intermediate stage state change node set, arrange them in chronological order, analyze the gradual shrinking trend of the interval value, and obtain a description of the intermediate stage interval change trend.

[0090] Calculate the time interval between adjacent nodes in the intermediate stage state change node set, which is equivalent to subtracting the timestamp of the previous node from the timestamp of the subsequent node. For example, if the timestamp of the first node is t1 and the timestamp of the second node is t2, then the time interval between them is t2-t1. Arrange these calculated time intervals in chronological order, using the bubble sort algorithm. After arrangement, analyze the trend of the interval values. During the intermediate transition stage, the time intervals usually show a gradual decreasing trend. By observing the numerical changes in the time intervals, such as decreasing from 2 seconds to 1.5 seconds, and then to 1 second, analyze the speed and magnitude of this decrease.

[0091] Step S3343: Based on the description of the intermediate stage interval change trend, set a sampling interval sequence from large to small, so that each sampling interval corresponds to an interval in the interval change trend, and obtain a preliminary intermediate sampling interval sequence.

[0092] Based on the description of the intermediate stage interval change trend, a sampling interval sequence is set. Since the frequency of state changes gradually increases during the intermediate transition stages, the sampling intervals need to be set from large to small. First, based on the description of the intermediate stage interval change trend, the range of time interval changes is divided into multiple intervals. Then, a corresponding sampling interval is set for each interval, so that the sampling interval gradually decreases as the interval changes. Arranging these sampling intervals in descending order yields a preliminary intermediate sampling interval sequence. This sequence can adaptively adjust the sampling interval according to the change in state change frequency, ensuring that detailed state changes in the intermediate stages can be captured.

[0093] Step S3344: Associate the initial intermediate sampling interval sequence with the intermediate stage state change node set, check the node coverage corresponding to the sampling interval, adjust the interval length so that the sampling entries cover the main detail change nodes, and obtain the adjusted intermediate sampling interval sequence.

[0094] The initial intermediate sampling interval sequence is associated with the set of intermediate stage state change nodes, that is, sampling intervals are mapped to state change nodes. For each sampling interval, the coverage of its corresponding state change nodes is checked. For example, it is checked whether the main state change nodes are included within a certain sampling interval. If the node coverage corresponding to a certain sampling interval is found to be unsatisfactory, such as not covering important state change nodes, then the interval length needs to be adjusted. The adjustment method is to appropriately increase or decrease the interval length based on the distribution of the intermediate stage state change node set and the description of the intermediate stage interval change trend. For example, if a sampling interval is found to be too long, causing some important state change nodes to be missed, then this sampling interval is shortened. After adjustment, the adjusted intermediate sampling interval sequence is obtained, which can better cover the main detailed change nodes of the intermediate stage, improving the sampling effectiveness.

[0095] Step S3345: Traverse the adjusted intermediate sampling interval sequence, associate the corresponding time period positions, mark the start and end points of each sampling interval, and obtain the intermediate sampling rule time period label set.

[0096] The adjusted intermediate sampling interval sequence is traversed, and each sampling interval is associated with a corresponding time period position. The time period position can be determined by timestamps. Based on the timestamp information of the intermediate stage state change node set, the start and end times corresponding to each sampling interval are determined. The start and end segments of each sampling interval are marked, so that the sampling interval has a clear time range. These marked time period positions and start and end segments are organized together to obtain the intermediate sampling rule time period label set.

[0097] Step S3346: Associate the intermediate sampling rule time period marker set with the intermediate transition phase transition state monitoring data subsequence, verify the matching degree between the sampling entries and the state change nodes, correct the interval length for insufficient matching degree, and obtain the intermediate transition phase sampling rules.

[0098] The intermediate sampling rule time period marker set is associated with the transitional state monitoring data subsequence of the intermediate transition phase, that is, the sampling interval is mapped to the state changes in the data. The matching degree between sampling items and state change nodes is verified to see if the sampling interval can accurately capture state change nodes. For example, it is checked whether the expected state change nodes are included within each sampling interval. If insufficient matching is found, such as a sampling interval not covering important state change nodes or covering too many invalid nodes, the interval length needs to be adjusted. The adjustment method is to adjust the interval length according to the actual situation of the transitional state monitoring data subsequence of the intermediate transition phase and the distribution of the intermediate phase state change node set. For example, if a sampling interval is found to be too long, causing some important state change nodes to be missed, then the sampling interval is shortened; if a sampling interval is found to be too short, containing too many invalid nodes, then the sampling interval is appropriately extended. After adjustment, the sampling rule for the intermediate transition phase is obtained. This rule can ensure a high matching degree between sampling items and state change nodes, providing a reliable sampling basis for accurately analyzing the state changes in the intermediate transition phase.

[0099] Step S335: Traverse the transition state monitoring data subsequence of the steady-state switching phase, count the time interval between adjacent state change nodes, calculate the minimum length of the interval, analyze the high-frequency distribution characteristics of state changes, and obtain the state frequency distribution description of the switching phase.

[0100] Traverse the transition state monitoring data subsequence during the steady-state transition phase to identify state change nodes. Calculate the time intervals between adjacent state change nodes and determine the minimum length of these intervals. During the steady-state transition phase, state changes occur frequently, and time intervals are typically short. For example, the time interval between adjacent state change nodes might be between 0.1 and 0.5 seconds; calculate the minimum of these intervals, such as 0.1 seconds. Analyzing the distribution of these time intervals reveals the high-frequency distribution characteristics of state changes. For instance, short and concentrated time intervals indicate high frequency and drastic changes in state. Organize these analysis results to obtain a description of the state frequency distribution during the transition phase.

[0101] Step S336: Based on the state frequency distribution description of the switching phase, set a sampling rule with an interval length equal to the minimum interval so that the sampling entries cover all state change nodes in the switching phase, and obtain the sampling rule for the steady-state switching phase; integrate the sampling rules of the three phases to obtain the phase sampling rule set.

[0102] Based on the state frequency distribution description of the switching phase, sampling rules are set. Since the state change frequency is high during the steady-state switching phase, and the minimum interval reflects the fastest rate of state change, a sampling rule with an interval length equal to the minimum interval can be set. For example, if the state frequency distribution description of the switching phase shows that the minimum time interval between adjacent state change nodes is 0.1 seconds, then the sampling interval is set to 0.1 seconds. This sampling rule ensures that the sampling entries cover all state change nodes during the switching phase. During sampling, data is sampled according to the set interval length to ensure that all key information about state changes is captured.

[0103] By integrating the sampling rules for the initial stage, intermediate transition stage, and steady-state switching stage, a set of stage sampling rules is obtained. This set is applicable to the entire start-stop transition state of the core board and can adaptively adjust the sampling interval according to the characteristics of different stages, providing comprehensive sampling guidance for accurately analyzing the core board's performance in the transition state.

[0104] Step S340: Extract the content of the transition state monitoring data subsequences of each stage according to the stage sampling rule set, select the corresponding time period entries according to the sampling interval, record the state change content of each sampling entry, and obtain the monitoring data after sampling of each stage.

[0105] According to the stage sampling rule set, content extraction is performed on the transition state monitoring data subsequences of each stage. For the initial stage, according to the initial stage sampling rules, the corresponding time period entries are selected from the initial stage transition state monitoring data subsequences at a set sampling interval, such as every 3 seconds. For the intermediate transition stage, according to the intermediate transition stage sampling rules, the corresponding time period entries are selected at a dynamically adjusted sampling interval, such as gradually shortening from 0.8 seconds to 0.6 seconds based on the state change frequency. For the stable state transition stage, according to the stable state transition stage sampling rules, the corresponding time period entries are selected at an interval length equal to the minimum interval, such as every 0.1 seconds.

[0106] After selecting time periods, record the status changes for each sampled item. These changes include changes in CPU utilization, increases or decreases in memory usage, and fluctuations in network bandwidth usage. For example, for each sampled item, record whether CPU utilization increased or decreased, and by how much; whether memory usage increased or decreased, and by how much; and whether network bandwidth usage remained stable or fluctuated, and the range of fluctuation. Through these operations, monitoring data after sampling at each stage is obtained. This data is the result of sampling and filtering, focusing more on the key status changes of the core board at each stage.

[0107] Step S350: Traverse the monitoring data after sampling at each stage, sort out the temporal relationship of state changes, record the state type and change direction of each sampling item, organize them into a structured sequence according to the stage, and obtain the computing power state analysis results of each stage.

[0108] By analyzing the timestamp information of the sampling entries, the order of state changes is determined. For example, the state change corresponding to the earlier sampling entry is listed first, and the state change corresponding to the later sampling entry is listed later. The state type and direction of change for each sampling entry are recorded. The state type can be determined based on the characteristics in the data, such as an increase or decrease in CPU utilization, an increase or decrease in memory usage, etc. The direction of change can be divided into positive and negative changes, such as an increase in CPU utilization being a positive change and a decrease being a negative change.

[0109] These records are organized into stages to obtain a structured sequence. For the initial stage, the sampled items are arranged chronologically, and the state type and direction of change for each item are recorded, resulting in an ordered sequence. The same process is repeated for intermediate transition stages and stable-state switching stages. This structured sequence makes the data more organized, facilitating subsequent analysis and processing. Ultimately, the computing power state analysis results for each stage are obtained. For example, in a notebook, the monitoring data after sampling at each stage is traversed, the temporal relationship of state changes is analyzed, state types and directions of change are recorded, and the data is organized into a structured sequence by stage to obtain the computing power state analysis results for each stage.

[0110] Step S360: Connect the computing power status analysis results of the initial stage, the intermediate transition stage, and the stable state switching stage in chronological order, check the continuity of state changes at the stage transition points, correct any conflicts, and obtain the computing power status analysis results for different stages of the transition state.

[0111] The results of the initial computing power status analysis, the intermediate transition stage computing power status analysis, and the stable state switching stage computing power status analysis are concatenated in chronological order to ensure data continuity over time. Data merging methods can be used to connect the structured sequences of the three stages sequentially.

[0112] Check the continuity of state changes at the transition points between stages to see if the transitions between adjacent stages are smooth. For example, at the transition point between the initial stage and the intermediate transition stage, check whether the changes in indicators such as CPU utilization and memory usage are consistent. If conflicts are found at the transition point, such as sudden interruptions in state changes or data anomalies, corrections are required. This can be done by analyzing the state changes between the preceding and following stages, combined with the normal operating rules of the core board, to adjust the conflicting content at the transition point. For example, if there is a sudden and large jump in CPU utilization at the transition point from the initial stage to the intermediate transition stage, while it should normally be a gradual transition, then the state changes at this transition point need to be reassessed, and the state changes can be made continuous through interpolation or data adjustment.

[0113] After correction, the computing power status analysis results for different stages of the transition state are obtained. This result is a complete and continuous description of the computing power status of the core board at different stages of the start-up and shutdown transition state, providing a comprehensive and accurate data foundation for subsequent analysis and control. For example, in a laptop, the computing power status analysis results of each stage are concatenated in chronological order, the continuity of state changes at the stage transition points is checked, and any conflicts are corrected to obtain the computing power status analysis results for different stages of the transition state.

[0114] Step S400: Connect the computing power status analysis results of different stages of the transition state with the computing power status analysis results corresponding to the historical monitoring data of the current computing power core board in the stable state in the multi-source computing power monitoring data set to obtain the full-cycle computing power status analysis results.

[0115] In one implementation, step S400 may specifically include the following steps S410 to S460: Step S410: Traverse the computing power status analysis results of different stages of the transition state, locate the last time period entry of the stable state switching stage, record the status content of the last time period entry and the node marker of entering the stable state, and obtain the computing power status record at the end of the switching stage.

[0116] The algorithm iterates through the computing power status analysis results of different transition stages to find the last time period entry in the stable state transition phase. This can be determined by timestamp information, specifically the entry with the largest timestamp. The status content of the last time period entry is recorded, including CPU utilization, memory usage, and network bandwidth usage. Simultaneously, the node marker indicating the entry into the stable state is recorded. This marker can be determined by analyzing data characteristics, such as CPU utilization reaching a stable value with minimal fluctuations over a period of time, and memory usage no longer showing significant changes.

[0117] Step S420: Traverse the historical monitoring data of the current computing power core board in the multi-source computing power monitoring data set to find the computing power status analysis results corresponding to the stable state of the historical monitoring data, locate the first time period entry of the stable state, record the status content of the first time period entry and the node marker of entering the stable state, and obtain the initial computing power status record of the stable state.

[0118] Within the multi-source computing power monitoring dataset, the analysis results of the computing power status corresponding to the historical monitoring data of the current computing power core board in a stable state are traversed. By comparing the timestamps of each entry, the earliest entry in the stable state is located. The status content of this earliest entry is recorded, specifically covering aspects such as CPU utilization, memory usage, and network bandwidth usage. Simultaneously, the node marker indicating the entry into a stable state must be clearly recorded, which can be determined through further in-depth analysis of data characteristics. For example, when it is found that CPU utilization remains stable within a specific, small fluctuation range over multiple consecutive sampling periods, memory usage also remains stable for a long time without significant increases or decreases, and the network bandwidth transmission rate remains stable within a reasonable error range, the time points corresponding to these characteristics can be used as node markers indicating the entry into a stable state.

[0119] Step S430: Compare the content of the end computing power status record of the switching phase with the initial computing power status record of the stable state, analyze the differences in the status content at the stable state node marker, record the content and location of the differences in the status content, and obtain a description of the differences in the content of the connecting node.

[0120] Regarding CPU utilization, compare the specific values ​​and fluctuations at the stable-state node markers. For memory usage, examine its size and trend at the node markers. For network bandwidth usage, compare metrics such as transmission rate and packet loss rate. This comprehensive comparison analyzes the differences in state content at the stable-state node markers. When recording these differences, record the specific details. For example, if CPU utilization is 85% at the end of the switching phase, while it's 78% at the beginning of the stable state, record this difference. Similarly, if memory usage fluctuates at the end of the switching phase, while it's completely stable at the beginning of the stable state, record this fluctuation as well. Simultaneously, accurately record the location of these differences, using timestamps to pinpoint their exact moment within the entire data sequence.

[0121] In one implementation, step S430 may specifically include the following steps S431-S436: Step S431: Extract all status content entries from the end computing power status record of the switching phase, classify and arrange them according to status type, record the time period position of each entry, and obtain the end content set of the switching phase.

[0122] The end-of-switch computing power status records are processed to extract all status content entries. These entries cover different aspects such as CPU utilization, memory usage, and network bandwidth usage. They are then categorized and arranged according to status type: CPU utilization-related entries are grouped together, memory usage-related entries are grouped together, and network bandwidth usage-related entries are grouped together. For each categorized entry, its corresponding time period is accurately recorded, and a timestamp is used to determine the specific time point of the entry within the entire end-of-switch record. These categorized and arranged entries with recorded time periods are then aggregated to form the end-of-switch content set.

[0123] Step S432: Extract all state content entries from the stable initial computing power state record, classify and arrange them according to state type, record the time period position of each entry, and obtain the stable initial content set.

[0124] Similar to step S431, the initial stable-state computing power status record is processed. All status entries are extracted, covering aspects such as CPU utilization, memory usage, and network bandwidth usage. Next, entries are categorized by status type, grouping similar entries together. For each entry, its time period position is recorded, using a timestamp to specify its exact time point in the initial stable-state record. Finally, these categorized entries with recorded time periods are integrated to obtain the initial stable-state content set.

[0125] Step S433: Match the switching end content set with the stable initial content set according to the state type, and set the matching tolerance based on the reasonable range of state value changes, so that items of the same type of state content within the tolerance range form a corresponding relationship, and obtain the content matching pair set.

[0126] The switching end content set and the stable initial content set are matched according to state type, that is, the CPU utilization entries, memory usage entries, and network bandwidth usage entries in the two sets are matched with each other. During the matching process, a matching tolerance is set based on the reasonable range of change in state values. Different state types have different reasonable ranges of change. For example, under normal circumstances, the change in CPU utilization from one stage to another will not be too drastic. A reasonable range of change can be determined based on historical data and the performance characteristics of the core board, and this range serves as the matching tolerance. When entries of the same type of state content are within this tolerance range, they are considered to be matched, and a correspondence is obtained. Organizing all these matching correspondences together yields the content matching pair set.

[0127] Step S434: Traverse the content matching pair set, analyze the state content differences of each matching pair, record the specific manifestations of the differences, organize the difference content according to the state type, and obtain the content difference description set.

[0128] In one implementation, step S434 may include the following steps S4341-S4346: Step S4341: Traverse the content matching pair set, extract the state content entries of each matching pair, record the state change process in the entries, arrange them in chronological order, and obtain the matching pair state process set.

[0129] For each matching pair, extract its state content entries. These entries record in detail the state changes before and after entering the stable state node. Record the state change process within each entry, such as how CPU utilization changes from the end of the switching phase to the initial value of the stable state, and how memory usage increases or decreases during this process. Arrange these state change processes in chronological order using a sorting algorithm, such as insertion sort. The basic idea of ​​insertion sort is to insert a data item into the appropriate position in an already sorted sequence, ensuring that the sequence remains ordered after insertion.

[0130] Step S4342: Compare and match the state contents before and after the state process set, analyze the differences between the start and end contents of the state change, record the specific contents of the differences, and obtain the description of the differences between the start and end of the state.

[0131] The matching process sets compare the state content of each matching pair before and after the transition. For CPU utilization, compare its specific values ​​and fluctuation range at the beginning of the state change (end of the switching phase) and the end (initial of the stable state); for memory usage, observe its initial and final values ​​and trends; for network bandwidth usage, compare the transmission rate, packet loss rate, and other indicators at the beginning and end. Through this comparison, analyze the differences between the beginning and end of the state change and record the specific details of the differences. If memory usage fluctuates slightly at the beginning but stabilizes completely at the end, record this fluctuation.

[0132] Step S4343: Compare and match the intermediate state content of the state process set, analyze the continuity difference of state changes, record the specific manifestations of the difference, and obtain a description of the continuity difference of the state.

[0133] Observe the continuity of changes in various state parameters during the transition from the end of the switching phase to the beginning of the steady state. For CPU utilization, check for sudden, large jumps or discontinuous changes during the process; for memory usage, check if the increases and decreases are smooth; for network bandwidth usage, analyze whether the fluctuations in transmission rate and packet loss rate are reasonable. Through this analysis, identify the differences in the continuity of state changes and record the specific manifestations of these differences in detail. For example, if CPU utilization suddenly drops by 10% at a certain point in the middle, while it should normally transition gradually and smoothly, record this discontinuous change. Record all these differences to obtain a description of the differences in state continuity.

[0134] Step S4344: Classify the state start-end difference description and state continuity difference description according to state type, organize the difference content of the same type, and obtain the classification difference description set.

[0135] The differences in state start / end and state continuity are categorized according to state type. Differences involving CPU utilization are grouped together, those involving memory usage are grouped together, and those involving network bandwidth usage are grouped together. Within each category, the differences are organized, removing duplicate information to make the differences of the same type clearer and more organized. These categorized and organized contents are then summarized to obtain the categorized difference description set.

[0136] Step S4345: Traverse the classification difference description set, count the occurrence frequency of each type of difference, arrange the difference types according to the frequency, and obtain the difference frequency sorted set.

[0137] The system iterates through the set of categorized differences, counting the frequency of each type of difference. For example, it counts the frequency of differences in CPU utilization, memory usage, and network bandwidth usage. Then, it sorts the difference types according to their frequency, with more frequent differences listed first and less frequent differences listed later. This sorting yields a frequency-ranked set of differences, which visually reflects which types of differences are more common at the point where the system enters a stable state.

[0138] Step S4346: Integrate the classification difference description set and the difference frequency ranking set, arrange the difference content and occurrence frequency according to the difference type, and obtain the content difference description set.

[0139] The categorical difference description set and the difference frequency ranking set are integrated. Based on the difference type, the difference content in the categorical difference description set is associated with the corresponding frequency in the difference frequency ranking set. For example, for the difference type of CPU utilization, its specific difference content is mapped to its frequency of occurrence. Then, the difference content and frequency are arranged according to the difference type, making the entire description set clearer and more concise. The final result is a content difference description set that comprehensively displays the state content differences at the stable state node marker and the frequency of occurrence of various difference types.

[0140] Step S435: Traverse the content difference description set, record the time period position corresponding to each difference content, associate it with the node markers that have entered the stable state, and obtain the difference position marker set.

[0141] The set of content difference descriptions is traversed, and for each difference, its corresponding time period position is accurately recorded, using a timestamp to determine the specific time point of the difference within the entire data sequence. Simultaneously, these differences are associated with the markers of nodes entering a stable state, clarifying whether these differences occurred before or after this crucial node of entering a stable state. All these records are then integrated to obtain the set of difference location markers.

[0142] Step S436: Integrate the content difference description set and the difference location marker set, arrange the difference content and corresponding location in chronological order, and obtain the content difference description of the connecting node.

[0143] The content difference description set and the difference location marker set are integrated to map the difference content to its corresponding time period location. Then, this integrated information is arranged in chronological order, so that the difference content and its corresponding location are presented sequentially. This yields the content difference description of the connecting node, which fully demonstrates the state content differences at the point of entering the stable state node marker and the specific time and location of these differences.

[0144] Step S440: Based on the description of the differences in the content of the connecting nodes, correct the state content of the end computing power state record of the switching phase so that the corrected content is consistent with the initial content of the initial computing power state record of the stable state, and obtain the adjusted end computing power state record of the switching phase.

[0145] Based on the detailed information provided in the description of differences in the connecting nodes, the status content of the computing power status record at the end of the switching phase is corrected. Each difference recorded in the description of differences in the connecting nodes is analyzed and adjusted. If a difference is found between the CPU utilization at the end of the switching phase and the CPU utilization at the beginning of the stable state, and this difference exceeds a reasonable range, the CPU utilization at the end of the switching phase can be adjusted based on the CPU utilization at the beginning of the stable state and the reasonable trend of state changes. Similar methods are used to correct other status content such as memory usage and network bandwidth usage. Through these correction operations, the status content of the computing power status record at the end of the switching phase is made consistent with the initial content of the computing power status record at the beginning of the stable state, resulting in the adjusted computing power status record at the end of the switching phase.

[0146] Step S450: Associate the adjusted end-of-phase computing power status record with the initial stable-state computing power status record to generate computing power status records covering the transition period from the transition state to the stable state. Organize these records into a structured sequence to obtain the computing power status analysis results for the transition period between the transition state and the stable state.

[0147] The adjusted end-of-phase computing power status record and the initial stable-state computing power status record are correlated. Following a chronological order, the data from the two records are integrated to generate a complete computing power status record covering the transition period from the transition state to the stable state. Within this record, the data must maintain temporal continuity and logical consistency. This record is then organized into a structured sequence, using data structures such as linked lists or arrays, to make the data more organized and facilitate subsequent analysis and processing.

[0148] Step S460: Connect the computing power status analysis results of different stages of the transition state, the computing power status analysis results of the transition state and the stable state transition section, and the computing power status analysis results corresponding to the current computing power core board stable state historical monitoring data in the multi-source computing power monitoring data set in chronological order, check the continuity of state changes at the connection points of each part, correct the connection conflicts, and obtain the full-cycle computing power status analysis results.

[0149] The computing power status analysis results from different stages of the transition state, the transition state and stable state transition phase, and the current computing power core board stable state historical monitoring data from the multi-source computing power monitoring dataset are concatenated in chronological order. A data merging algorithm can be used to connect these three parts of data sequentially according to time.

[0150] After the interconnection is completed, check the continuity of state changes at the junctions of each part. Examine the junctions between different stages of the transition state, the transition between the transition and stable states, and the junctions between the analysis results corresponding to historical monitoring data of the transition and stable states. Check whether the changes in state parameters such as CPU utilization, memory usage, and network bandwidth usage are smooth. If conflicts are found at the junctions, such as sudden jumps in state parameters or data anomalies, corrections are required. By analyzing the state changes of the preceding and following parts and combining this with the normal operating rules of the core board, adjustments are made to the conflicting content, such as using interpolation or reasonable inference based on historical data. After correction, the full-cycle computing power state analysis results are obtained, comprehensively reflecting the changes in the computing power state of the core board throughout the entire operating cycle.

[0151] Step S500: Perform computing power regulation operations based on the full-cycle computing power status analysis results to complete the connection between the current computing power core board start-stop transition state and stable state computing power regulation.

[0152] In one implementation, step S50 may specifically include the following steps S510-S560: Step S510: Traverse the full-cycle computing power status analysis results, locate the time period entries of the transitional and stable states, record the adjustment requirements of the state changes in the period, and arrange them in time order to obtain the description of the computing power control requirements of the transition period.

[0153] The full-cycle computing power status analysis results are traversed, and time period entries connecting the transitional and stable states are located using timestamps and state change characteristics. The state changes within these time periods, such as changes in parameters like CPU utilization, memory usage, and network bandwidth usage, are analyzed. Adjustment requirements for these state changes are recorded. If significant fluctuations in CPU utilization are observed during the transition period, affecting the core board's stability, adjustments are recorded to stabilize it within a reasonable range. Similarly, unreasonable increases or decreases in memory usage during the transition period are also recorded. These adjustment requirements are arranged chronologically to make the entire description clearer and more organized, ultimately yielding a description of the computing power control requirements for the transition period.

[0154] Step S520: Based on the adjustment requirements in the description of computing power control requirements of the connecting segment, generate corresponding instructions for adjusting the computing power operation status, mark the execution time and adjustment content of each instruction, and obtain a preliminary computing power control instruction sequence.

[0155] Based on the adjustment requirements described in the transition segment's computing power control needs, corresponding instructions for adjusting the computing power operating status are generated. For requirements requiring CPU utilization adjustment, instructions to reduce or increase CPU utilization are generated; for requirements requiring memory usage adjustment, instructions to optimize memory allocation or release memory are generated. During instruction generation, the execution time period for each instruction is marked. Based on the time information in the full-cycle computing power status analysis results, the specific time period in which the instruction should be executed is determined. Simultaneously, the adjustment content of the instructions is clearly marked, specifying which status parameter the instruction targets for adjustment and the specific goals and methods of adjustment. These instructions are arranged according to the order of their execution time periods to obtain a preliminary computing power control instruction sequence.

[0156] In one implementation, step S520 may specifically include the following steps S521-S526: Step S521: Traverse the adjustment requirements in the description of computing power regulation requirements of the connection segment, arrange them in time order, record the state change type corresponding to each requirement, and obtain the set of regulation requirement types.

[0157] The adjustment requirements in the description of computing power regulation needs for the transition segment are traversed and arranged in chronological order. Simultaneously, the state change type corresponding to each requirement is analyzed and accurately recorded. For example, a requirement to adjust CPU utilization is recorded as "CPU Utilization Adjustment"; a requirement to adjust memory usage is recorded as "Memory Usage Adjustment". All these state change types are then compiled to obtain the regulation requirement type set.

[0158] Step S522: Based on the set of control demand types, generate adjustment actions corresponding to the state change types, record the specific content of each action, and obtain the control action set.

[0159] Based on the set of regulation needs, corresponding adjustment actions are generated for different types of state changes. For the "CPU utilization adjustment" type, actions such as adjusting the number of CPU cores enabled and adjusting task scheduling strategies can be generated; for the "memory usage adjustment" type, actions such as clearing the cache and optimizing memory allocation algorithms can be generated. Detailed records are kept for each action, including the execution method and the expected effect.

[0160] Step S523: Associate the set of control actions with the time period markers in the description of the computing power control requirements of the connecting segment, mark the execution time period of each action, and obtain the action time period association set.

[0161] In one implementation, step S523 may include the following steps S5231-S5236: Step S5231: Traverse the description of computing power regulation requirements for the connecting segments, extract all time period markers, arrange them in chronological order, record the requirement content corresponding to each marker, and obtain the set of requirement time period markers.

[0162] The process involves iterating through the description of computing power adjustment requirements for each transition segment, extracting all time period markers, and representing these time period markers with timestamps. These time period markers are then arranged in chronological order, using a sorting algorithm such as bubble sort. During the arrangement process, the requirement content corresponding to each marker is recorded, clarifying the state adjustment requirements needed for that time period. For example, for a specific timestamp marker, the corresponding requirement is recorded as adjusting CPU utilization.

[0163] Step S5232: Traverse the set of control actions, extract the state change type corresponding to each action, classify and arrange them by type, record the specific content of each action, and obtain the action type classification set.

[0164] The set of control actions is traversed, and for each action, its corresponding state change type is extracted. For example, the action of adjusting the number of CPU cores enabled has a state change type of "CPU utilization adjustment". These actions are then categorized and arranged according to their state change types, grouping actions of the same type together. Simultaneously, the detailed content of each action is recorded, including the specific operation steps and the expected effect.

[0165] Step S5233: Match the action type classification set with the demand time period mark set according to the state change type, so that the time period mark of the same type of demand corresponds to the same type of action, and obtain the action time period matching set.

[0166] The action type classification set and the demand time period marker set are matched according to the type of state change. That is, the time period markers of the "CPU utilization adjustment" type in the demand time period marker set are matched with the actions of the "CPU utilization adjustment" type in the action type classification set, and the time period markers of the "memory usage adjustment" type are matched with the actions of the "memory usage adjustment" type in the action type classification set. Through this matching, a correspondence is formed between the time period markers of the same type of demand and the same type of action.

[0167] Step S5234: Traverse the action time period matching set, check the matching status of action content and requirement content, correct entries with mismatched action content, and obtain the action time period matching set with matching content.

[0168] The action-time matching pair set is traversed, checking the match between the action content and the requirement content in each pair. For example, for a time period marker indicating a requirement to reduce CPU usage, the corresponding action is checked to see if it actually reduces CPU usage. If a mismatch is found between the action content and the requirement content—for example, if the expected effect of the action does not match the goal of the requirement—the entry is corrected. A suitable action can be selected again, or the specific content of the action can be adjusted to match the requirement content. After correction, the action-time matching pair set with matching content is obtained.

[0169] Step S5235: Traverse the action time period matching set that matches the content, check the continuity between the action execution time period and the required time period, correct the entries with discontinuous time periods, and obtain the action time period matching set with continuous time periods.

[0170] The system iterates through the action time period matching pairs, checking the continuity between the action execution time and the demand time period in each pair. It examines whether the action execution time is consecutive to the demand time and whether there are any discontinuous time periods. If a discontinuity is found between the action execution time and the demand time period (e.g., the demand time period ends at a certain point, but the action execution time begins much later), the entry is corrected. The timestamps of the action execution time periods can be adjusted to make them continuous with the demand time period. After correction, a set of action time period matching pairs with continuous time periods is obtained.

[0171] Step S5236: Arrange the action time period matching pairs with consecutive time periods in chronological order, record the action content and execution time period of each matching pair, and obtain the action time period association set.

[0172] To arrange the set of matching pairs of consecutive action time periods in chronological order, a sorting algorithm, such as insertion sort, can be used. After sorting, the action content and execution time period of each matching pair are recorded. These records are then compiled together to obtain the action time period association set. This clearly shows when each action should be executed and its specific content.

[0173] Step S524: Convert the action time period association set into an instruction format, record the action content and execution time of each instruction, and obtain a preliminary draft of the computing power control instruction sequence.

[0174] The action time period association set is converted into an instruction format. Following the core board's control protocol and instruction specifications, each action content and execution time period is transformed into a specific instruction. For example, adjusting the number of CPU cores enabled is converted into a corresponding control instruction, including specific parameters and opcodes. The action content and execution time period of each instruction are recorded to ensure that the instructions accurately convey the control intent and execution time. These instructions are then organized according to the chronological order of their execution times to obtain a preliminary draft of the computing power control instruction sequence.

[0175] Step S525: Traverse the initial draft of the preliminary computing power control instruction sequence, check the matching of the execution time of the instructions with the demand time, correct instructions with mismatched time periods, and obtain a preliminary instruction sequence with matching time periods.

[0176] The initial draft of the preliminary computing power control instruction sequence is iterated through to check the match between the execution time of each instruction and the demand time. The execution time of the instruction is compared with the time the demand occurs; if a mismatch is found, such as an instruction's execution time being too early or too late, the instruction is corrected. This can be achieved by adjusting the instruction's execution timestamp to match the demand time. After correction, a preliminary instruction sequence with matching time periods is obtained.

[0177] Step S526: Traverse the preliminary instruction sequence matched by the time period, check the matching of the adjustment content of the instruction with the demand content, correct the instructions with mismatched content, and obtain the preliminary computing power control instruction sequence.

[0178] The initial instruction sequence for time-period matching is traversed to check the matching between the adjustment content of each instruction and the required content. The specific operation and expected effect of the instruction are examined to see if they align with the target requirements. If a mismatch is found, such as the adjustment direction of the instruction being opposite to the required adjustment direction, the instruction is corrected. The instruction content can be rewritten to accurately meet the requirements. After correction, the initial computing power control instruction sequence is obtained.

[0179] Step S530: Associate the initial computing power control instruction sequence with the control protocol of the current computing power core board, adjust the instruction format to be consistent with the protocol requirements, and obtain a computing power control instruction sequence with a compatible format.

[0180] The initial computing power control command sequence is associated with the control protocol of the current computing power core board. Different core boards have different control protocols, which have specific requirements for command format, encoding method, parameter settings, etc. Based on the core board's control protocol, the format of each command in the initial computing power control command sequence is adjusted. For example, the opcode of the command is modified, necessary prefixes or suffixes are added, and the order of parameters is adjusted to ensure that the command format is completely consistent with the protocol requirements. After such adjustments, a computing power control command sequence with a compatible format is obtained, ensuring that the commands can be correctly recognized and executed by the core board.

[0181] Step S540: Send the format-adapted computing power control instruction sequence one by one to the control interface of the current computing power core board, record the sending time of each instruction and the receiving feedback of the control interface, and obtain the instruction execution feedback record.

[0182] The system sends each instruction in the format-adapted computing power control instruction sequence to the control interface of the current computing core board. During the transmission process, the transmission time of each instruction is precisely recorded and represented by a timestamp. Simultaneously, it waits for feedback from the control interface and records the reception status of each instruction, such as whether it was successfully received and the time of reception.

[0183] Step S550: Based on the instruction execution period in the instruction execution feedback record, continuously collect the current computing power operation status of the computing power core board, and arrange them in time order to obtain the real-time record of the adjusted computing power operation.

[0184] Based on the instruction execution time period in the instruction execution feedback record, the computing power operation status of the current computing core board is continuously collected within the corresponding time period of instruction execution. Using the same sensors and monitoring tools as previously collected data, parameters such as CPU utilization, memory usage, and network bandwidth usage are collected. The collected data is arranged in chronological order, using a sorting algorithm such as merge sort. After sorting, a real-time record of the adjusted computing power operation is obtained, intuitively displaying the real-time changes in the core board's operating status after executing the adjustment instructions.

[0185] Step S560: Compare the real-time record of the adjusted computing power operation with the stable computing power status record in the full-cycle computing power status analysis results, analyze the matching situation, adjust the subsequent computing power control instructions to improve the matching degree, and complete the connection between the current computing power core board start-stop transition state and stable state computing power control.

[0186] The real-time records of the adjusted computing power operation are compared with the stable-state computing power records in the full-cycle computing power status analysis results. Parameters such as CPU utilization, memory usage, and network bandwidth usage are compared one by one to analyze the content matching between the two. It is checked whether the adjusted computing power operation status is close to the ideal stable state. If significant differences are found, such as the adjusted CPU utilization still fluctuating greatly while the CPU utilization in the stable-state record is stable, then the subsequent computing power adjustment instructions need to be adjusted. Based on the comparative analysis results, the adjustment targets and methods of the instructions are revised or modified to make the adjusted computing power operation status closer to the stable state, improving the matching degree.

[0187] Based on the foregoing embodiments, this invention provides a computing power monitoring and control device. The units and modules included in the device can be implemented by a processor in a computer device; of course, they can also be implemented by specific logic circuits. In the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0188] Figure 2 This is a schematic diagram of the composition structure of a computing power monitoring and control device provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the computing power monitoring and control device 200 includes: The data acquisition module 210 is used to collect real-time monitoring data of the current computing power core board's start-stop transition state, historical monitoring data of the current computing power core board's stable state, and start-stop transition state monitoring data of adjacent computing power core boards, to obtain a multi-source computing power monitoring data set. The data completion module 220 is used to complete the broken data segments in the real-time monitoring data of the current computing core board start-stop transition state in the multi-source computing power monitoring data set by using the current computing core board stable state historical monitoring data and the start-stop transition state monitoring data of adjacent computing core boards in the multi-source computing power monitoring data set, so as to obtain the completed transition state monitoring data. The state analysis module 230 is used to gradually improve the processing accuracy standard of the completed transition state monitoring data from the initial stage of the current computing core board start-stop transition state to the stable state switching stage. It performs computing power state analysis processing on the completed transition state monitoring data of each stage to obtain computing power state analysis results for different stages of the transition state. The result connection module 240 is used to connect the computing power status analysis results of different stages of the transition state with the computing power status analysis results corresponding to the current computing power core board stable state historical monitoring data in the multi-source computing power monitoring data set to obtain the full-cycle computing power status analysis results. The computing power control module 250 is used to perform computing power control operations based on the full-cycle computing power status analysis results, and to complete the connection between the current computing power core board start-stop transition state and stable state computing power control. The descriptions of the apparatus embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. In some embodiments, the functions or modules included in the apparatus provided by the present invention can be used to perform the methods described in the method embodiments above. For technical details not disclosed in the apparatus embodiments of the present invention, please refer to the descriptions of the method embodiments of the present invention for understanding.

[0189] Figure 3 A hardware entity diagram of a computer device provided in an embodiment of the present invention, such as... Figure 3 As shown, the hardware entity of the computer device 1000 includes a processor 1001 and a memory 1002, wherein the memory 1002 stores a computer program that can run on the processor 1001, and the processor 1001 executes the program to implement the steps in the method of any of the above embodiments.

[0190] The memory 1002 stores computer programs that can run on the processor. The memory 1002 is configured to store instructions and applications that can be executed by the processor 1001. It can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 1001 and various modules in the computer device 1000. It can be implemented by flash memory or random access memory (RAM).

[0191] When the processor 1001 executes the program, it implements the steps of the edge inference-based computing power monitoring and control method described above. The processor 1001 typically controls the overall operation of the computer device 1000.

Claims

1. A computing power monitoring and control method based on edge inference, characterized in that, The method includes: Collect real-time monitoring data of the current computing power core board's start-stop transition state, historical monitoring data of the current computing power core board's stable state, and start-stop transition state monitoring data of adjacent computing power core boards to obtain a multi-source computing power monitoring data set; By using the historical stable state monitoring data of the current computing core board and the start-stop transition state monitoring data of adjacent computing core boards in the multi-source computing power monitoring data set, the broken data segments in the real-time start-stop transition state monitoring data of the current computing core board in the multi-source computing power monitoring data set are completed to obtain the completed transition state monitoring data. From the initial stage of the current computing core board start-stop transition state to the stable state switching stage, the processing accuracy standard of the completed transition state monitoring data is gradually improved. Computing power status analysis processing is performed on the completed transition state monitoring data of each stage to obtain computing power status analysis results of different stages of the transition state. The computing power status analysis results at different stages of the transition state are combined with the computing power status analysis results corresponding to the historical monitoring data of the current computing power core board in the multi-source computing power monitoring data set to obtain the full-cycle computing power status analysis results. Based on the full-cycle computing power status analysis results, computing power regulation operations are performed to complete the connection between the current computing power core board start-stop transition state and stable state computing power regulation.

2. The computing power monitoring and control method based on edge inference as described in claim 1, characterized in that, The method involves using the historical stable-state monitoring data of the current computing core board and the start-stop transition-state monitoring data of adjacent computing core boards in the multi-source computing power monitoring data set to complete the broken data segments in the real-time start-stop transition-state monitoring data of the current computing core board in the multi-source computing power monitoring data set, thereby obtaining the completed transition-state monitoring data, including: Traverse the current computing power core board stable state historical monitoring data in the multi-source computing power monitoring data set, filter the time period content of the corresponding start-stop transition process, arrange them in chronological order, mark the start-stop trigger node of each time period, and obtain the current core board historical start-stop time period sequence; Traverse the adjacent computing core board start-stop transition monitoring data in the multi-source computing power monitoring data set, filter the time period content of the corresponding start-stop transition process, and normalize it to eliminate the influence of hardware and load differences. Arrange it in chronological order, mark the start-stop trigger node of each time period, and obtain the normalized adjacent core board start-stop time period sequence. The current core board's historical start-stop time period sequence is time-aligned with the adjacent core board's start-stop time period sequence to keep the start-stop node time period markers of the two sequences synchronized, align the recording positions of the nodes with status changes, and generate a time-synchronized start-stop time period comparison sequence. Traverse the current computing core board start-stop transition real-time monitoring data in the multi-source computing power monitoring data set, identify blank periods where all content is missing, record the start and end markers of each blank period, associate the corresponding start-stop action type, and obtain the fragmented data segment time period marker set; Based on the time period content that matches the time period marker set of the broken data segment in the start and stop time period comparison sequence of the time synchronization, the blank interval covered by the time period marker set of the broken data segment is filled in time period by time, so that the filled content is continuous with the state changes of the preceding and following time periods, and preliminary complete transition state monitoring data is obtained. The preliminary completed transitional monitoring data is traversed, the connection between state changes of adjacent time period entries is checked, and the content conflicts at the time period connection are corrected to ensure that the state changes of the entire transitional monitoring data remain continuous, thus obtaining the completed transitional monitoring data.

3. The computing power monitoring and control method based on edge inference as described in claim 2, characterized in that, The step of performing time-series alignment processing on the current core board's historical start / stop time period sequence and the adjacent core board's start / stop time period sequence, keeping the start / stop node time period markers of the two sequences synchronized, aligning the recording positions of the status change nodes, and generating a time-synchronized start / stop time period comparison sequence includes: Extract the start / stop trigger node markers from the historical start / stop time sequence of the current core board, record the time position and action type corresponding to each marker, classify and arrange them according to action type, and obtain the current core board start / stop trigger marker set; Extract the start-stop trigger node markers from the start-stop time sequence of the adjacent core boards, record the time position and action type corresponding to each marker, classify and arrange them according to action type, and obtain the start-stop trigger marker set of the adjacent core boards. The current core board start / stop trigger mark set is matched with the normalized adjacent core board start / stop trigger mark set by action type, and the matching time period position is calibrated based on the performance baseline of each core board so that the trigger marks of the same type of start / stop action correspond on the normalized time axis. The time period position of the calibrated matching pair is recorded to obtain the trigger mark matching pair set. By comparing the time period position of each calibrated matching pair in the trigger marker matching pair set, the relative temporal deviation is calculated on the normalized time axis. Based on the relative temporal deviation, the time period markers of the preliminary alignment sequence are adjusted to keep the relative temporal relationship of the matching marker pairs consistent, thus obtaining the adjusted alignment sequence. Traverse the adjusted alignment sequence, check the continuity of state changes between adjacent start and stop trigger markers, correct the time period entries with abrupt state changes, so that the state changes of the entire sequence remain continuous, and obtain the verified alignment sequence. By associating the verified alignment sequence with the start and stop action types of the time segment marker set of the broken data segment, the sequence content is made to match the action requirements of the broken segment, thus obtaining a time-synchronized start and stop time segment comparison sequence.

4. The computing power monitoring and control method based on edge inference as described in claim 3, characterized in that, The process involves comparing the time period positions of each calibrated matching pair in the trigger marker matching pair set, calculating their relative temporal deviation on the normalized time axis, and adjusting the time period markers of the initial alignment sequence based on the relative temporal deviation to maintain consistency in the relative temporal relationship of the matching marker pairs, resulting in an adjusted alignment sequence, including: Extract the start and end time markers of each matching pair in the trigger marker matching pair set, calculate the time difference between the corresponding markers of the current core board and the adjacent core board, and organize them according to the action type to obtain the time period deviation value set; Traverse the adjacent time period entries of the current core board's historical start-stop time period sequence, calculate the time period interval between adjacent start-stop trigger markers, and organize them according to action type to obtain a time period interval reference value set; Based on the time period deviation value set and the time period interval reference value set, the time period interval of adjacent trigger markers in the preliminary alignment sequence is adjusted so that the adjusted interval is consistent with the reference value set, thus obtaining the preliminary adjusted alignment sequence; Traverse the initially adjusted alignment sequence, check the state change content corresponding to each start / stop trigger flag, correct entries where the state content does not match the time interval, and keep the state change related to the time interval to obtain the alignment sequence after content verification. By comparing the content-verified alignment sequence with the time period content of the adjacent core board start-stop time period sequence, the time period markers of the sequence are adjusted to improve the content matching degree, and an alignment sequence with matching time period content is obtained. Traverse the alignment sequence that matches the content of the time period, check the overall continuity of state changes, correct conflicting content at the time period junctions, and obtain the adjusted alignment sequence.

5. The computing power monitoring and control method based on edge inference as described in claim 1, characterized in that, The process gradually improves the processing accuracy standard of the completed transition state monitoring data from the initial stage of the current computing core board start-stop transition state to the stable state switching stage. Computing power state analysis processing is performed on the completed transition state monitoring data at each stage to obtain computing power state analysis results for different stages of the transition state, including: Divide the time intervals of the initial stage, intermediate transition stage and stable state switching stage of the current computing power core board start-stop transition state, mark the start and end point of each stage, associate the corresponding start-stop action type, and obtain the transition state stage time interval mark set; Extract all contents of the corresponding transitional phase time period marker set from the completed transitional monitoring data, classify and arrange them according to phase, record the state change content of each phase, and obtain the transitional monitoring data subsequence of each phase; Analyze the frequency of state change in the transition state monitoring data subsequences at each stage, and set corresponding sampling interval rules for each stage so that the sampling interval in the initial stage corresponds to low-frequency changes, the interval in the middle stage corresponds to gradual frequency changes, and the interval in the switching stage corresponds to high-frequency changes, thus obtaining a set of stage sampling rules. According to the stage sampling rule set, the content of each stage transition state monitoring data subsequence is extracted, the corresponding time period entries are selected according to the sampling interval, the state change content of each sampling entry is recorded, and the monitoring data after each stage sampling is obtained. By traversing the monitoring data after sampling at each stage, sorting out the temporal relationship of state changes, recording the state type and direction of change of each sampling item, and organizing them into a structured sequence according to the stage, the computing power state analysis results of each stage are obtained. The computing power status analysis results of the initial stage, the intermediate transition stage, and the stable state switching stage are concatenated in chronological order. The continuity of state changes at the stage transition points is checked, and any conflicts are corrected to obtain the computing power status analysis results for different stages of the transition state.

6. The computing power monitoring and control method based on edge inference as described in claim 5, characterized in that, The analysis of the state change frequency of the transition state monitoring data subsequence at each stage corresponds to setting sampling interval rules for each stage. This ensures that the initial stage sampling interval corresponds to low-frequency changes, the intermediate stage interval corresponds to gradual frequency changes, and the switching stage interval corresponds to high-frequency changes, resulting in a set of stage sampling rules, including: Traverse the initial stage transition state monitoring data subsequence, count the time interval between adjacent state change nodes, calculate the average length of the interval, analyze the low-frequency distribution characteristics of state changes, and obtain a description of the initial stage state frequency distribution. Based on the initial stage state frequency distribution description, a sampling rule with an interval length equal to the average interval is set so that the sampling entries cover the main state change nodes in the initial stage, thus obtaining the initial stage sampling rule. Traverse the transition state monitoring data subsequence of the intermediate transition stage, count the time interval between adjacent state change nodes, calculate the gradual shrinking trend of the interval, analyze the gradual frequency characteristics of state changes, and obtain a description of the intermediate stage state frequency distribution. Based on the intermediate stage state frequency distribution description, a sampling rule is set to gradually reduce the interval length as the frequency increases, so that the sampling entries cover the detailed state changes of the intermediate stage, thus obtaining the intermediate transition stage sampling rule. Traverse the transition state monitoring data subsequence of the steady-state switching phase, count the time interval between adjacent state change nodes, calculate the minimum length of the interval, analyze the high-frequency distribution characteristics of state changes, and obtain a state frequency distribution description of the switching phase. Based on the state frequency distribution description of the switching phase, a sampling rule with an interval length equal to the minimum interval is set so that the sampling entries cover all state change nodes in the switching phase, thus obtaining the sampling rule for the steady-state switching phase; the sampling rules of the three phases are integrated to obtain the phase sampling rule set.

7. The computing power monitoring and control method based on edge inference as described in claim 6, characterized in that, Based on the description of the intermediate stage state frequency distribution, a sampling rule is set to gradually decrease the interval length as the frequency increases, so that the sampling entries cover the detailed state changes of the intermediate stage, resulting in the sampling rule for the intermediate transition stage, including: Traverse the intermediate transition state monitoring data subsequence, mark the time period position of all state change nodes, arrange them in chronological order, record the state type corresponding to each node, and obtain the intermediate stage state change node set; Calculate the time interval between adjacent nodes in the intermediate stage state change node set, arrange them in chronological order, analyze the gradual decreasing trend of the interval value, and obtain a description of the intermediate stage interval change trend. Based on the description of the intermediate stage interval change trend, a sampling interval sequence from large to small is set so that each sampling interval corresponds to an interval in the interval change trend, thus obtaining a preliminary intermediate sampling interval sequence. The preliminary intermediate sampling interval sequence is associated with the intermediate stage state change node set, the node coverage corresponding to the sampling interval is checked, and the interval length is adjusted so that the sampling entries cover the main detail change nodes to obtain the adjusted intermediate sampling interval sequence. Traverse the adjusted intermediate sampling interval sequence, associate the corresponding time period positions, and mark the start and end points of each sampling interval to obtain the intermediate sampling rule time period label set; The intermediate sampling rule time period marker set is associated with the intermediate transition phase transition state monitoring data subsequence, the matching degree between the sampling entries and the state change nodes is verified, the interval length of insufficient matching degree is corrected, and the sampling rules of the intermediate transition phase are obtained.

8. The computing power monitoring and control method based on edge inference as described in claim 1, characterized in that, The process of connecting the computing power status analysis results of different stages of the transition state with the computing power status analysis results corresponding to the current computing power core board stable state historical monitoring data in the multi-source computing power monitoring data set to obtain the full-cycle computing power status analysis results includes: By traversing the computing power status analysis results of different stages of the transition state, locating the last time period entry of the stable state switching stage, recording the status content of the last time period entry and the node marker for entering the stable state, the computing power status record at the end of the switching stage is obtained. Traverse the historical monitoring data of the current computing power core board in the multi-source computing power monitoring data set to find the computing power status analysis results corresponding to the current computing power core board in the stable state, locate the first time period entry in the stable state, record the status content of the first time period entry and the node marker for entering the stable state, and obtain the initial computing power status record of the stable state. Compare the content of the end computing power status record of the switching phase with the initial computing power status record of the stable state, analyze the differences in the status content at the stable state node marker, record the content and location of the differences in the status content, and obtain a description of the differences in the content of the connecting node. Based on the description of the differences in the content of the connecting nodes, the state content of the end computing power state record of the switching phase is corrected so that the corrected content is consistent with the starting content of the initial computing power state record of the stable state, thus obtaining the adjusted end computing power state record of the switching phase. The adjusted end-of-phase computing power status record is associated with the initial stable-state computing power status record to generate computing power status records covering the transition period from the transition state to the stable state. These records are then organized into a structured sequence to obtain the computing power status analysis results for the transition period between the transition state and the stable state. The computing power status analysis results of different stages of the transition state, the computing power status analysis results of the transition state and the stable state connection segment, and the computing power status analysis results corresponding to the current computing power core board stable state historical monitoring data in the multi-source computing power monitoring data set are connected in chronological order. The continuity of state changes at the connection points of each part is checked, and the connection conflicts are corrected to obtain the full-cycle computing power status analysis results. The process involves comparing the end-of-phase computing power state record with the initial stable-state computing power state record, analyzing the differences in state content at the stable-state node marker, recording the content and location of these differences, and obtaining a description of the differences in the transition node content, including: Extract all status content entries from the end computing power status record of the switching phase, classify and arrange them according to status type, record the time period position of each entry, and obtain the end content set of the switching phase; Extract all state content entries from the stable initial computing power state record, classify and arrange them according to state type, record the time period position of each entry, and obtain the stable initial content set; The switching end content set is matched with the stable initial content set according to the state type, and a matching tolerance is set based on the reasonable range of state value changes, so that items of the same type of state content within the tolerance range form a corresponding relationship, thus obtaining a content matching pair set; Traverse the set of content matching pairs, analyze the differences in state content for each matching pair, record the specific manifestations of the differences, organize the differences by state type, and obtain a set of content difference descriptions. Traverse the content difference description set, record the time period position corresponding to each difference content, associate it with the node marker that has entered the stable state, and obtain the difference position marker set; By integrating the content difference description set and the difference location marker set, and arranging the difference content and corresponding location in chronological order, the content difference description of the connecting node is obtained.

9. A computing power monitoring and control device, characterized in that, include: The data acquisition module is used to collect real-time monitoring data of the current computing power core board's start-stop transition state, historical monitoring data of the current computing power core board's stable state, and start-stop transition state monitoring data of adjacent computing power core boards, to obtain a multi-source computing power monitoring data set. The data completion module is used to complete the broken data segments in the real-time monitoring data of the current computing core board start-stop transition state in the multi-source computing power monitoring data set by using the current computing core board stable state historical monitoring data and the start-stop transition state monitoring data of adjacent computing core boards in the multi-source computing power monitoring data set, so as to obtain the completed transition state monitoring data. The state analysis module is used to gradually improve the processing accuracy standard of the completed transition state monitoring data from the initial stage of the current computing core board start-stop transition state to the stable state switching stage. The module performs computing power state analysis processing on the completed transition state monitoring data of each stage to obtain computing power state analysis results for different stages of the transition state. The result connection module is used to connect the computing power status analysis results of different stages of the transition state with the computing power status analysis results corresponding to the current computing power core board stable state historical monitoring data in the multi-source computing power monitoring data set to obtain the full-cycle computing power status analysis results. The computing power control module is used to perform computing power control operations based on the full-cycle computing power status analysis results, and to complete the connection between the current computing power core board start-stop transition state and stable state computing power control.

10. A computer device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1 to 9.

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