Cache coherency control method, coherency directory, and processor chip

By using multiple directory entries to record the distribution information of cache line copies in a multi-core processor system, recording the address label only in the first directory entry and the path pointer in the second directory entry, the problem of directory entry bit width increasing with the number of cores in traditional cache coherence protocols is solved, achieving hardware overhead savings and system performance improvement.

CN122019414BActive Publication Date: 2026-07-24LOONGSON TECH CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
LOONGSON TECH CORP
Filing Date
2026-04-09
Publication Date
2026-07-24

AI Technical Summary

Technical Problem

In multi-core processor systems, as the number of cores increases to hundreds or even thousands, the directory entry bit width of traditional cache coherency protocols increases linearly with the number of cores, resulting in excessive hardware overhead and affecting system performance.

Method used

Multiple directory entries are used to record the distribution information of cache line copies. The address label is recorded only in the first directory entry and the path pointer is recorded in the second directory entry, which reduces the width of the directory entries. The address label is obtained by pointing to the first directory entry through the path pointer.

Benefits of technology

While maintaining a low width of a single directory entry, it accurately represents the location of cache line copies in many-core scenarios, saving hardware overhead and improving system performance.

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Abstract

Embodiments of the present application provide a cache consistency control method, a consistency directory and a processor chip. The method comprises: in response to a first core first accessing a target cache line, allocating a first directory entry in a consistency directory; the first directory entry is used to record an address tag of the target cache line and a first sharer; the first sharer comprises the first core; in response to a second core accessing the target cache line, allocating a second directory entry in the consistency directory; the second directory entry is used to record a target way pointer and a second sharer; the target way pointer points to the first directory entry; the second sharer comprises the second core; the number of the second core is greater than or equal to 1. Embodiments of the present application can accurately indicate the cache line copy position under the many-core situation while keeping a low single directory entry width, thereby saving hardware overhead and improving system performance.
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