Data link initialization methods, devices, electronic equipment, storage media, and chips

Abstract

This disclosure relates to the field of chip technology, and in particular to a data link initialization method, apparatus, electronic device, storage medium, and chip. The method includes: acquiring the transmission protocols supported by a local chip and the transmission protocols supported by a remote chip; determining, based on a first protocol capability, a second protocol capability, and pre-obtained physical link training results between the local and remote chips, whether a preset single-protocol pass-through condition is met between the local and remote chips; and, if the single-protocol pass-through condition is met, establishing a pass-through data path for the transmission protocol corresponding to the single-protocol pass-through condition. This disclosure helps improve the data link establishment speed, shorten the data link initialization time, and help eliminate redundant processing delays and significant resource overhead caused by the protocol negotiation process, thereby improving the communication efficiency between chips.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a data link initialization method, apparatus, electronic device, storage medium, and chip. Background Technology

[0002] As Moore's Law approaches its physical limits, the development of traditional monolithic integrated chips faces performance bottlenecks. Chiplet technology, as a novel heterogeneous integration solution, breaks down a large system-on-chip (SoC) into multiple functionally modular chips and interconnects them using advanced packaging technologies, thereby improving chip design flexibility, yield, and cost-effectiveness.

[0003] The UCIe (Universal Chiplet Interconnect Express) specification is a standard for interconnecting chips. Its purpose is to enable the integration of chips manufactured by different manufacturers and using different processes within the same package structure, thereby enabling complex system-on-a-chip (SoC) composed of at least two chips.

[0004] Because different chips manufactured by different companies using different processes may support multiple data transmission protocols, such as PCIe (Peripheral Component Interconnect Express) and CXL (Compute Express Link), these data transmission protocols support long-distance data transmission. To achieve short-distance and faster data transmission between chips, the UCIe specification defines a mapping between PCIe, CXL, and streaming protocols, making UCIe a short-distance data transmission bridge between chips. In UCIe, the protocol layer of the data transmission protocols supported by the chip (e.g., the transaction layer of PCIe and CXL)... The layer remains unchanged, only the physical link for long-distance transmission of the data transmission protocol supported by the chip is replaced with the short-distance physical link of the UCIe specification. UCIe provides a more efficient physical transmission channel, and the chip can still use its supported data transmission protocols (such as PCIe, CXL). Therefore, based on UCIe's compatibility with multiple data transmission protocols and its high speed of short-distance data transmission, different chips made by different manufacturers and using different processes can be freely combined according to needs to form system-on-a-chip with different functional requirements.

[0005] Because the UCIe specification allows mapping of multiple data transmission protocols, when establishing a connection between a local and a remote core, it's necessary to confirm the data transmission protocols supported by both the local and remote cores. Based on this, the data encapsulation should then be performed using the data transmission protocol that both the local and remote cores can simultaneously support. Therefore, the UCIe specification mandates a complete protocol negotiation process during each link initialization. This includes exchanging the protocols supported by both the local and remote cores (e.g., PCIe, CXL) via a sideband channel, performing protocol discovery, priority arbitration, and parameter negotiation. Even if both the local and remote cores only want to use the same protocol (e.g., PCIe), the entire process must still be completed, resulting in processing delays and resource overhead due to the protocol negotiation process. Summary of the Invention

[0006] In view of this, the present disclosure provides a data link initialization method, apparatus, electronic device, storage medium, and chip, which shortens the processing delay and resource overhead caused by the protocol negotiation process in the link initialization process in a defined communication field, and maintains compatibility with the UCIe specification.

[0007] According to one aspect of the embodiments of this disclosure, a data link initialization method is provided, comprising:

[0008] Acquire a first protocol capability of a local chip and a second protocol capability of a remote chip, wherein the first protocol capability is used to characterize the transmission protocol supported by the local chip, and the second protocol capability is used to characterize the transmission protocol supported by the remote chip, wherein the local chip supports at least one transmission protocol, and the remote chip supports at least one transmission protocol.

[0009] Based on the first protocol capability, the second protocol capability, and the pre-obtained physical link training results between the local chip and the remote chip, determine whether the local chip and the remote chip meet the preset single protocol pass-through condition;

[0010] If the single protocol pass-through condition is met between the local kernel and the remote kernel, a pass-through data path of the transmission protocol corresponding to the single protocol pass-through condition is established.

[0011] In one possible implementation, acquiring the first protocol capability of the local chip and the second protocol capability of the remote chip includes:

[0012] Send protocol capability acquisition requests to the capability register of the local chip and the capability register of the remote chip, respectively;

[0013] The first protocol capability and the second protocol capability are obtained based on the response information received from the capability register of the local chip and the capability register of the remote chip.

[0014] In one possible implementation, the physical link training results include the data transmission rate and power status of the physical layers of the local chip and the remote chip, respectively.

[0015] The single protocol pass-through condition includes: the first protocol capability and the second protocol capability indicating that the first chip in the local chip and the remote chip support only one protocol and the second chip in the local chip and the remote chip support at least the protocol supported by the first chip, and the data transmission rates of the physical layer of the local chip and the physical layer of the remote chip are matched, and the power states of the physical layer of the local chip and the physical layer of the remote chip are matched, wherein the first chip is either the local chip or the remote chip, and the second chip is the other one of the local chip and the remote chip besides the first chip.

[0016] In one possible implementation, establishing a pass-through data path for the transport protocol corresponding to the single protocol pass-through condition includes the following steps performed by at least one of the local kernel and the remote kernel:

[0017] Configure data transmission parameters associated with a specified protocol, wherein the specified protocol is one of the protocols in the single protocol pass-through conditions satisfied by the local chip and the remote chip;

[0018] Activate the protocol stack of the specified protocol;

[0019] Establish the pass-through data path, which includes a receive buffer for the specified protocol, a parser for the specified protocol, and a data send queue.

[0020] In one possible implementation, the data link is a UCIe-based data link.

[0021] In one possible implementation, after establishing a pass-through data path for the transport protocol corresponding to the single protocol pass-through condition, the data link initialization method further includes:

[0022] Set the FDI interface to active state to enable the data link between the local chip and the remote chip.

[0023] In one possible implementation, after setting the FDI interface to an active state, the data link initialization method further includes:

[0024] Continuously monitor the link quality information between the local chip and the remote chip;

[0025] When the link quality information meets the preset abnormal conditions, the data link between the local core and the remote core is disconnected, and the data link between the local core and the remote core is rebuilt according to the link initialization process of the UCIe specification.

[0026] In one possible implementation, the link quality information includes at least one of the following: link bit error rate, number of CRC check failures, and FDI handshake timing.

[0027] The abnormal conditions include at least one of the following: the link bit error rate reaches a preset bit error rate threshold, the number of CRC check failures reaches a preset number of failures, and the FDI handshake times out.

[0028] In one possible implementation, the data link initialization method further includes:

[0029] If the single protocol pass-through condition is not met between the local chip and the remote chip, a data link between the local chip and the remote chip is established according to the link initialization procedure of the UCIe specification.

[0030] According to another aspect of the embodiments of this disclosure, a data link initialization apparatus is provided, comprising:

[0031] The protocol prediction unit is used to obtain the first protocol capability of the local chip and the second protocol capability of the remote chip, wherein the first protocol capability is used to characterize the transmission protocol supported by the local chip, and the second protocol capability is used to characterize the transmission protocol supported by the remote chip. The local chip supports at least one transmission protocol, and the remote chip supports at least one transmission protocol.

[0032] The mode decision unit is used to determine whether the local chip and the remote chip meet the preset single protocol pass-through condition based on the first protocol capability, the second protocol capability and the pre-obtained physical link training results between the local chip and the remote chip.

[0033] The path establishment unit is used to establish a pass-through data path of the transmission protocol corresponding to the single protocol pass-through condition when the single protocol pass-through condition is met between the local core and the remote core.

[0034] In one possible implementation, the data link initialization device further includes:

[0035] The fallback protection unit is used to continuously monitor the link quality information between the local core and the remote core. When the link quality information meets the preset abnormal conditions, the data link between the local core and the remote core is disconnected, and the link initialization process of the UCIe specification is triggered to rebuild the data link between the local core and the remote core.

[0036] According to another aspect of the present disclosure, an electronic device is provided, comprising:

[0037] processor;

[0038] Memory for storing the executable instructions of the processor;

[0039] The processor is configured to execute the executable instructions to implement the data link initialization method as described in any of the preceding claims.

[0040] According to another aspect of the present disclosure, a computer-readable storage medium is provided, which, when at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, enables the electronic device to implement the data link initialization method as described in any of the preceding claims.

[0041] According to another aspect of the present disclosure, a chip is provided, including the data link initialization device as described in any of the preceding claims.

[0042] As can be seen from the above scheme, the data link initialization method, apparatus, electronic device, storage medium and chip disclosed herein, under the condition of single protocol pass-through, bypass the complex protocol negotiation process of the UCIe specification and establish a pass-through data path based on the data link initialization method and apparatus disclosed herein. This helps to improve the data link establishment speed, shorten the data link initialization time, and help to eliminate the redundant processing delays and large resource overhead caused by the protocol negotiation process, thereby helping to improve the communication efficiency between chips. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the link initialization process according to the UCIe specification;

[0044] Figure 2 This is a schematic diagram illustrating a data link initialization method according to an illustrative embodiment;

[0045] Figure 3 This is a flowchart illustrating the steps of acquiring a first protocol capability and a second protocol capability according to an illustrative embodiment;

[0046] Figure 4This is a flowchart illustrating the steps of establishing a pass-through data path for a transport protocol corresponding to a single protocol pass-through condition, according to an illustrative embodiment.

[0047] Figure 5 This is a flowchart illustrating the steps of data link reconnection according to an illustrative embodiment;

[0048] Figure 6 This is a schematic diagram of a data link initialization device according to an illustrative embodiment;

[0049] Figure 7 This is a schematic diagram illustrating the workflow of a data link initialization apparatus employing an embodiment of the present disclosure, according to an illustrative embodiment.

[0050] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure.

[0051] In the attached diagram, the component names represented by each number are as follows:

[0052] 600. Data link initialization device.

[0053] 601. Protocol Prediction Unit

[0054] 602. Model Decision Unit

[0055] 603. Path Establishment Unit

[0056] 604. Back-off protection unit.

[0057] 800. Electronic equipment

[0058] 801, Processor

[0059] 802. Memory. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0061] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0062] Figure 1 This is a schematic diagram of the link initialization process according to the UCIe specification. For example... Figure 1As shown, the link initialization process in the UCIe specification mainly includes four stages: stage 0, stage 1, stage 2, and stage 3. Stage 0 is the local initialization stage for both the local PHY and remote PHY layers. Stage 0 includes impedance calibration and clock recovery, executed independently by the PHY layer without the involvement of the remote PHY layer. Stage 1 involves sideband initialization. Stage 2 involves the training and repair of the mainband, exchanging training parameters through the sideband. Stage 3 involves protocol parameter exchange through the sideband. Stage 3 mainly occurs in the UCIe adapter layer, primarily responsible for the following three parts of the work of the local PHY layer (and the remote PHY layer as well):

[0063] Part 1: Determine the capabilities of the local chip itself.

[0064] Part 2: Parameter exchange with remote cores.

[0065] Part 3: FDI (Flit-aware Die-to-Die Interface) interface startup.

[0066] Here, capability refers to the negotiation ability of a chip to support link operating parameters such as protocol types, flow control unit formats, multi-protocol stack configurations, and retimer buffering capabilities. The FDI interface, located between the protocol layer and the adaptation layer, is a Flit-level inter-chip interface that transmits Flit (Flow Control Unit) format data and supports flow control and error management. A Flit is the basic unit of data transmission in the UCIe specification, containing data payload and flow control information for efficient flow control and error management. A retimer is a protocol-aware intelligent signal relay device that enables long-distance reliable transmission of high-speed data by fully recovering and regenerating digital signals.

[0067] The protocol negotiation process in Phase 3 is quite complex, and the entire protocol negotiation process must be forcibly executed every time the link is initialized, resulting in redundant processing delays and significant resource overhead.

[0068] In view of this, embodiments of the present disclosure provide a data link initialization method, apparatus, electronic device, storage medium, and chip. By introducing a self-aware approach, under specific communication conditions, the complex protocol negotiation process in the UCIe specification is bypassed, and a high-performance pass-through mode is directly entered. This helps to solve the redundant transmission delay problem caused by the protocol negotiation process in the UCIe architecture under known protocol communication scenarios. While ensuring compatibility with the standard UCIe specification, it helps to reduce data path latency and improve inter-chip communication efficiency.

[0069] Figure 2 This is a schematic diagram illustrating a data link initialization method according to an illustrative embodiment, such as... Figure 2 As shown in the illustrative embodiment, the data link initialization method includes the following steps 201 to 203.

[0070] Step 201: Obtain the first protocol capability of the local chip and the second protocol capability of the remote chip, wherein the first protocol capability is used to characterize the transmission protocol supported by the local chip, and the second protocol capability is used to characterize the transmission protocol supported by the remote chip. The local chip supports at least one transmission protocol, and the remote chip supports at least one transmission protocol.

[0071] Step 202: Based on the first protocol capability, the second protocol capability, and the pre-obtained physical link training results between the local core and the remote core, determine whether the local core and the remote core meet the preset single protocol pass-through condition.

[0072] Step 203: If the single protocol pass-through condition is met between the local chip and the remote chip, establish a pass-through data path of the transmission protocol corresponding to the single protocol pass-through condition.

[0073] In the illustrative embodiment, the data link initialization method of this disclosure, namely steps 201 to 203, is executed and completed during the initialization window of phase 3 in the link initialization process of the UCIe specification. This allows for the preemptive establishment of a pass-through data path during the initialization window of phase 3 without pausing the normal execution of phase 3. In the illustrative embodiment, the initialization window begins when the RDI (Raw Die-to-Die Interface) state machine enters the Active state (active or working state). The RDI state machine entering the Active state signifies the completion of phase 2 (master band training and repair), and the physical layer link is ready. In the illustrative embodiment, the initialization window ends with the activation of the FDI Bring-up (FDIBring-up Trigger). The activation of the FDI Bring-up signifies the completion of adaptation layer parameter negotiation and the preparation for establishing the upper-layer protocol interface.

[0074] In an illustrative embodiment, the pass-through data path is located locally within the core. For example, if a local core establishes a pass-through data path for a transport protocol corresponding to a single protocol pass-through condition, the pass-through data path is located within the local core. If a remote core establishes a pass-through data path for a transport protocol corresponding to a single protocol pass-through condition, the pass-through data path is located within the remote core. In this illustrative embodiment, based on the UCIe specification, the pass-through data path is located in the core's adaptation layer and connected to the RDI interface. Data sent and received by the core through the RDI interface is then transmitted within the adaptation layer via the pass-through data path, instead of being transmitted in the manner determined by the mandatory execution of the complete protocol negotiation process in Phase 3 of the link initialization process of the UCIe specification.

[0075] The following describes the data link initialization method disclosed herein, in accordance with the UCIe specification.

[0076] Figure 3 This is a flowchart illustrating the steps for acquiring a first protocol capability and a second protocol capability according to an illustrative embodiment, as shown below. Figure 3 As shown in the illustrative embodiment, in accordance with the UCIe specification, the acquisition of the first protocol capability of the local chip and the second protocol capability of the remote chip in step 201 may specifically include the following steps 301 to 302.

[0077] Step 301: Send protocol capability acquisition requests to the capability register of the local chip and the capability register of the remote chip, respectively;

[0078] Step 302: Obtain the first protocol capability and the second protocol capability based on the response information received from the capability register of the local chip and the capability register of the remote chip.

[0079] In an illustrative embodiment, in conjunction with the link initialization process of the UCIe specification, step 201 begins execution when the RDI interface in phase 3 is set to the Active state. That is, when the RDI interface in phase 3 of the link initialization in the UCIe specification is set to the Active state, the transmission protocols supported by the local chip and the remote chip are obtained. Specifically, when the RDI interface is set to the Active state, a standard capability read command (opcode=0x00) supported by the UCIe specification is sent through the sideband channel initialized in phase 1 (equivalent to the protocol capability acquisition request in step 301). The contents of the UCIe Link DVSEC CapabilityRegister of the remote chip are obtained (in a specific application scenario, the contents of the DCR (Device CapabilityRegister) of the remote chip are obtained), and the contents of the fields related to the supported protocols are parsed (in a specific application scenario, the Protocol Support field in the DCR is parsed). The Bitmap (Protocol Support Bitmap) field, a register bit in the DCR used to indicate the protocol support status of the chip, corresponds to different protocols in bitmap form (a bit of 1 indicates support for the corresponding protocol). This yields a Remote Protocol Capability List (Remote_Protocol_List) recording the transport protocols supported by the remote chip (i.e., the second protocol capability). Simultaneously, the contents of the vendor-specific extended capability register of the UCIe link of the local chip are read, and the fields related to supported protocols are parsed to obtain a Local Protocol Capability List (Local_Protocol_List) recording the transport protocols supported by the local chip (i.e., the first protocol capability). Therefore, in this illustrative embodiment, the first protocol capability is represented as a Local Protocol Capability List, and the second protocol capability is represented as a Remote Protocol Capability List. Among them, the UCIe link-specific vendor-specific extended capability register is a register defined by the UCIe specification. It stores basic link capability information such as the protocol types, maximum data rates, encapsulation types, and multi-protocol stack capabilities supported by the core, so that the software executed by the core can discover the local UCIe capabilities of the core and negotiate with remote cores to determine the final link operating parameters in Phase 3.

[0080] In the illustrative embodiment, the local chip may support more than one transport protocol, and the remote chip may support more than one transport protocol. For example, the same chip may support both PCIe and CXL. Therefore, at least one of the local protocol capability list and the remote protocol capability list may contain more than one protocol. In the illustrative embodiment, a condition for subsequently determining whether to establish a pass-through data path for the transport protocol corresponding to a single protocol pass-through condition is whether one of the local protocol capability list and the remote protocol capability list includes only one protocol, and whether the other of the local protocol capability list and the remote protocol capability list includes at least one protocol, while both the local protocol capability list and the remote protocol capability list include the same protocol. This is because, on the one hand, if the local protocol capability list and the remote protocol capability list include different protocols—that is, if a protocol included in the local protocol capability list does not exist in the remote protocol capability list—then it means that the data transmission protocol of the local chip is incompatible with the data transmission protocol of the remote chip, and the data transmitted between them cannot be correctly parsed by the other party. On the other hand, if both the local protocol capability list and the remote protocol capability list include two or more protocols supported by both the local chip and the remote chip, then it may not be immediately possible to determine which protocol is better for data interaction between the local chip and the remote chip. Determining which protocol is better for data interaction between the local chip and the remote chip is usually a task in Phase 3 of the link initialization process in the UCIe specification. In Phase 3 of the link initialization process in the UCIe specification, even if the local chip supports only one transport protocol and the remote chip supports only one transport protocol (e.g., PCIe), a complex protocol negotiation process still needs to be executed, resulting in redundant processing delays and significant resource overhead. The data link initialization method of this disclosure addresses this issue. When it is discovered that either the local chip or the remote chip supports only one transport protocol, and the other chip also supports that transport protocol, Phase 3 is bypassed, especially the protocol negotiation process in Phase 3. By establishing a direct data path, the data link initialization time is shortened as much as possible, eliminating redundant processing delays and significant resource overhead, thereby helping to improve the communication efficiency between chips.

[0081] In an illustrative embodiment, for the local chip and the remote chip to interact normally, the relevant parameters of their respective physical layers also need to be matched. For example, the data transmission rates of the physical layers of the local chip and the remote chip need to be matched, and the power states such as the voltage domains of their respective physical layers need to be matched.

[0082] In accordance with the UCIe specification, Phase 2 of the link initialization process involves the training and repair of the mainband. Phase 2 yields results such as data transmission rates, voltages, and channel counts for the physical layers of both the local and remote cores. Therefore, in this illustrative embodiment, the physical link training results in step 202 include the data transmission rates and voltages of the physical layers of both the local and remote cores. In this illustrative embodiment, the physical link training results can be obtained in Phase 2 of the link initialization process according to the UCIe specification.

[0083] In an illustrative embodiment, the single protocol pass-through condition needs to consider the types of protocols supported by the local and remote cores, as well as whether the electrical parameters (e.g., data transmission rate, power state) between the physical layers of the local and remote cores match. This is because if the local and remote cores support different protocols, they cannot parse each other's signals to obtain information (including data). Furthermore, if the electrical parameters of the physical layers between the local and remote cores do not match, such as mismatched data transmission rates or power states, they will be unable to correctly identify each other's signals. Based on this, in the illustrative embodiment, the single protocol pass-through condition includes: the first protocol capability and the second protocol capability indicate that the first chip in the local chip and the remote chip support only one protocol, and the second chip in the local chip and the remote chip support at least the protocol supported by the first chip; the data transmission rates of the physical layer of the local chip and the physical layer of the remote chip are matched; and the power states of the physical layers of the local chip and the physical layers of the remote chip are matched. Here, the first chip is either the local chip or the remote chip, and the second chip is the other chip besides the first chip. It should be noted that the power state is not limited to the voltage domain mentioned above; the above only uses the voltage domain as an example. The power state includes the power supply mode, voltage domain, and power operating state of the chip's physical layer. Matching the power states of the physical layers of the local chip and the remote chip means that the power supply modes, voltage domains, and power operating states of the physical layers of the local chip and the remote chip are matched. This ensures that data between the local chip and the remote chip can be received correctly. For example, data sent from the local chip to the remote chip can be received correctly by the remote chip, and data sent from the remote chip to the local chip can be received correctly by the local chip.

[0084] The first protocol capability and the second protocol capability indicate that the first kernel in the local kernel and the remote kernel support only one protocol, and the second kernel in the local kernel and the remote kernel support at least the protocol supported by the first kernel. For example, this can include the following three cases:

[0085] (1) The local protocol capability list records that the local chip supports a protocol and the remote protocol capability list records that the remote chip also supports a protocol. The protocol supported by the local chip is the same as the protocol supported by the remote chip, for example, both only support the PCIe protocol.

[0086] (2) The local protocol capability list records that the local chip supports one protocol (e.g., PCIe), and the remote protocol capability list records that the remote chip supports at least two protocols (e.g., including PCIe, CXL, etc.), and the remote chip supports at least two protocols, including the protocol supported by the local chip (e.g., PCIe).

[0087] (3) The local protocol capability list records that the local chip supports at least two protocols (e.g., PCIe, CXL, etc.), the remote protocol capability list records that the remote chip supports one protocol (e.g., PCIe), and the local chip supports at least two protocols, including the protocol supported by the remote chip (e.g., PCIe).

[0088] In an illustrative embodiment, if the first protocol capability and the second protocol capability indicate that both the local and remote kernels support multiple protocols, it is determined that the single protocol pass-through condition is not met. In this case, the establishment of a data link with the transmission protocol corresponding to the single protocol pass-through condition in step 203 is not performed. Instead, the process waits for the completion of Phase 3 of the UCIe specification and utilizes the data link established in Phase 3 of the UCIe specification. Based on this, in an illustrative embodiment, the data link initialization method of this disclosure may further include: establishing a data link between the local and remote kernels according to the link initialization process of the UCIe specification when the single protocol pass-through condition is not met. In this way, the data link initialization method of this disclosure embodiment, especially step 203, can be embedded in the link initialization process of the UCIe specification. Based on the result of the single protocol pass-through condition, a decision is made between two execution branches: establishing a data link with the transmission protocol corresponding to the single protocol pass-through condition and executing phase 3 of the UCIe specification. This achieves compatibility with the UCIe specification. Furthermore, since the process of establishing a data link with the transmission protocol corresponding to the single protocol pass-through condition does not require a protocol negotiation process, its time consumption is less than that of the complex protocol negotiation process in phase 3 of the UCIe specification. Therefore, when the single protocol pass-through condition is met, using the data link initialization method of this disclosure embodiment helps to shorten the processing delay and resource overhead caused by the protocol negotiation process in the link initialization process in a defined communication scenario, while maintaining compatibility with the UCIe specification.

[0089] Because of the compatibility with the UCIe specification, two scenarios are possible. One is that both the local and remote cores adopt the data link initialization method of this disclosure. Under the condition of single protocol pass-through, both the local and remote cores establish a pass-through data path based on the data link initialization method of this disclosure. Therefore, both the local and remote cores can bypass the complex protocol negotiation process. This improves the overall speed of data link establishment between the local and remote cores, shortens data link initialization time, and helps eliminate redundant processing delays and significant resource overhead caused by the protocol negotiation process, thereby improving communication efficiency between cores. The second scenario involves one of the local and remote cores employing the data link initialization method of this disclosure, while the other core still executes Phase 3. In this case, although the execution of Phase 3 by the other core is time-consuming, it does not significantly increase the overall time required for data link initialization in the UCIe protocol. Furthermore, even if only the local core has improved the data link initialization method of this disclosure, while the remote core still uses the standard UCIe specification, it does not affect the interconnection between the local and remote cores, and the remote core does not need to make corresponding improvements. In this scenario, the local core can still independently execute the data link initialization method of this application, which establishes a pass-through data path based on a single protocol pass-through condition. The remote core can continue to execute the Phase 3 protocol negotiation process of the standard UCIe specification. Since both parties ultimately use the same protocol (e.g., PCIe), the link can still be established normally and is compatible. Therefore, the core using the data link initialization method of this disclosure can still be compatible with cores using the standard UCIe specification. At the same time, once both the local core and the remote core use the data link initialization method of this disclosure, both parties can bypass the complex protocol negotiation process, thereby achieving the goal of improving the communication efficiency between cores while being compatible with the UCIe specification.

[0090] Figure 4 This is a flowchart illustrating the steps for establishing a pass-through data path for a transport protocol corresponding to a single protocol pass-through condition, according to an illustrative embodiment. Figure 4 As shown in the illustrative embodiment, the establishment of a pass-through data path for the transport protocol corresponding to the single protocol pass-through condition in step 203 may include the following steps 401 to 403 performed by at least one of the local kernel and the remote kernel.

[0091] Step 401: Configure the data transmission parameters associated with the specified protocol, wherein the specified protocol is the protocol in the single protocol pass-through condition satisfied by the local chip and the remote chip.

[0092] As an example, the specified protocol is, for example, PCIe, meaning that one of the local protocol capability list and the remote protocol capability list includes only the PCIe protocol, and the other of the local protocol capability list and the remote protocol capability list includes at least the PCIe protocol.

[0093] Step 402: Activate the protocol stack of the specified protocol and disable the processing logic of other protocols besides the specified protocol.

[0094] As an example, if the specified protocol is PCIe, activate the PCIe protocol stack and shut down other protocol stacks besides PCIe. Here, a protocol stack is an independent data transmission channel in the UCIe adaptation layer, and each protocol stack can be independently configured and run a protocol (e.g., PCIe, CXL, or Streaming).

[0095] Disabling the processing logic for protocols other than the specified protocol means stopping the execution of Phase 3. In other words, the data link initialization method of this embodiment can establish a direct data path before Phase 3 is completed, thus eliminating the need for the complete protocol negotiation process of Phase 3 and the method determined by Phase 3. Because the process of establishing a direct data path is shorter than the complex protocol negotiation process of Phase 3, this embodiment can establish a direct data path before Phase 3 is completed, provided that the single protocol direct path condition is met. Therefore, compared to completing Phase 3, it can bypass Phase 3 and use the direct data path to perform data transmission between cores in advance, thereby helping to improve the communication efficiency between cores.

[0096] Step 403: Establish a pass-through data path that includes a receive buffer for the specified protocol, a parser for the specified protocol, and a data send queue.

[0097] The receive buffer for a specified protocol is a data storage area independently owned by the protocol stack of that specified protocol in the adaptation layer. It is used to temporarily store received Flit data of the specified protocol, manage flow control through a credit mechanism, and deliver data to the protocol layer through the FDI interface. For example, the PCIe receive buffer is a data storage area independently owned by the PCIe protocol stack in the adaptation layer, used to temporarily store received PCIe protocol Flit data, manage flow control through a credit mechanism, and deliver data to the protocol layer through the FDI interface.

[0098] The protocol-specific parser is a dedicated parsing module used to identify and parse the Flit format of the specified protocol, extract content information, and perform protocol-specific processing to ensure that data of the specified protocol can be correctly distributed to the receive buffer of its protocol stack. For example, the PCIe packet parser is used to identify and parse the PCIe Flit format, extract TLP (Transaction Layer Packet) information, and perform protocol-specific processing to ensure that PCIe data is correctly distributed to the receive buffer of the PCIe protocol stack.

[0099] The data transmission queue is a shared transmission buffer for all protocol stacks, used to temporarily store Flit data to be sent. It supports retransmission mechanisms and manages data scheduling across multiple protocol stacks through a protocol arbitrator, ultimately sending the data to the physical layer via the RDI interface. Based on the data link initialization method of this disclosure, disabling the processing logic of other protocols may include disabling the protocol stacks and state machines of other protocols, and disabling processing involving other protocols, such as disabling the data scheduling management of other protocol stacks by the protocol arbitrator. In an illustrative embodiment, clock gating is used to disable the clock of the processing logic of protocols other than the specified protocol, thereby disabling the processing logic of protocols other than the specified protocol.

[0100] By establishing a direct data path for the transmission protocol corresponding to the direct connection condition of a single protocol, the adaptation layer can directly start supporting only the specified protocol without having to go through protocol negotiation. This helps to speed up the configuration process of the adaptation layer and shorten the link initialization process.

[0101] In accordance with the UCIe specification, the establishment of a data link between a local kernel and a remote kernel requires the RDI interface to be active in order to enable data interaction between the local kernel and the remote kernel. Based on this, in the illustrative embodiment, after establishing the pass-through data path of the transport protocol corresponding to the single protocol pass-through condition in step 203, the data link initialization method of this disclosure embodiment may further include: setting the FDI interface to an active state to enable the data link between the local kernel and the remote kernel.

[0102] After this, data exchange can occur between local and remote kernels.

[0103] The data link initialization method of this disclosure completes remote capability detection (step 201) and mode decision and bypass condition judgment (step 202) within the initialization window. If the single protocol pass-through condition is met, FDI Bring-up is directly triggered after completing step 203, skipping redundant negotiation steps such as Flit format exchange and protocol arbitration in stage 3, and quickly establishing a data channel. This initialization window does not occupy the main data path timing and follows the state machine transition rules of the UCIe specification.

[0104] In addition to achieving compatibility with the UCIe specification, to further ensure the stability of data transmission between cores and to prevent the difficulty in re-establishing the connection through steps 201 to 203 after an accidental break in the inter-core link, in the illustrative embodiment, the data link initialization method of this disclosure may further include a backup and reconnection scheme based on the UCIe specification. Figure 5 This is a flowchart illustrating the steps of data link reconnection according to an illustrative embodiment, such as... Figure 5 As shown in the illustrative embodiment, after the FDI interface is set to an active state, the data link initialization method of this disclosure embodiment may further include the data link reconnection process of steps 501 to 502.

[0105] Step 501: Continuously monitor the link quality information between the local chip and the remote chip;

[0106] Step 502: When the link quality information meets the preset abnormal conditions, disconnect the data link between the local core and the remote core, and rebuild the data link between the local core and the remote core according to the link initialization process of the UCIe specification.

[0107] In an illustrative embodiment, based on the UCIe specification, link quality information includes at least one of the following: link bit error rate (BER), number of CRC (Cyclic Redundancy Check) failures, and FDI handshake timing. The BER is a metric for the probability of bit errors in physical layer transmission within the UCIe specification. The UCIe specification requires the BER to meet a specific threshold. The BER is used to evaluate link signal integrity and reliability, and it is a key parameter determining whether to enable retry mechanisms and the success of link training. The CRC check is a mechanism in the UCIe specification's adaptation layer used to detect errors in Flit data transmission. It ensures data integrity by calculating and appending a checksum to the Flit at the sending end (e.g., local core) and verifying the checksum at the receiving end (e.g., remote core). CRC checks are used to trigger retransmissions or error handling. Based on the UCIe protocol, a failed CRC check triggers a retransmission; therefore, too many failed CRC checks mean too many retransmissions, leading to inefficient data transmission between cores. FDI handshake timing is a timing management mechanism used during state transitions between the UCIe adaptation layer and the protocol layer. It ensures that the FDI interface is correctly synchronized between protocol layer requests and adaptation layer responses, guaranteeing the reliability and timing consistency of data transmission.

[0108] In the illustrative embodiment, the abnormal conditions include at least one of the following: the link bit error rate reaches a preset bit error rate threshold, the number of CRC check failures reaches a preset number of failures, and the FDI handshake times out. The settings for the bit error rate threshold, the preset number of failures, and the FDI handshake timeout can be configured based on the UCIe specification and actual needs.

[0109] Because the data link initialization method of this disclosure automatically executes the setting of a pass-through data path by judging (also known as sensing) the transmission protocols supported by the local core and the remote core, thereby establishing a data link between cores, and because the data link initialization method of this disclosure can adaptively adjust different data link initialization branches (including the branch for establishing the pass-through data path in this disclosure embodiment and the branch for stage 3 of the link initialization process of executing the UCIe specification) according to the different transmission protocols supported by the different cores used, the data link initialization method of this disclosure can also be called a protocol self-aware link initialization method.

[0110] This disclosure also provides a data link initialization device. Figure 6 This is a schematic diagram of the data link initialization device according to an illustrative embodiment, as shown below. Figure 6As shown in the illustrative embodiment, the data link initialization device 600 of this disclosure is disposed in the adaptation layer of the UCIe specification. The data link initialization device 600 mainly includes a protocol prediction unit 601, a mode decision unit 602, and a path establishment unit 603. The protocol prediction unit 601 is used to obtain the first protocol capability of the local chip and the second protocol capability of the remote chip. The first protocol capability characterizes the transmission protocols supported by the local chip, and the second protocol capability characterizes the transmission protocols supported by the remote chip. The local chip supports at least one transmission protocol, and the remote chip supports at least one transmission protocol. The mode decision unit 602 is used to determine whether a preset single protocol pass-through condition is met between the local chip and the remote chip based on the first protocol capability, the second protocol capability, and the pre-obtained physical link training results between the local chip and the remote chip. The path establishment unit 603 is used to establish a pass-through data path for the transmission protocol corresponding to the single protocol pass-through condition if the single protocol pass-through condition is met between the local chip and the remote chip.

[0111] In a preferred embodiment, both the local core's adaptation layer and the remote core's adaptation layer are equipped with the data link initialization device 600 of this disclosure. This allows both the local and remote cores to bypass the complex protocol negotiation process while meeting the single protocol pass-through condition, thus shortening the link initialization process and improving inter-core communication efficiency. Furthermore, even if only one of the local or remote core's adaptation layers is equipped with the data link initialization device 600 of this disclosure, it is still compatible with the UCIe standard. The fact that the party without the data link initialization device 600 (e.g., the remote core) follows the UCIe standard's data link initialization process will not affect the pass-through data path of the party with the data link initialization device 600 (e.g., the local core).

[0112] Meanwhile, to further ensure compatibility with the UCIe specification, in the illustrative embodiment, the path establishment unit 603 can also be further configured to establish a link between the local core and the remote core according to the link initialization procedure of the UCIe specification when the single protocol pass-through condition is not met between the local core and the remote core. Specifically, in the illustrative embodiment, the path establishment unit 603 can also be further configured to trigger stage 3 of the link initialization procedure of the UCIe specification when the single protocol pass-through condition is not met between the local core and the remote core.

[0113] Furthermore, to further ensure the stability of data transmission between cores and prevent the possibility of difficulty in re-establishing a direct data path for the transmission protocol corresponding to the single protocol's direct connection condition after an unexpected break in the inter-core link, and thus complete the initialization of the data link, such as... Figure 6 As shown in the illustrative embodiment, the data link initialization apparatus 600 of this disclosure may further include a fallback protection unit 604. The fallback protection unit 604 is used to continuously monitor the link quality information between the local core and the remote core. When the link quality information meets preset abnormal conditions, the data link between the local core and the remote core is disconnected, and the link initialization process of the UCIe specification is triggered to rebuild the data link between the local core and the remote core.

[0114] Regarding the data link initialization device 600 in the above embodiments, the specific manner in which each unit performs its operation has been described in detail in the embodiments of the data link initialization method described above, and will not be elaborated here.

[0115] In illustrative embodiments, depending on the design, at least one of the protocol prediction unit 601, mode decision unit 602, path establishment unit 603, and fallback protection unit 604 can be implemented as a combination of multiple hardware, firmware, and software (i.e., programs).

[0116] In terms of hardware, at least one of the protocol prediction unit 601, mode decision unit 602, path establishment unit 603, and fallback protection unit 604 can be implemented in logic circuits on integrated circuits. For example, the relevant functions of at least one of the protocol prediction unit 601, mode decision unit 602, path establishment unit 603, and fallback protection unit 604 can be implemented in various logic blocks, modules, and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), central processing units (CPUs), or other processing units. The relevant functions of at least one of the protocol prediction unit 601, mode decision unit 602, path establishment unit 603, and fallback protection unit 604 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in integrated circuits, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0117] In software or firmware form, the relevant functions of at least one of the protocol prediction unit 601, mode decision unit 602, path establishment unit 603, and fallback protection unit 604 can be implemented as programming codes. For example, at least one of the protocol prediction unit 601, mode decision unit 602, path establishment unit 603, and fallback protection unit 604 can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded and stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or a storage device. An electronic device (e.g., a CPU, hardware controller, microcontroller, hardware processor, or microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium to implement the relevant functions of at least one of the protocol prediction unit 601, mode decision unit 602, path establishment unit 603, and fallback protection unit 604.

[0118] In the illustrative embodiments, the data link initialization device of this disclosure is applicable to SoC chips, etc., wherein the SoC chip can be any one of CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit).

[0119] The following description uses a specific application scenario where the local chip only supports the PCIe protocol as an example to supplement the description of the data link initialization method and apparatus of this disclosure. For any descriptions not covered in the above embodiments, please refer to the following description.

[0120] In the illustrative embodiment, during the initialization window starting from the RDI signal being valid (i.e., the RDI interface being set to Active state, indicating entry into Phase 3), the protocol prediction unit 601 sends a capability read command for the standards supported by the UCIe specification to the remote chip via a sideband. This retrieves the contents of the vendor-specific extended capability register of the UCIe link on the remote chip, parses the fields related to supported protocols, and obtains a remote protocol capability list. Simultaneously, the protocol prediction unit 601 reads the contents of the vendor-specific extended capability register of the UCIe link on the local chip, parses the fields related to supported protocols, and obtains a local protocol capability list. Since this specific application scenario exemplifies a local chip that only supports the PCIe protocol, the local protocol capability list only includes the PCIe protocol.

[0121] In the illustrative embodiment, the mode decision unit 602 performs Boolean condition judgment based on the capability matching results between the local and remote core particles, the physical layer training results obtained in Phase 2 (including rate, voltage, and number of channels), and the power status flag, to determine whether the preset single protocol pass-through condition is met, and finally outputs the Bypass_Enable signal (active high, indicating that the pass-through condition is met). The Boolean condition judgment is a logical determination mechanism based on true / false states, which can be used in the UCIe specification to determine state transitions, capability negotiation, and error handling decisions in the UCIe link state machine. The power status flag characterizes the power supply mode, voltage domain, and power operating state of the core particle's physical layer. In the illustrative embodiment, the power supply mode, voltage domain, and power operating state can be collectively referred to as the power state. If the power status flags of the local core particle and the remote core particle match, it indicates that the power state of the local and remote core particle physical layers is matched (power supply mode matching, voltage domain matching, power operating state matching), thus ensuring that data between the local and remote core particles can be correctly received. In the illustrative embodiment, the power supply mode includes the power supply type, power consumption mode, and regulator operation mode of the chip physical layer; the power supply operation state includes the voltage stability of the chip physical layer, power-on completion state, reset release state, and signal drive ready state.

[0122] Assuming the remote protocol capability list includes at least the PCIe protocol, and the data transfer rates of the physical layers of the local chip and the remote chip match, and the power states of the physical layers of the local chip and the remote chip match, then the mode decision unit 602 determines that the preset single protocol pass-through condition is met and outputs Bypass_Enable=1. Conversely, assuming the remote protocol capability list does not include the PCIe protocol, then the mode decision unit 602 determines that the preset single protocol pass-through condition is not met and outputs Bypass_Enable=0.

[0123] In the illustrative embodiment, the protocol prediction unit 601 and the mode decision unit 602 utilize the initialization window period defined in the UCIe specification (typically hundreds of microseconds to several milliseconds) to quickly complete capability detection and mode decision-making after the RDI signal is set (i.e., the RDI state machine enters the active state). The path establishment unit 603, under the preset single protocol pass-through condition (i.e., upon receiving the Bypass_Enable=1 signal), skips the multi-protocol negotiation process in phase 3 of the link initialization process in the UCIe specification. That is, it does not execute steps such as Flit Format Exchange and Protocol Arbitration, and directly establishes a pass-through data path corresponding to PCIe. For example, this may include directly sending an FDI Bring-up request to the protocol layer of the local chip, specifying the protocol type as PCIe, and simultaneously disabling unnecessary logic such as the CXL parser, protocol arbitration state machine, and multi-protocol selector (MUX) without affecting the timing of the main data path.

[0124] In the illustrative embodiment, the fallback protection unit 604 continuously monitors the link error rate, CRC check failure count, FDI handshake timing, and other triggering conditions that can lead to physical layer retraining of the local and remote cores. When a triggering condition is generated, such as the link error rate reaching a preset error rate threshold, the CRC check failure count reaching a preset failure count threshold, or the FDI handshake timeout, it automatically switches to the full-function mode of the standard UCIe specification (i.e., the link initialization process and related function modes specified by the UCIe specification) to ensure connection reliability.

[0125] In the illustrative embodiment, the triggering condition can be summarized as the situation where, under the preset single protocol pass-through condition, i.e., when Bypass_Enable=1, a pass-through data path between the local chip and the remote chip cannot be established normally, and low-latency transmission cannot be maintained. For example:

[0126] (1) Misjudgment of mode decision: The single protocol pass-through condition was misjudged (when in fact the protocols at both ends were mismatched and the physical layer rates were incompatible), which resulted in the inability to establish an effective data link channel between the cores after the pass-through data path was established;

[0127] (2) Failed to establish pass-through data path: An error occurred when establishing the pass-through data path (e.g., incorrect FDI parameter configuration, or unnecessary logic being disabled).

[0128] (3) Data link anomaly: After the data link is established, the data link between the cores cannot transmit normally (such as the link error rate reaching the preset error rate threshold, the number of CRC check failures reaching the preset number of failures, and the FDI handshake timeout), which in turn exceeds the fault tolerance range of the pass-through mode implemented by the data link.

[0129] In the illustrative embodiment, the data link initialization device of this disclosure starts immediately after the RDI state machine enters the Active state (active state or working state) and completes it before the end of stage 3 to avoid affecting the timing of the main data path (i.e., the main band).

[0130] In the illustrative embodiment, the protocol layer is configured by default as a PCIe protocol stack, and CXL and other protocol parsing logic are disabled when using the data link initialization method and apparatus of this disclosed embodiment, thereby saving power consumption and combinational logic latency.

[0131] In the illustrative embodiment, when using the data link initialization method and apparatus of the present disclosed embodiment, the data path inside the adaptation layer is reconstructed. The multi-protocol selector and arbitration logic related to protocol selection are removed from the pass-through data path, and only the packet encapsulation / decapsulation unit required by the corresponding protocol is retained. Compared with the data path in the full protocol negotiation mode of the UCIe specification, the latency from the receive buffer to the send queue can be greatly reduced. Tests have shown that the path latency from the receive buffer to the send queue can be reduced by about 90%.

[0132] In a preferred embodiment, the data link initialization device of this disclosure can be deployed between two interconnected chips with the same package, and each chip integrates the data link initialization device of this disclosure.

[0133] Figure 7 This is a schematic diagram illustrating the workflow of a data link initialization apparatus employing an embodiment of the present disclosure, according to an exemplary embodiment. This link initialization workflow is embedded in the UCIe specification and, in conjunction with... Figure 7 As shown, the link initialization workflow of the data link initialization device in this embodiment includes the following steps 701 to 706.

[0134] Step 701: Power on and reset release.

[0135] Step 701 should include: (1) the system is powered on, and the local chip and the remote chip each complete their internal reset; (2) the physical layer executes the link initialization phase 0 to phase 2 of the UCIe specification.

[0136] Step 702: Start-up and capability exploration of the data link initialization device.

[0137] Step 702 mainly includes: (1) After the RDI state machine enters the Active state, the data link initialization device is immediately activated; (2) The protocol prediction unit initiates the reading of protocol capabilities, at which time the local core and the remote core exchange protocol capabilities; (3) Synchronously acquire the physical layer training results obtained in stage 2.

[0138] Step 703: Perform pattern determination.

[0139] Step 703 mainly includes: (1) The mode decision unit performs a Boolean judgment to determine whether the single protocol pass-through condition is met between the local kernel and the remote kernel; (2) If the single protocol pass-through condition is met, the Bypass_Enable signal is output as 1. In the illustrative embodiment, the Bypass_Enable signal is output to the path establishment unit and simultaneously synchronized to the fallback protection unit.

[0140] Step 704: Path switching.

[0141] Step 704 mainly includes the following operations performed by the path establishment unit: (1) bypassing the protocol negotiation window in phase 3 of the UCIe specification, because the UCIe timeout condition setting allows the protocol negotiation window to last up to 8ms; (2) directly configuring the FDI interface parameters, such as Flit size of 256B and protocol of PCIe; (3) activating the PCIe protocol stack and disabling other protocol-related logic; (4) establishing a direct data path from the receive buffer to the PCIe packet parser to the send queue.

[0142] Step 705: Link Activation and Data Transmission.

[0143] Step 705 mainly includes: (1) setting the FDI signal (the FDI state machine enters the ACTIVE state), and opening the main data link between the local chip and the remote chip; (2) data is directly transmitted in PCIe TLP format through the pass-through data path established in the adaptation layer, without protocol conversion overhead. After actual testing, the end-to-end latency from the local chip to the remote chip can be reduced by more than 90% (excluding the chain establishment time).

[0144] Step 706: Anomaly monitoring and rollback.

[0145] Step 706 is an optional step, which mainly includes: (1) the fallback protection unit continuously samples the link quality; (2) if an anomaly is detected, the fallback process is triggered: (a) disconnect the current connection; (b) re-initialize the link and disable the data link initialization device; (c) rebuild the link according to the UCIe specification process.

[0146] The data link initialization method and apparatus of this disclosure reconstruct the data path. When using the data link initialization method and apparatus of this disclosure, the original multi-protocol selector (typically a 4:1 or 8:1 selector) can be removed from the adapter layer and replaced with a fixed single-protocol (e.g., PCIe) direct data path, reducing the number of combinational logic stages and lowering path latency. Simultaneously, this disclosure optimizes power consumption because clock gating shuts down the clocks of other protocol state machines (e.g., CXL state machines) and module clocks such as protocol arbitrators, besides the single protocol used (e.g., PCIe), thereby contributing to power consumption reduction. Tests show a static power consumption reduction of approximately 15% to 20%.

[0147] The data link initialization device of this disclosure embodiment can also provide necessary control registers (such as enable registers and rollback status registers for starting the data link initialization device) as needed, to facilitate status querying and debugging by the firmware or BMC (Baseboard Management Controller). The BMC is a dedicated microcontroller used to implement out-of-band management functions.

[0148] The data link initialization method and apparatus of this disclosure are implemented based on UCIe and are fully compatible with the relevant definitions of the UCIe specification, including the physical layer and sideband definitions. They are interoperable with any standard UCIe specification core. When a remote core does not support the data link initialization method and apparatus of this disclosure, the local core can adaptively switch to the standard mode of the UCIe specification.

[0149] The application scenarios of the data link initialization method and apparatus in this disclosure include, but are not limited to, the interconnection between the computing chip and the HBM (High Bandwidth Memory) controller chip in an AI (Artificial Intelligence) acceleration chip, the direct connection between the CPU and the dedicated PCIe Root Complex chip, and low-latency communication between homogeneous computing units in a data center SoC.

[0150] To address the issue of redundant negotiation delays in the UCIe specification under known protocol scenarios, this disclosure employs a data link initialization method and apparatus at the protocol layer to establish a direct data path. While ensuring compatibility with the UCIe specification, it skips redundant protocol negotiation processes by judging the direct connection conditions for a single protocol, achieving low-latency direct communication for scenarios supporting only a single protocol. This helps improve the overall system performance and energy efficiency. Furthermore, a fallback mechanism ensures that a reliable connection as specified in the UCIe specification can be established even in the event of link anomalies.

[0151] Compared with the data link initialization method and apparatus of this disclosure, the standard UCIe specification enforces a complete protocol enumeration and arbitration process in terms of protocol negotiation. This disclosure, however, dynamically senses whether a single protocol pass-through condition is met; if so, it skips the protocol negotiation of the standard UCIe specification, helping to shorten the chain establishment time. Test results show that this can reduce the short chain establishment time by more than 90%. Regarding operational mode flexibility, the standard UCIe specification adopts a fixed multi-protocol coexistence architecture, while this disclosure supports two modes: the fixed multi-protocol coexistence architecture used in the standard UCIe specification and a pass-through data path mode, adaptively switching according to different conditions, balancing versatility and high performance. In terms of hardware resource overhead, the standard UCIe specification always enables logic such as the arbitrator, multi-protocol selector, and protocol parsing unit, while this disclosure disables unnecessary protocol logic in the pass-through data path mode. This invention helps save power consumption and related circuit area overhead, with test results showing a power saving of approximately 18%. Regarding data path latency, data in the standard UCIe specification requires processing from protocol identification to encapsulation to transmission, while this embodiment directly binds to a single protocol stack (e.g., PCIe), simplifying the data transmission path and reducing path latency by approximately 90%. In terms of error recovery mechanisms, the standard UCIe specification lacks an automatic fallback mechanism (failure results in a disconnection), while this embodiment, through a built-in fallback protection unit, can automatically switch back to the standard UCIe specification mode in case of an anomaly, improving system robustness and reliability. Regarding applicable scenarios, the standard UCIe specification is applicable to a wide range of heterogeneous hybrid protocol environments, but lacks specificity, while this embodiment is particularly suitable for various dedicated systems, such as inter-core communication in AI accelerator cards, interconnection between HBM and logic chips, and various closed ecosystem chipsets, offering stronger optimization for various dedicated system scenarios.

[0152] Figure 8This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. In some embodiments, the electronic device is a server. The electronic device 800 can vary considerably due to different configurations or performance, and may include one or more Central Processing Units (CPUs) 801 and one or more memories 802, wherein the memory 802 stores at least one line of program code, which is loaded and executed by the processor 801 to implement the data link initialization method provided in the various embodiments described above. Of course, the electronic device 800 may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The electronic device 800 may also include other components for implementing device functions, which will not be elaborated here.

[0153] In an exemplary embodiment, a computer-readable storage medium including at least one instruction is also provided, such as a memory including at least one instruction, which can be executed by a processor in a computer device to complete the data link initialization method in the above embodiments.

[0154] Optionally, the aforementioned computer-readable storage medium may be a non-transitory computer-readable storage medium, such as ROM (Read-Only Memory), RAM (Random-Access Memory), CD-ROM (Compact Disc Read-Only Memory), magnetic tape, floppy disk, and optical data storage devices.

[0155] In an illustrative embodiment, a chip is also provided, including the data link initialization device of any of the above embodiments.

[0156] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method of data link initialization, characterized by, include: Acquire a first protocol capability of a local chip and a second protocol capability of a remote chip, wherein the first protocol capability is used to characterize the transmission protocol supported by the local chip, and the second protocol capability is used to characterize the transmission protocol supported by the remote chip, wherein the local chip supports at least one transmission protocol, and the remote chip supports at least one transmission protocol. Based on the first protocol capability, the second protocol capability, and the pre-obtained physical link training results between the local chip and the remote chip, determine whether the local chip and the remote chip meet the preset single protocol pass-through condition; If the single protocol pass-through condition is met between the local kernel and the remote kernel, a pass-through data path of the transmission protocol corresponding to the single protocol pass-through condition is established. The physical link training results include the data transmission rate and power status of the physical layers of the local core and the remote core, respectively. The single protocol pass-through condition includes: the first protocol capability and the second protocol capability indicate that the first core among the local core and the remote core supports only one protocol and the second core among the local core and the remote core supports at least the protocol supported by the first core, and the data transmission rates of the physical layers of the local core and the remote core match, and the power status of the physical layers of the local core and the remote core match, wherein the first core is either the local core or the remote core, and the second core is the other one among the local core and the remote core besides the first core.

2. The data link initialization method according to claim 1, characterized in that, The acquisition of the first protocol capability of the local chip and the second protocol capability of the remote chip includes: Send protocol capability acquisition requests to the capability register of the local chip and the capability register of the remote chip, respectively; The first protocol capability and the second protocol capability are obtained based on the response information received from the capability register of the local chip and the capability register of the remote chip.

3. The data link initialization method according to claim 1, characterized in that, The establishment of a pass-through data path for the transport protocol corresponding to the single protocol pass-through condition includes the following steps performed by at least one of the local kernel and the remote kernel: Configure data transmission parameters associated with a specified protocol, wherein the specified protocol is one of the protocols in the single protocol pass-through conditions satisfied by the local chip and the remote chip; Activate the protocol stack of the specified protocol; Establish the pass-through data path, which includes a receive buffer for the specified protocol, a parser for the specified protocol, and a data send queue.

4. The data link initialization method according to any one of claims 1 to 3, characterized in that: The data link is a data link based on the UCIe specification.

5. The data link initialization method according to claim 4, characterized in that, After establishing the pass-through data path of the transport protocol corresponding to the single protocol pass-through condition, the data link initialization method further includes: Set the FDI interface to active state to enable the data link between the local chip and the remote chip.

6. The data link initialization method according to claim 5, characterized in that, After setting the FDI interface to an active state, the data link initialization method further includes: Continuously monitor the link quality information between the local chip and the remote chip; When the link quality information meets the preset abnormal conditions, the data link between the local core and the remote core is disconnected, and the data link between the local core and the remote core is rebuilt according to the link initialization process of the UCIe specification.

7. The data link initialization method according to claim 6, characterized in that: The link quality information includes at least one of the following: link bit error rate, number of CRC check failures, and FDI handshake timing; The abnormal conditions include at least one of the following: the link bit error rate reaches a preset bit error rate threshold, the number of CRC check failures reaches a preset number of failures, and the FDI handshake times out.

8. The data link initialization method according to claim 4, characterized in that, The data link initialization method further includes: If the single protocol pass-through condition is not met between the local chip and the remote chip, a data link between the local chip and the remote chip is established according to the link initialization procedure of the UCIe specification.

9. A data link initialization device, characterized in that, include: The protocol prediction unit is used to obtain the first protocol capability of the local chip and the second protocol capability of the remote chip, wherein the first protocol capability is used to characterize the transmission protocol supported by the local chip, and the second protocol capability is used to characterize the transmission protocol supported by the remote chip. The local chip supports at least one transmission protocol, and the remote chip supports at least one transmission protocol. The mode decision unit is used to determine whether the local chip and the remote chip meet the preset single protocol pass-through condition based on the first protocol capability, the second protocol capability and the pre-obtained physical link training results between the local chip and the remote chip. The path establishment unit is used to establish a pass-through data path of the transmission protocol corresponding to the single protocol pass-through condition when the single protocol pass-through condition is met between the local core and the remote core. The physical link training results include the data transmission rate and power status of the physical layers of the local core and the remote core, respectively. The single protocol pass-through condition includes: the first protocol capability and the second protocol capability indicate that the first core among the local core and the remote core supports only one protocol and the second core among the local core and the remote core supports at least the protocol supported by the first core, and the data transmission rates of the physical layers of the local core and the remote core match, and the power status of the physical layers of the local core and the remote core match, wherein the first core is either the local core or the remote core, and the second core is the other one among the local core and the remote core besides the first core.

10. The data link initialization apparatus according to claim 9, characterized in that, The data link initialization device further includes: The fallback protection unit is used to continuously monitor the link quality information between the local core and the remote core. When the link quality information meets the preset abnormal conditions, the data link between the local core and the remote core is disconnected, and the link initialization process of the UCIe specification is triggered to rebuild the data link between the local core and the remote core.

11. An electronic device, characterized in that, include: processor; Memory for storing the executable instructions of the processor; The processor is configured to execute the executable instructions to implement the data link initialization method as described in any one of claims 1 to 8.

12. A computer-readable storage medium, characterized in that, When at least one instruction in the computer-readable storage medium is executed by the processor of the electronic device, the electronic device is able to implement the data link initialization method as described in any one of claims 1 to 8.

13. A chip, characterized in that, Includes the data link initialization device as described in claim 9 or 10.

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