Method, apparatus and circuit for feature mapping data padding
By generating and optimizing data transmission in real time through a hardware-based data filling control circuit, the problems of low data filling efficiency and wasted memory bandwidth in neural network hardware are solved, thus realizing a high-efficiency, low-power neural network hardware design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING UNIV OF TECH
- Filing Date
- 2025-12-02
- Publication Date
- 2026-07-21
Smart Images
Figure CN122019458B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of artificial intelligence. Background Technology
[0002] As artificial intelligence technology penetrates deeper into fields such as computer vision, natural language processing, and autonomous driving, the demands for model accuracy and complexity in application scenarios continue to increase, driving neural networks to evolve towards deeper and broader directions. From the early LeNet-5 (7 layers) to ResNet-50 (50 layers), and now to the ultra-deep architectures used for training large models, the increase in the number of network layers means enhanced feature extraction capabilities, but it also places higher demands on the computing and data processing capabilities of the underlying hardware: it not only needs to support massive amounts of core computations such as convolution and pooling, but also needs to efficiently handle various accompanying preprocessing operations, gradually highlighting the bottleneck problem of hardware performance.
[0003] However, the design focus of current mainstream neural network hardware has long been on accelerating and optimizing convolution and pooling operations. These two operations are core components of feature extraction in neural networks, so hardware manufacturers continuously improve their computational efficiency through parallel computing unit design and pipeline optimization. However, in actual network operation, in addition to convolution and pooling, there are numerous preprocessing operations such as data normalization, channel dimension adjustment, and data padding. Although these operations have relatively small individual computational loads, they need to be performed frequently before each network layer. As the number of network layers increases, the cumulative time and resource consumption of preprocessing operations continuously increase, gradually transforming from a secondary aspect into a key bottleneck restricting overall hardware efficiency.
[0004] Among numerous preprocessing steps, data padding, due to its high frequency and strong dependence on data transmission, has become a core obstacle to improving current hardware efficiency. The core function of data padding is to address the problem of feature map size shrinkage during convolution operations. Specifically, when the convolution kernel slides across the input feature map for computation, if the input size does not match the kernel size, the edge length of the output feature map will decrease with each computation. To maintain consistency between the input and output feature map sizes and ensure that edge features are not lost (edge pixels only participate in one convolution computation, while internal pixels participate multiple times; without padding, edge information weights will be too low), a certain number of values (usually zero values) need to be padded at the edges of the input feature map. This increases the input size to offset the size compression caused by the convolution operation.
[0005] Current hardware methods for data padding primarily rely on processors implementing it through software logic. This approach has three main drawbacks: First, it suffers from low computational efficiency. Software padding requires iterating through each pixel of the input feature map, determining whether zero values need to be filled in at each position, and writing them into memory. This is essentially a serialized operation, severely slowing down network speeds. Second, it results in significant memory bandwidth waste. After software padding, the data containing zero values needs to be completely moved from external memory to the on-chip cache. However, these zero values are invalid data, yet they consume memory bandwidth. Third, it leads to a surge in on-chip cache area. To store the complete feature map containing the padding data, the on-chip cache must be designed according to the padded size, requiring additional space for cache capacity. This not only increases the chip area and manufacturing cost but also leads to increased leakage power consumption due to the expanded cache capacity, violating the high energy efficiency goals of hardware design.
[0006] To address the aforementioned issues, there is an urgent need to design a dedicated hardware filling control circuit to resolve the filling bottleneck from the perspective of data transmission and computational coordination. The core design idea of this circuit is to generate filling data in real time, avoiding invalid data transmission.
[0007] (1) To address the problem that relying on software to perform data filling operations in neural network computation leads to low computational efficiency and difficulty in accurately matching the data supply demand of convolutional pooling operations, an innovative method is proposed by designing a hardware automatic filling control circuit, combining network layer information such as convolution kernel size and input feature mapping position to judge data type in real time and generate effective data or zero-value filling data. This method can achieve the results of accurately providing data, eliminating the bottleneck of software serial filling efficiency, and efficiently cooperating with convolutional pooling computation.
[0008] (2) To address the problem that the memory bandwidth is wasted due to the need to transmit data containing invalid zero values after software filling, and the area of the on-chip cache increases due to the need to store complete filling data, a transmission control mechanism is adopted to transmit only valid input feature mapping data to the on-chip cache and not transmit invalid zero values, thereby significantly reducing memory bandwidth consumption and reducing the on-chip cache capacity requirement. Summary of the Invention
[0009] To improve the execution efficiency of neural network algorithms and reduce memory data transfer bandwidth, this invention proposes a data padding method and apparatus. The apparatus includes a data padding calculation control module to efficiently handle data padding between each neural network convolutional layer; simultaneously, the data padding transmission control module, in conjunction with a corresponding data transmission module, can quickly move input data from memory to on-chip cache, thereby initiating neural network algorithm computation. A functional schematic diagram of the data padding circuit is shown below. Figure 1 As shown.
[0010] First, the data filling circuit calculates the transmission control signal through network information and sends it to the data transmission module. The data transmission module then transfers the memory data to the on-chip cache according to the control signal. Next, the data filling calculation control module obtains the on-chip cache control signal or the fill zero signal and controls the multiplexer MUX to send the corresponding data to the computing array.
[0011] 2.1.1 Data Filling Calculation Control Module
[0012] This module calculates the corresponding control signal based on the relevant network layer information, which is used to control whether the data given to the computing array is fill data or on-chip cache data; if it is on-chip cache data, it will also give the corresponding address and enable control signal to the on-chip cache to ensure that the on-chip cache outputs correct data.
[0013] Depending on the network layer information, this module will output different control signals. The circuit supports four types of data filling, such as... Figure 2 As shown. If the feature mapping data is not divided into blocks, then the four boundaries (top, bottom, left, and right) of the feature mapping need to be filled with 0, and other data is output through on-chip buffer. If the feature mapping data is divided into blocks, then corresponding control signals need to be given according to the specific block position, which can be divided into three positions: start block, middle block, and end block. The specific filling situation is as follows:
[0014] (1) The starting line block needs to be filled with 3 boundaries (top, left, right).
[0015] (2) The middle row block needs to be filled with two boundaries (left and right).
[0016] (3) The ending line block needs to be filled with 3 boundaries (bottom, left, right).
[0017] The flowchart for data filling calculation control is as follows: Figure 3 As shown, after the data is transmitted to the on-chip buffer, it is first determined whether the feature mapping data of this network layer is segmented. If it is not segmented, all boundaries are checked, and a zero-value control signal is given when the top, bottom, left, and right boundaries are detected. If it is segmented, the corresponding boundaries are checked based on the above information, and a zero-value control signal is given when the corresponding boundaries are detected.
[0018] Therefore, the detection of boundaries requiring data padding falls into four categories: top, bottom, left, and right. Calculation for each boundary case requires corresponding network layer information. The data padding control circuit is as follows... Figure 4 As shown.
[0019] (1) The upper boundary needs to be determined based on the number of rows in the feature map row block (row_tile), the stride of the convolution kernel, the number of rows (kr), and the number of padding rows (pad), according to the formula (row_tile*stride + kr) < pad. When this formula is satisfied, it is determined to be the upper boundary, and a zero-value control signal is output.
[0020] (2) The lower boundary requires all information from the upper boundary and the total number of rows of feature mapping, row, which is obtained according to the formula (row_tile*stride + kr) > row + pad - 1. When this formula is satisfied, it is determined to be the lower boundary, and a zero-value control signal is output.
[0021] (3) The left boundary is similar to the top boundary, and the number of rows needs to be modified to the corresponding number of columns. The left boundary needs to be determined based on the number of columns in the feature map column block col_tile, the convolution kernel stride and number of columns kc, and the number of padding rows pad, according to the formula (col_tile*stride + kc) < pad. When this formula is satisfied, it is judged as the left boundary, and a zero-value control signal is output.
[0022] (4) The right boundary is similar to the lower boundary, and the number of rows needs to be modified to the corresponding number of columns. The left boundary requires all information of the left boundary and the total number of columns col of the feature mapping, according to the formula (col_tile*stride + kc) > col + pad - 1. When this formula is satisfied, it is judged as the right boundary, and a zero-value control signal is output.
[0023] In all the above calculations, if the convolution kernel stride is 1, there are no multiplication calculations, only basic addition and comparison operations. Furthermore, the same calculations in the circuit design reuse the same arithmetic unit.
[0024] In addition, in any case, it is necessary to calculate the address and enable control signal to be given to the on-chip cache so that the data at the corresponding location of the on-chip cache can be output to the computing array.
[0025] 2.1.2 Data Filling and Transmission Control Module
[0026] Before data filling computation control and boundary detection, data needs to be transferred from memory to on-chip cache based on network information. Therefore, the data filling circuit also needs to provide control signals to the data transmission module. Similar to the control logic of the computation control module, it also needs to determine the correct control signal based on different network layer information. The flowchart of data filling transmission control is as follows: Figure 5 As shown.
[0027] First, read the network information to determine if the feature mapping data is segmented. If not segmented, transmit all data to the on-chip buffer. If segmented, further determine the specific line block. The specific transmission process is as follows:
[0028] (1) The starting line block does not need to transmit the data to be filled at the upper, left and right boundaries, but it needs to transmit the feature mapping data at the lower boundary.
[0029] (2) The end line block does not need to transmit the data to be filled at the lower, left and right boundaries, but it needs to transmit the feature mapping data at the upper boundary.
[0030] (3) The middle row block does not need to transmit the data to be filled on the left and right boundaries, but it needs to transmit the feature mapping data of the upper and lower boundaries.
[0031] Once the corresponding control signal is obtained based on the block division and row block determination, the control signal is sent to the data transmission module, and then data transmission is started to transfer the data at the corresponding memory location to the on-chip cache.
[0032] Therefore, the data filling circuit realizes the transmission of feature mapping data through the calculation control and transmission control modules, and fills the data into data that can be directly used for calculation by the calculation array according to the network information.
[0033] (1) This technical solution can significantly improve computational efficiency. The hardware circuit does not use the serialized traversal operation of software filling. By judging the position of feature mapping pixels in real time and generating zero values of filling synchronously, the filling process time is negligible, eliminating the speed difference between software filling and parallel convolution calculation, and significantly improving the overall operating efficiency of neural network hardware.
[0034] (2) Secondly, it effectively reduces memory bandwidth consumption. Since the hardware circuit only transmits the original valid data of the input feature mapping to the on-chip cache, there is no need to move the complete data containing invalid zero values from external memory to the on-chip cache, which fundamentally avoids the bandwidth occupation of invalid data.
[0035] (3) Finally, the on-chip cache requirement is greatly reduced. The on-chip cache only needs to store the original valid data and does not need to reserve extra space according to the padded size. This not only reduces the area occupied by the hardware chip and the manufacturing cost, but also reduces leakage power consumption due to the smaller cache size, which is in line with the core goal of high energy efficiency in hardware design and makes it possible for the miniaturization and low power consumption application scenarios of neural network hardware.
[0036] In addition, the circuit has good flexibility and can be adapted to the padding parameters of different network models (such as the number of padding layers and the type of padding values) by configuring registers. It is compatible with various neural network architectures such as CNN and Transformer, providing key support for the high-efficiency operation of deep neural network hardware. Attached Figure Description
[0037] Figure 1 Functional diagram of the data filling circuit
[0038] Figure 2 Data filling diagram
[0039] Figure 3 Flowchart of data filling calculation control
[0040] Figure 4 Data filling control circuit
[0041] Figure 5 Flowchart of data filling transmission control Detailed Implementation
[0042] The method, apparatus, and circuit for feature mapping data filling provided by the present invention will be described in detail below with reference to the accompanying drawings. This part is intended to enable any person skilled in the art to understand and implement the present invention. It is worth noting that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.
[0043] 3.1 Overall Architecture and Core Ideas
[0044] refer to Figure 1 It shows a functional diagram and connection relationship of the data filling circuit of the present invention in a neural network computing system.
[0045] The neural network computing system typically includes: a data transmission module, an on-chip cache, the data filling circuit of this invention, and a back-end computing array. The data filling circuit further includes a data filling transmission control module and a data filling computing control module.
[0046] The core idea of this invention lies in implementing the data padding operation, which was originally executed serially by software, through a dedicated hardware circuit. This circuit, based on known neural network layer information (such as feature map size, convolution kernel parameters, padding strategy, etc.), performs coordinated intelligent control during the data transfer stages from external memory to on-chip cache, and during the data output stages from on-chip cache to the computing array. Its two core mechanisms are:
[0047] (1) Transmission control: During the data transfer stage, the data filling transmission control module generates a control signal to instruct the data transmission module to read only valid feature mapping data from external memory, thus avoiding the transmission of invalid data from the source.
[0048] (2) Computation control: During the data supply computation stage, the data filling computation control module determines in real time what kind of data should be provided to the computing array. For valid data areas, it generates the correct address and enable signal and reads data from the on-chip cache; for boundary areas that need to be filled, it directly generates a zero-value control signal and outputs a zero-value data to the computing array.
[0049] Through the aforementioned collaborative mechanism of "avoiding during transmission and generating during computation," this invention completely eliminates the efficiency bottleneck of software padding and the waste of memory bandwidth, and significantly reduces the capacity requirements of on-chip cache.
[0050] 3.2 Detailed Implementation of the Data Filling Calculation Control Module
[0051] The data filling calculation control module is the key technology of the entire circuit. It is responsible for determining in real time whether each data point is valid data or a zero value that needs to be filled.
[0052] 3.2.1 Input Parameters and Basic Concepts
[0053] The input to this module is a series of pre-configured network layer parameters stored in the configuration register, which typically include:
[0054] - row: The total number of rows in the input feature map;
[0055] - col: The total number of columns in the input feature map;
[0056] - kr: Row size of the convolution kernel;
[0057] - kc: Column size of the convolution kernel;
[0058] - stride: The sliding stride of the convolution kernel;
[0059] - pad: The number of padding rings to be placed around the feature map;
[0060] - row_tile: The current row block index being processed;
[0061] - col_tile: The column block index currently being processed.
[0062] 3.2.2 Boundary Decision Logic and Circuit Implementation
[0063] refer to Figure 4 The core of the data filling calculation control module is four parallel boundary determination circuits, corresponding to the upper, lower, left, and right boundaries respectively.
[0064] (1) Upper boundary determination circuit
[0065] - Function: Determines whether the currently output data point is located in the top padding area of the feature map.
[0066] - Determination formula: (row_tile*stride + kr) < pad
[0067] - Circuit Implementation: This circuit includes a multiplier, an adder, and a comparator. It calculates `row_tile * stride` and adds the kernel row size `kr`, then compares it to the padding number `pad`. If the result is less than `pad`, it is considered the upper boundary, and a zero-value control signal is immediately output. For optimization, when `stride=1`, the multiplier is bypassed, and only the adder is used.
[0068] (2) Lower boundary determination circuit
[0069] - Function: Determines whether the currently output data point is located in the bottom padding area of the feature map.
[0070] - Determination formula: (row_tile*stride + kr) > row + pad - 1
[0071] - Circuit Implementation: Similar to the upper boundary circuit, but the other end of the comparison is (row + pad - 1). This circuit calculates whether the current row index plus kr has exceeded the last row after the original feature map plus padding (index starts from 0). If the condition is met, the lower boundary zero value control signal is output.
[0072] (3) Left boundary determination circuit
[0073] - Function: Determines whether the currently output data point is located in the left-hand padding area of the feature map.
[0074] - Judgment formula: (col_tile*stride + kc) < pad
[0075] - Circuit implementation: Its logic is completely symmetrical to the upper boundary determination circuit, except that the row parameters are replaced with column parameters (row_tile->col_tile, kr->kc, etc.).
[0076] (4) Right boundary determination circuit
[0077] - Function: Determines whether the currently output data point is located in the right-hand padding area of the feature map.
[0078] - Decision formula: (col_tile*stride + kc) > col + pad - 1
[0079] - Circuit implementation: Its logic is completely symmetrical to the lower boundary determination circuit, replacing the row parameters with column parameters.
[0080] 3.2.3 Control signal output
[0081] The outputs of these four boundary condition determination circuits are four independent zero-value flag signals. Logically, these signals are synthesized through an OR gate. As long as any one of the boundary conditions is met, the synthesized zero-value control signal is set to active.
[0082] Additionally, this module contains an address generation unit. This unit calculates the corresponding read address of the on-chip cache based on the current row / column index. When the address is valid and not currently within any boundary, it simultaneously generates a read enable signal for the on-chip cache.
[0083] Ultimately, these signals are fed into a multiplexer (MUX). The MUX has two data inputs: Input 0: the output data line from the on-chip buffer; Input 1: hardwired to logic '0'.
[0084] The selection terminal of the MUX is controlled by the synthesized zero-value control signal:
[0085] - When the zero control signal is invalid, select input 0 to output the valid data read from the on-chip cache to the computing array.
[0086] - When the zero-value control signal is valid, select input terminal 1 and output the zero value to the calculation array, simulating the effect of software filling.
[0087] 3.2.4 Control Flow
[0088] refer to Figure 3 The data filling calculation control flowchart shown below details the specific steps:
[0089] Step 1: The process starts after data begins to be transferred to the on-chip buffer.
[0090] Step 2: Determine whether the feature map is segmented. This determination is based on configuration parameters.
[0091] Step 3 (Unblocked Path): If the path is not divided into blocks, the four boundaries (top, bottom, left, and right) are determined sequentially. If any boundary condition is met, the process jumps to the calculation and outputs a zero-value control signal.
[0092] Step 4 (Block Path): If the block has been partitioned, the type of the current line block needs to be further determined: starting line block, middle line block, or ending line block.
[0093] Step 5 (Starting line block processing): If it is the starting line block, determine the top, left, and right boundaries. If any condition is met, jump to the calculation and output the zero-value control signal.
[0094] Step 6 (Ending Row Block Processing): If it is the end of a row block (i.e., row_tile == total_row_tiles - 1), then determine the bottom, left, and right boundaries. If any condition is met, jump to the calculation and output the zero-value control signal.
[0095] Step 7 (Middle Row Block Processing): If it is a middle row block, only the left and right boundaries are determined. If either condition is met, jump to the calculation and output the zero-value control signal.
[0096] Step 8: If, after all the above checks, the current data point does not belong to any boundary that needs to be filled, the zero control signal is invalid. At this time, the address generation unit calculates the correct on-chip cache address and issues a read enable signal.
[0097] The process repeats until all data in the entire feature map (or block) has been processed.
[0098] 3.3 Detailed Implementation of the Data Filling and Transmission Control Module
[0099] The data filling and transmission control module controls data transmission, and its decisions are based on network layer information similar to those of the computation control module.
[0100] refer to Figure 5 The data filling and transmission control flowchart shown below details the specific steps:
[0101] Step 1: The process begins by reading and parsing the network layer information configuration.
[0102] Step 2: Determine whether the feature mapping is segmented.
[0103] Step 3 (Unblocked Transmission): If the data is not blocked, a transmission instruction covering all valid data in the entire feature map is generated.
[0104] Step 4 (Clock Transmission Judgment): If the data has been divided into blocks, determine its type based on the current row block index.
[0105] Step 5 (Starting Row Block Transfer Strategy): For the starting row block, the areas that should have been filled at the top and left / right sides are skipped during transfer. Transfer instructions are generated only for the valid data area of this row block and the overlapping area at its bottom that may be used for the next block's calculation.
[0106] Step 6 (Ending Line Block Transmission Strategy): For the ending line block, the padding areas at its bottom and left and right sides are skipped during transmission. Transmission instructions are generated only for the valid data area of the line block and its top overlapping area.
[0107] Step 7 (Intermediate Row Block Transmission Strategy): For intermediate row blocks, the padding areas on the left and right sides are skipped during transmission. Transmission instructions are generated for the valid data area of the row block and its top and bottom overlapping areas.
[0108] Step 8: Send the generated transmission control signal to the data transmission module and start data transmission.
[0109] In this way, the on-chip cache always stores compact, zero-padded, and valid feature data, saving cache space and memory bandwidth.
[0110] 3.4 Application Example Analysis
[0111] To more clearly illustrate the working process of this invention, the following is combined with... Figure 2 The four data filling scenarios shown are illustrated with a specific example. Assumption:
[0112] - Input feature map size: row=5, col=5
[0113] - Kernel size: kr=3, kc=3
[0114] - Step size: stride=1
[0115] - Padding: pad=1 (meaning fill the four sides with a ring of zero values).
[0116] - Tile size: tile_height=3, tile_width=3 (This tile size is small for example)
[0117] Case 1: No block processing
[0118] like Figure 2 (a) shows the “unblocked” schematic diagram, where the entire 5x5 feature map is processed as a whole.
[0119] Transmission Control: The data filling transmission control module instructs the data transmission module to read the complete 5x5 valid data block from memory and transfer it to the on-chip buffer. At this point, the filling is logical, so there is no need to read the fill bits.
[0120] Computation Control: When the computing array needs data, the data filling computation control module starts running. For data targeting position (0,0) in the output, its corresponding input index is calculated to satisfy the upper and left boundary conditions, so the MUX directly outputs a zero value. For data targeting position (1,1), its corresponding input index is within the valid area, the data filling computation control module generates a buffer address, reads the actual data output. Ultimately, what is provided to the computing array is a logically 7x7 data stream with padding.
[0121] Case 2: Starting line block
[0122] like Figure 2 As shown in (b), process rows 1, 2, and 3.
[0123] Transmission Control: The transmission control module recognizes this as the starting block and does not transmit the data in the top virtual row 1 and the padding columns 1 and 7 on the left and right sides. It only transmits the valid data in columns 2, 3, 4, 5, and 6 of rows 2, 3, and 4.
[0124] Calculation control: When processing this block, the calculation control module will determine the first row as the upper boundary and output a zero value; the first column as the left boundary and output a zero value; and the seventh column as the right boundary and output a zero value.
[0125] Case 3: Middle row block
[0126] like Figure 2 As shown in (c), lines 2, 3, and 4 are processed.
[0127] Transmission control: The transmission control module skips the fill columns 1 and 7 on the left and right sides and transmits the valid data in the middle columns.
[0128] Calculation control: The calculation control module will not determine the upper and lower boundaries of any row in this block (because it is not the top or bottom), but it will determine the left and right boundaries of the 1st and 7th columns and output zero values.
[0129] Case 4: End of line block
[0130] like Figure 2 As shown in (d), lines 4, 5, and 6 are processed.
[0131] Transmission control: The transmission control module skips the bottom and left and right side padding data and only transmits the necessary valid rows.
[0132] Calculation control: The calculation control module determines the last line of this block as the lower boundary and outputs a zero value, and also outputs zero values for the left and right boundaries.
Claims
1. An apparatus for feature mapping data filling, characterized in that... The device includes a data filling calculation control module; at the same time, the data filling transmission control module, together with the corresponding data transmission module, moves the input data from memory to on-chip cache, thereby starting the neural network algorithm calculation. First, the data filling circuit calculates the transmission control signal through network information and sends it to the data transmission module. The data transmission module then transfers the memory data to the on-chip cache according to the control signal. Next, the data filling calculation control module receives the on-chip cache control signal or the fill zero signal and controls the multiplexer MUX to send the corresponding data to the computing array. The data filling calculation control module calculates the corresponding control signal based on the corresponding network layer information, which is used to control whether the data given to the computing array is filling data or on-chip cache data. If it is on-chip cache data, the corresponding address and enable control signal will also be given to the on-chip cache to ensure that the on-chip cache outputs the correct data; Depending on the network layer information, this module will output different control signals. Data padding is divided into four cases: if the feature map data is not segmented, then the four boundaries of the feature map (top, bottom, left, and right) need to be padded with 0, and other data is output through on-chip buffer; if the feature map data is segmented, then corresponding control signals need to be given according to the specific segment position, which is divided into three positions: start line block, middle line block, and end line block; the specific padding is as follows: (1) The starting line block needs to be filled with three boundaries, namely the top, left and right; (2) The middle row block needs to be filled with two boundaries, namely the left and right; (3) The ending line block needs to be filled with three boundaries, namely the bottom, left and right; After the data is transmitted to the on-chip buffer, it is first determined whether the feature mapping data of the network layer is divided into blocks. If there are no blocks, all boundaries are checked. When the top, bottom, left, and right boundaries are detected, a zero-value control signal is given. If there are blocks, the corresponding boundaries are checked based on the above information. When the corresponding boundaries are detected, a zero-value control signal is given. The detection requires data filling for four boundary cases: top, bottom, left, and right; the calculation of each boundary case requires the corresponding network layer information. (1) The upper boundary needs to be determined based on the number of rows in the feature mapping row block (row_tile), the stride of the convolution kernel, the number of rows (kr), and the number of padding rows (pad), according to the formula (row_tile*stride + kr) < pad; when the formula is satisfied, it is determined to be the upper boundary, and a zero-value control signal is output. (2) The lower boundary requires all the information of the upper boundary and the total number of rows of feature mapping, row, which is obtained according to the formula (row_tile*stride+ kr) > row + pad - 1; when the formula is satisfied, it is judged as the lower boundary and the zero value control signal is output. (3) The left boundary is similar to the upper boundary, and the number of rows needs to be modified to the corresponding number of columns. The left boundary needs to be obtained according to the number of columns of the feature mapping column block col_tile, the stride of the convolution kernel stride and the number of columns kc and the number of padding rows pad, according to the formula (col_tile*stride + kc) < pad. When the formula is satisfied, it is judged as the left boundary and the zero value control signal is output. (4) The right boundary is similar to the lower boundary, and the number of rows needs to be modified to the corresponding number of columns; the left boundary requires all information of the left boundary and the total number of columns of feature mapping col, according to the formula (col_tile*stride + kc) > col + pad - 1; when the formula is satisfied, it is judged as the right boundary and the zero value control signal is output. In all the above calculations, if the convolution kernel stride is 1, there is no multiplication calculation, only basic addition and comparison operations; at the same time, the same calculations in the circuit design reuse the same arithmetic unit. In any case, it is necessary to calculate the address and enable control signal to be given to the on-chip cache so that the data at the corresponding location of the on-chip cache can be output to the computing array; Before data filling calculation control and boundary detection, the data filling transmission control module also needs to transfer data from memory to on-chip cache according to network information. Therefore, the data filling circuit also needs to provide control signals to the data transmission module. First, read the network information to determine if the feature mapping data is segmented. If not segmented, transmit all data to the on-chip buffer. If segmented, further determine the specific line block. The specific transmission process is as follows: (1) The starting row block does not need to transmit the data to be filled at the top, left and right boundaries, but it needs to transmit the feature mapping data at the bottom boundary; (2) The end line block does not need to transmit the data to be filled at the bottom, left and right boundaries, but it needs to transmit the feature mapping data at the top boundary; (3) The middle row block does not need to transmit the data to be filled at the left and right boundaries, but it needs to transmit the feature mapping data at the upper and lower boundaries; Once the corresponding control signal is obtained based on the block division and row block determination, the control signal is sent to the data transmission module, and then data transmission is started to transfer the data at the corresponding memory location to the on-chip cache.