A configurable delay transient effect ring oscillator puf

Abstract

The application discloses a configurable delay transient effect ring oscillator PUF, comprising: two NAND gates, one input end of the first NAND gate and the second NAND gate is used for input of an enable signal; two groups of configurable delay units, each group of configurable delay units is composed of n series of configurable delay units, the output end of the first NAND gate is connected with the first group of configurable delay units, the output end of the first group of configurable delay units is connected with the other input end of the second NAND gate, the output end of the second NAND gate is connected with the second group of configurable delay units, and the output end of the second group of configurable delay units is connected with the other input end of the first NAND gate; wherein the configurable delay unit is configured to have different time delays based on an excitation signal configuration. By using the nonlinear dynamic behavior embodied by the period collapse count CTC in the TERO oscillation process, an excitation-related oscillation path configuration and adjustable delay mechanism are introduced, and a low-resource-overhead, high-nonlinear PUF architecture resisting modeling attacks is constructed.

Description

Technical Field

[0001] This invention belongs to the field of PUF circuit technology, and more specifically, this invention relates to a configurable delay transient effect ring oscillator (PUF). Background Technology

[0002] Physically Unclonable Functions (PUFs) are a class of hardware-based security primitives that leverage the inherent random manufacturing variations in CMOS processes to generate unique and unpredictable physical characteristics for each chip. When a PUF circuit is subjected to external stimuli, it outputs a corresponding challenge-response pair (CRP). The response originates from minute and uncontrollable process differences such as transistor threshold, circuit linewidth, and interconnect parasitic parameters. Therefore, different chips will produce different outputs under the same stimulus, forming a unique hardware "fingerprint." These random fluctuations generated during manufacturing possess inherent unpredictability and unclonability, forming the core support for the inherent characteristics of PUFs. Even if attackers use advanced physical attacks or reverse engineering techniques, they cannot accurately reconstruct its complex internal mechanisms at the physical level. This irreversible physical layer security feature makes PUFs a high-performance, highly reliable hardware security primitive in the IoT ecosystem, becoming a key source of trust for maintaining the authenticity of the identities of massive numbers of terminal devices.

[0003] Based on the spatial size of CRPs, Physically Unclonable Functions (PUFs) are generally divided into two main categories: Weak PUFs and Strong PUFs. The number of CRPs in Strong PUFs grows exponentially with circuit size, and they are widely used for authentication in IoT devices. Arbitrator PUFs (APUFs) are the earliest and most popular Strong PUF circuits, generating a large number of CRPs by selecting symmetric delay paths at each stage. To date, researchers have conducted extensive research on Strong PUFs, with the APUF being the most representative and widely used structure. APUFs generate a massive number of stimulus-response pairs (CRPs) by selecting symmetric delay paths at each stage. While its ingenious symmetric architecture facilitates the exponential expansion of CRPs, paradoxically, due to its underlying physical properties relying on a linear cumulative delay model, a significant linear correlation exists among the numerous CRPs in an APUF. After obtaining the CRPs of a PUF, an attacker can model the internal circuitry of the PUF through these internal correlations, thereby predicting other CRPs. Summary of the Invention

[0004] The present invention provides a configurable delay transient effect ring oscillator (PUF) aimed at solving at least one of the above-mentioned problems.

[0005] This invention is implemented as follows: a configurable delay transient effect ring oscillator (PUF), the PUF comprising:

[0006] Two NAND gates, including a first NAND gate and a second NAND gate, with one input of the first NAND gate and the second NAND gate used as the input of the enable signal;

[0007] Two sets of configurable delay units, each set of configurable delay units consists of n configurable delay units connected in series. The output of the first NAND gate is connected to the first set of configurable delay units, the output of the first set of configurable delay units is connected to the other input of the second NAND gate, the output of the second NAND gate is connected to the second set of configurable delay units, and the output of the second set of configurable delay units is connected to the other input of the first NAND gate.

[0008] The configurable delay unit is configured to have different time delays based on the excitation signal configuration.

[0009] Furthermore, the configurable delay unit includes configurable delay unit I and / or configurable delay unit II;

[0010] Among them, the configurable delay unit I and configurable delay unit II have different time delays under different excitation bits.

[0011] Furthermore, the configurable delay unit I includes:

[0012] The OR gate, AND gate, first XOR gate, and second XOR gate are connected to the inputs of the OR gate and the first XOR gate, respectively. The outputs of the OR gate and the first XOR gate are connected to the AND gate, and the outputs of the AND gate and the excitation signal output are connected to the second XOR gate.

[0013] Furthermore, the input excitation bit C i =1, the configurable delay unit I has an inverter function, and the input excitation bit C i =0, configurable delay unit I has a buffer function, wherein, configurable delay unit I in excitation bit C i When the time delay is 1, it is less than the excitation bit C. i =0.

[0014] Furthermore, the configurable delay unit II includes:

[0015] The AND gate, OR gate, first XNOR gate, and second XNOR gate are connected to the inputs of the AND gate and the first XNOR gate, respectively. The outputs of the AND gate and the first XNOR gate are connected to the OR gate, and the outputs of the OR gate and the excitation signal output are connected to the second XNOR gate.

[0016] Furthermore, the input excitation bit Ci =0, the configurable delay unit II has an inverter function, and the input excitation bit C i =1, the configurable delay unit II has a buffer function, wherein the configurable delay unit II in excitation bit C i The delay when =0 is less than the excitation bit C. i =1.

[0017] Furthermore, when the configurable delay unit includes configurable delay unit I and configurable delay unit II, delay unit I and configurable delay unit II are connected end to end.

[0018] This invention is implemented as follows: a method for selecting excitation signals based on a configurable delay transient effect ring oscillator (PUF), the method being as follows:

[0019] (1) Remove incentives that are sensitive to environmental fluctuations from the original incentive set;

[0020] (2) Extract the current adjacent incentives from the original incentive set in sequence. Calculate the current adjacent excitations The absolute value of the difference in the crash cycle count (CTC) under the basic environment;

[0021] (3) If the absolute value of the difference is less than the set difference threshold, then the incentive is deleted from the original incentive set. and incentives ,make Execute step (2) until the traversal of the original stimulus set is completed.

[0022] Furthermore, the specific method for determining the stimuli sensitive to environmental fluctuations is as follows:

[0023] Calculate the i-th incentive in the incentive set Environmental fluctuations In environmental fluctuations Greater than the environmental fluctuation tolerance threshold Then the incentive is recognized. Sensitivity to environmental fluctuations, among which environmental fluctuations The calculation formula is as follows:

[0024] ;

[0025] in, This indicates that the i-th incentive in the incentive set is in the basic environment. The number of crash cycles under the following conditions This indicates that the i-th incentive in the incentive set is in an extreme environment. The number of crash cycles is counted.

[0026] This invention utilizes the nonlinear dynamic behavior of the periodic collapse counting (CTC) during TERO oscillations, introduces excitation-related oscillation path configuration and adjustable delay mechanism, and constructs a low-resource-overhead, high-nonlinearity, anti-modeling-attack PUF architecture. In addition, to address the reliability issues that nonlinear structures may introduce under environmental fluctuations, a two-step reliability excitation selection strategy is proposed, which significantly improves response stability while ensuring safety. Attached Figure Description

[0027] Figure 1 A schematic diagram of the configurable delay transient effect ring oscillator (PUF) provided in an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of the structure of the configurable delay unit I provided in an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of the structure of the configurable delay unit II provided in an embodiment of the present invention;

[0030] Figure 4 A schematic diagram of the excitation bit configuration of configurable delay unit I and configurable delay unit II with inverter function provided in an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of the excitation bit configuration of the configurable delay unit I and configurable delay unit II with buffer function provided in an embodiment of the present invention. Detailed Implementation

[0032] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, so as to help those skilled in the art to have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention.

[0033] This invention proposes a nonlinear TERO-PUF circuit structure. By studying the nonlinear entropy source of a transient ring oscillator (TERO) under the drafting effect, it comprehensively improves the PUF's resistance to model attacks from both the circuit structure and response generation mechanism levels. Compared to traditional delay-based strong PUFs that mainly rely on linear delay accumulation and arbitration results as responses, this invention utilizes the nonlinear dynamic behavior embodied by the Collapse Time Count (CTC) during TERO oscillation, introduces excitation-related oscillation path configuration and adjustable delay mechanisms, and constructs a low-resource-cost, high-nonlinearity, model-attack-resistant PUF architecture. Furthermore, addressing the reliability issues that nonlinear structures may introduce under environmental fluctuations, a two-step reliability excitation selection strategy is proposed, significantly improving response stability while ensuring safety.

[0034] The core design of this architecture lies in fully utilizing and significantly amplifying minute static process variations within the devices. Compared to traditional structures, this invention introduces a configurable loop constructed from hybrid logic gates, dynamically reconstructing the circuit's logical topology and physical delay path using external excitation signals. More importantly, this invention leverages the physical structure characteristics of lookup tables (LUTs) in FPGAs to efficiently stimulate the stretching effect during oscillation.

[0035] Figure 1 This is a schematic diagram of the configurable delay transient effect ring oscillator (PUF) provided in an embodiment of the present invention. For ease of explanation, only the parts relevant to the embodiment of the present invention are shown. The PUF includes:

[0036] Two NAND gates, including a first NAND gate and a second NAND gate, with one input of the first NAND gate and the second NAND gate used as the input of the enable signal;

[0037] Two sets of configurable delay units are provided, each set consisting of n cascaded configurable delay units. The output of the first NAND gate is connected to the first set of configurable delay units, the output of the first set of configurable delay units is connected to the other input of the second NAND gate, the output of the second NAND gate is connected to the second set of configurable delay units, and the output of the second set of configurable delay units is connected to the other input of the first NAND gate. The configurable delay units are configured to have different time delays based on the excitation signal, and n is 32.

[0038] The overall PUF structure is as follows Figure 1 As shown, the excitation signal is sequentially input into a 32-stage CD-TERO-PUF circuit. Due to different excitation configurations, each configurable delay unit (CD unit) can exhibit different equivalent logic functions during transient oscillation. When the excitation bit takes different values, the logic gate combination inside the unit will dynamically be equivalent to two cascaded inverters or buffer structures, with different propagation delays. Thus, the excitation signal not only determines the logical function of the oscillation path but also introduces non-uniform and nonlinear delay disturbances at the physical level.

[0039] During the oscillation initiation phase, the enable signal is simultaneously injected into the loop under excitation and propagates along the configurable delay path. Influenced by both manufacturing process deviations and the stretching effect, the two signals continuously compete for dominance within the loop, forming a transient oscillation process. As the signal interval continuously decreases, the oscillation eventually terminates due to phase collapse. This invention counts the number of cycles (CTC) before oscillation collapse, compares the CTC values ​​under adjacent excitations (greater than the response value is 1, otherwise less than 0), and uses this as the response entropy source of the PUF to generate the final response bit.

[0040] In this embodiment of the invention, the configurable delay unit includes configurable delay unit I and / or configurable delay unit II, and the structure of configurable delay unit I is as follows: Figure 2 As shown, the configurable delay unit II is as follows: Figure 3 As shown, the structures of configurable delay unit I and configurable delay unit II are described below. Configurable delay unit I includes:

[0041] OR gate (A), AND gate (C), first XOR gate (B) and second XOR gate (D), the output of the previous configurable delay unit and the excitation signal output terminal are connected to the input terminals of OR gate (A) and first XOR gate (B); the output terminals of OR gate (A) and first XOR gate (B) are connected to AND gate (C), and the output terminal of AND gate (C) and excitation signal output terminal are connected to second XOR gate (D).

[0042] like Figure 4 Figure (a) in the middle Figure 4 As shown in Figure (b), when the excitation bit C of the input configurable delay unit I is... i =1. When the input signal IN=1, the output signal OUT of the configurable delay unit I is 0; when the excitation bit C of the configurable delay unit I is input... i =1. When the input signal IN=0, the output signal OUT of the configurable delay unit I is 1. Therefore, when the excitation bit C of the configurable delay unit I is input, the output signal OUT is 1. i =1, Configurable delay unit I has inverter function;

[0043] like Figure 5 Figure (a) in the middle Figure 5 As shown in Figure (b), when the excitation bit C of the configurable delay unit I is input... i =0, when the input signal IN=1, the output signal OUT of the configurable delay unit I is 1; when the excitation bit C of the configurable delay unit I is input... i =0, when the input signal IN=0, the output signal OUT of the configurable delay unit I is 0. Therefore, when the excitation bit C of the configurable delay unit I is input... i =0, configurable delay unit I has buffer function.

[0044] In this embodiment of the invention, the configurable delay unit II includes:

[0045] AND gate (A), OR gate (C), first XNOR gate (B) and second XNOR gate (D), the output terminal and excitation signal output terminal of the previous configurable delay unit are connected to the input terminals of AND gate (A) and first XNOR gate (B); the output terminals of AND gate (A) and first XNOR gate (B) are connected to OR gate (C), and the output terminal and excitation signal output terminal of OR gate (C) are connected to second XNOR gate (D).

[0046] like Figure 4 Figure (c) in the middle Figure 4 As shown in Figure (d), when the excitation bit C of the configurable delay unit II is input... i =0, when the input signal IN=1, the output signal OUT of the configurable delay unit II is 0; when the excitation bit C of the configurable delay unit II is input... i =0, when the input signal IN=0, the output signal OUT of the configurable delay unit II is 1. Therefore, when the excitation bit C of the configurable delay unit II is input... i =0, the configurable delay unit II has an inverter function;

[0047] like Figure 5 Figure (c) in the middle Figure 5 As shown in Figure (d), when the excitation bit C of the configurable delay unit II is input... i =1. When the input signal IN=1, the output signal OUT of the configurable delay unit II is 1; when the excitation bit C of the configurable delay unit II is input... i =1. When the input signal IN=0, the output signal OUT of the configurable delay unit II is 0. Therefore, when the excitation bit C of the configurable delay unit II is input... i =1, Configurable delay unit II has buffer function.

[0048] like Figure 4 As shown, when the excitation signal is configured to a low level, one input of the AND gate (A) in the configurable delay unit II is preset to logic "0", and its output is forced to clamp to a fixed level, so that the AND gate (A) of the upper path no longer participates in the dynamic switching process in this mode. At this time, the input signal mainly propagates along the lower path, is logically processed by the XOR gate (B), and is then output through the OR gate (C). Since the upper path is statically clamped, the entire three-stage cascaded structure is logically equivalent to an inverter. On the other hand, when the excitation signal is configured to a high level, one input of the OR gate (A) in the configurable delay unit I is preset to logic "1", and its output is also clamped to a fixed logic level, thereby suppressing the dynamic switching behavior of the upper path. At this time, the signal also mainly propagates through the XOR gate (B) of the lower path and is finally output through the AND gate (C), and the overall logical function is still equivalent to an inverter structure. Furthermore, in both configurations described above, since one input of the OR gate (C) or AND gate (C) is preset, its internal transistor network is in a pre-enabled state. When one input of the OR gate (C) is set to logic "1", some branches in its pull-down network are turned off in advance; while when one input of the AND gate (C) is set to logic "0", the number of series transistors in its pull-up or pull-down path is effectively reduced. These mechanisms collectively simplify the effective signal transmission path, reduce the parasitic capacitance charging and discharging overhead of internal nodes, and thus significantly reduce signal propagation delay, corresponding to a "low delay" operating state.

[0049] like Figure 5 As shown, when the excitation signal is configured to be low, the OR gate (A) of the upper path in configurable delay unit I is no longer in a clamped state, and its output must wait for the arrival of the dynamic input signal before completing the logic decision. Simultaneously, the lower path signal needs to be processed by the XOR gate (B) before participating in subsequent logic calculations together with the output of the upper path OR gate (A). When the excitation signal is configured to be high, the AND gate (A) of the upper path in configurable delay unit II is also in a non-clamped state, and its output depends on the real-time changes of the dynamic input signal. In this case, the lower path signal needs to pass through the XNOR gate (B) before driving the final logic result together with the output of the upper path AND gate (A). Under both configurations, signal propagation requires cascading switching of multiple logic gates, and the transistor networks inside the relevant logic gates are not in a pre-enabled state. The signal needs to complete a relatively complete charge charging and discharging process during propagation. This results in a significant increase in overall propagation delay, making the three-stage cascaded structure logically equivalent to a buffer structure, corresponding to a "large delay" operating state.

[0050] When the excitation signal of the OR gate (A) in configurable delay unit I is preset to C i When =1, some branches of its internal pull-down network are closed in advance, simplifying the transmission path of dynamic signals and reducing parasitic interference during charge charging and discharging, thereby reducing signal propagation delay; similarly, when one input of the AND gate (A) in the configurable delay unit II is preset to C... i When the value is 0, the internal logic node is in a pre-enabled state, which improves the signal propagation speed. This delay reduction caused by the configuration signal is not a simple linear bias, but rather a change in the operating point of the logic gate. In the LUT structure of an FPGA, this characteristic greatly improves the excitation efficiency of the stretching effect, causing tiny process deviations to be dramatically amplified under extremely short signal edge spacing. Ultimately, this endows TERO-PUF with extremely complex nonlinear mapping characteristics, significantly enhancing the system's resistance to modeling attacks.

[0051] For the overall circuit architecture, the logic '0' or '1' of the excitation input does not directly correspond to the simple switching of inverter or buffer functions, nor is it a linear relationship of increasing or decreasing delay. Instead, it is a complex nonlinear mapping mechanism. By dynamically adjusting the delay parameter through this mechanism, the key variable y in the stretching effect model can be changed, thereby efficiently stimulating the nonlinear characteristics in the transient oscillation process, nonlinearly amplifying small process deviations, thus breaking the linear correlation between excitation and response, and effectively resisting machine learning modeling attacks.

[0052] In TERO-PUF design, the stretching effect plays a crucial role in the oscillation process due to the difference in signal propagation speed caused by process variations. In a TERO loop, two signals propagate simultaneously. Because of the speed difference caused by process variations, the faster signal continuously catches up with the slower signal, creating a nonlinear dynamic process. During this process, the switching time of logic gates is no longer constant but is affected by the signal interval, causing the delay to change nonlinearly as the signal interval decreases. This phenomenon is called the "stretching effect." The stretching effect creates an extremely complex nonlinear relationship between the final number of oscillation cycles (CTC) and the static delay difference of the path, making the oscillation process even more unpredictable.

[0053] In this design, lookup tables (LUTs) in the FPGA are efficiently excited to enhance the stretching effect. Compared to standard ASIC cells, FPGA LUTs have more complex internal routing matrices and switching structures. When the excitation signal changes configuration, the capacitor charging and discharging paths and transistor switching combinations within the LUT change drastically. This dynamic reconfiguration characteristic makes it easier for the signal to trigger a deep stretching effect during the catch-up process, thereby prolonging the time the signal stays in the metastable region and making the signal behavior more unpredictable. Simultaneously, due to the limitations of FPGA routing resources, the interconnection delay between different LUTs exhibits significant randomness. Combined with the dynamic path selection mechanism, every change in the excitation signal guides the oscillating signal through different LUT paths and external interconnects, resulting in a nonlinear jump in the strength of the stretching effect under different excitation signals.

[0054] This nonlinear behavior significantly enhances the resistance of TERO-PUF to modeling attacks. Traditional strong PUFs, such as Arbitrator PUFs (APUFs), rely on a linear summation model of delay, which allows attackers to effectively fit delay features and make predictions using machine learning algorithms (such as logistic regression). In TERO-PUFs, however, the excitation signal not only determines the signal path but also introduces non-uniform delay perturbations by altering the logic function of the LUT. This nonlinear perturbation prevents the total delay from being simplified to a linear combination of feature vectors, thus violating the linear model assumption.

[0055] Furthermore, the efficient excitation of the LUT further enhances the stretching effect. The number of oscillations in the signal during the oscillation process is highly sensitive to minute delay differences, making it difficult even for high-dimensional neural networks (such as ANNs and DNNs) to accurately fit this nonlinear behavior with a limited training set. This high-dimensional nonlinear mapping ensures that the response of TERO-PUF is highly unpredictable against modeling attacks, making it difficult to breach its security even against complex machine learning models.

[0056] In summary, the proposed TERO-PUF, by combining a configurable logic architecture with the physical characteristics of LUTs, successfully transforms the transient nonlinear behavior of circuits into a security barrier resistant to modeling attacks, achieving a balance between low hardware overhead and high security.

[0057] In the proposed TERO-PUF, the oscillation process is dominated by the continuous phase competition between the two signals under the influence of the stretching effect. Unlike traditional structures, this design employs a highly complex logic mapping constructed from four FPGA LUTs in each delay unit, introducing more process variations into the path and significantly enhancing the excitation efficiency of the stretching effect. As the number of cascaded stages increases, random process deviations between different LUTs and their interconnect resources within the FPGA are amplified and accumulated stage by stage in the transmission path, forming a significant initial path delay mismatch. This cumulative effect not only prolongs the interaction time of the two signals during the "catch-up" process but also makes the phase evolution process of the oscillation stage more complete, macroscopically manifested as a significant lengthening of the oscillation period. For TERO-PUF, a longer oscillation path means that noise is averaged multiple times over a longer time scale, thus effectively suppressing the impact of noise on the response. In this structure, the large delay accumulation causes the oscillation period to converge rapidly in a nonlinear manner, resulting in the collapse cycle count (CTC) distribution being concentrated in a small and stable numerical range. Because the statistical fluctuations of the CTC (Collapse Cycle Count) are within a stable range and exhibit a long-tailed distribution, it is difficult to cause drastic fluctuations in the CTC, thus improving the original reliability. Therefore, without introducing additional error correction or compensation circuits, this structure achieves time averaging and nonlinear suppression of transient noise through delay series expansion and enhancement. This significantly reduces the random volatility of the CTC at the physical level, resulting in high stability of the response under most excitations.

[0058] Although the proposed TERO-PUF has high reliability at the structural level, a small number of CTCs still exhibit significant fluctuations under extreme PVT conditions, indicating high environmental sensitivity. Therefore, to improve the fault tolerance of CD-TERO-PUF, this invention proposes a reliability-aware bit selection strategy based on differential thresholding without altering the core PUF structure. This strategy is executed during the registration phase to filter out potentially unstable bits and generate a reliable bitmask, thereby further compressing the worst-case bit error rate with low hardware overhead.

[0059] This invention also provides a method for selecting the excitation signal of a configurable delay transient effect ring oscillator (PUF), the method being as follows:

[0060] (1) Remove incentives that are sensitive to environmental fluctuations from the incentive set;

[0061] To quantify and suppress the sensitivity of the TERO unit to environmental fluctuations, if the CTC amplitude under a certain excitation exceeds a preset threshold under both nominal and extreme stress conditions, it indicates that the unit is in an unstable region, has extremely high environmental sensitivity, and is very prone to output flipping.

[0062] First, a single incentive Environmental fluctuations for:

[0063] ;

[0064] in, This indicates that the i-th incentive in the incentive set is in the basic environment. The number of crash cycles under the following conditions This indicates that the i-th incentive in the incentive set is in an extreme environment. The crash cycle count under the following conditions, where the basic environment Typically at room temperature and standard voltage, extreme environments Typically, this is due to extreme temperature or extreme voltage stress.

[0065] exist At that time, motivation Assuming sufficient environmental stability, retain incentives. , Then the incentive is recognized. Sensitivity to environmental fluctuations; incentives are removed from the original incentive set. ,in, The environmental fluctuation tolerance threshold, such as 80, effectively suppresses the sensitivity to PVT changes.

[0066] (2) Extract the current adjacent incentives from the incentive set in sequence. Calculate the current adjacent excitations The absolute value of the difference in the crash cycle count (CTC) under the basic environment;

[0067] Since the response R of CD-TERO-PUF depends on adjacent excitations CTC difference sign When the difference is too small, even minor random noise or quantization error can change the sign, causing a bit flip error. Therefore, it is essential to ensure that the difference pairs have a sufficient safety threshold, i.e., to minimize bit errors caused by environmental fluctuations, by defining the differential threshold corresponding to the response bits. for:

[0068] ;

[0069] Among them, among them, This indicates that the (i+1)th incentive in the incentive set is in the basic environment. The number of crash cycles is counted.

[0070] (3) If the absolute value of the difference is less than the set difference threshold Then the incentive is removed from the original incentive set. and incentives ,make Execute step (2) until the traversal of the original stimulus set is completed.

[0071] Adjacent excitations Differential threshold corresponding to the response bit To prevent noise from causing a response flip, a minimum safe distance will be used. Setting the value to 40 filters out excitation pairs that are prone to causing abrupt response changes if they fall below the threshold of 40. After this double filtering, only excitation pairs that simultaneously satisfy low environmental sensitivity and high differential tolerance are retained, resulting in the final set of excitations. .

[0072] This invention proposes a nonlinear CD-TERO-PUF architecture based on a transient effect ring oscillator (TERO). Through a multi-stage cascaded delay structure based on an FPGA LUT, it fully amplifies and accumulates random process deviations while simultaneously achieving time averaging of transient noise during long-term oscillations, thereby effectively reducing the volatility of collapse cycle count (CTC). The nonlinear response generation mechanism based on CTC breaks the linear modeling assumption of traditional delay-based PUFs, significantly improving its resistance to machine learning modeling attacks. Combined with the proposed reliability-aware two-stage bit selection strategy, this PUF maintains high response stability even under voltage and temperature fluctuations.

[0073] The present invention has been described by way of example. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvements made using the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other occasions without modification, are all within the protection scope of the present invention.

Claims

1. A configurable delay transient effect ring oscillator (PUF), characterized in that, The PUF includes: Two NAND gates, including a first NAND gate and a second NAND gate, with one input of the first NAND gate and the second NAND gate used as the input of the enable signal; Two sets of configurable delay unit groups, each set of configurable delay unit groups consists of n configurable delay units connected in series. The output of the first NAND gate is connected to the input of the first set of configurable delay units. The output of the first set of configurable delay units is connected to the other input of the second NAND gate. The output of the second NAND gate is connected to the second set of configurable delay units. The output of the second set of configurable delay units is connected to the other input of the first NAND gate. The configurable delay unit is configured to have different time delays based on the excitation signal configuration; The configurable delay unit includes configurable delay unit I and / or configurable delay unit II; Among them, the configurable delay unit I and configurable delay unit II have different time delays under different excitation bits; Configurable delay unit I includes: The OR gate, AND gate, first XOR gate, and second XOR gate are connected to the inputs of the OR gate and the first XOR gate, respectively. The outputs of the OR gate and the first XOR gate are connected to the AND gate, and the outputs of the AND gate and the excitation signal output are connected to the second XOR gate. Input excitation bit C i =1, the configurable delay unit I has an inverter function, and the input excitation bit C i =0, configurable delay unit I has a buffer function, wherein, configurable delay unit I in excitation bit C i When the time delay is 1, it is less than the excitation bit C. i =0 delay; Configurable delay unit II includes: The AND gate, OR gate, first XNOR gate, and second XNOR gate are connected to the inputs of the AND gate and the first XNOR gate, respectively. The outputs of the AND gate and the first XNOR gate are connected to the OR gate, and the outputs of the OR gate and the excitation signal output are connected to the inputs of the second XNOR gate. Input excitation bit C i =0, the configurable delay unit II has an inverter function, and the input excitation bit C i =1, the configurable delay unit II has a buffer function, wherein the configurable delay unit II in excitation bit C i The delay when =0 is less than the excitation bit C. i =1 delay.

2. The configurable delay transient effect ring oscillator PUF as described in claim 1, characterized in that, When the configurable delay unit includes configurable delay unit I and configurable delay unit II, configurable delay unit I and configurable delay unit II are connected end to end.

3. A method for selecting the excitation signal of a configurable delay transient effect ring oscillator (PUF) as described in any one of claims 1 to 2, characterized in that, The method is as follows: (1) Remove incentives that are sensitive to environmental fluctuations from the original incentive set; (2) Extract the current adjacent incentives from the original incentive set in sequence. Calculate the current adjacent excitations The absolute value of the difference in the crash cycle count (CTC) under the basic environment; (3) If the absolute value of the difference is less than the set difference threshold, then the incentive is deleted from the original incentive set. and incentives ,make Execute step (2) until the traversal of the original stimulus set is completed.

4. The excitation signal selection method as described in claim 3, characterized in that, The specific method for determining the stimuli that are sensitive to environmental fluctuations is as follows: Calculate the i-th incentive in the incentive set Environmental fluctuations In environmental fluctuations Greater than the environmental tolerance threshold Then the incentive is recognized. Sensitivity to environmental fluctuations, among which environmental fluctuations The calculation formula is as follows: ； in, This indicates that the i-th incentive in the incentive set is in the basic environment. The number of crash cycles under the following conditions This indicates that the i-th incentive in the incentive set is in an extreme environment. The number of crash cycles under; Basic Environment For room temperature and standard voltage, extreme environments For extreme temperatures or extreme voltages.

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