A method for automatically generating positive and negative examples of DRC design rules based on a large language model and formal verification

CN122021489BActive Publication Date: 2026-07-03FUDAN UNIVERSITY

Patent Information

Authority / Receiving Office: CN · China
Patent Type: Patents(China)
Current Assignee / Owner: FUDAN UNIVERSITY
Filing Date: 2026-04-13
Publication Date: 2026-07-03

AI Technical Summary

Technical Problem

Existing technologies rely on manual processes to translate design rules into machine-readable scripts, which is error-prone and complex to verify. Furthermore, the accuracy of scripts generated by large language models is insufficient, and there is a lack of systematic automated solutions.

Method used

The system utilizes a large language model to transform natural language rules into logical expressions. It generates a test layout through logical decomposition and full Boolean space enumeration, and introduces a satisfiability modular theory solver and a context management mechanism to automatically generate positive and negative example labels and identify redundant rules.

Benefits of technology

It achieves precise formalization of rule semantics, improves the accuracy and coverage of automated verification, reduces the cost of manual intervention, and improves the generation efficiency and quality of DRC scripts.

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Abstract

The application discloses a DRC design rule positive and negative example automatic generation method based on a large language model and formal verification, relates to the field of electric digital data processing, and comprises the following steps: firstly, a large language model is utilized in combination with an entity library and a function library constructed, and natural language rules are accurately converted into logical expressions; then, logic is disassembled and full-coverage enumeration traversal of a Boolean algebra space is performed; subsequently, an SMT solver is introduced to construct a target optimization problem, automatically solve coordinates to generate a test layout close to a rule boundary, and assign clear positive and negative example labels; finally, through an innovative hierarchical context management mechanism, false positive false reports caused by multi-rule interference are excluded, and redundant rules are intelligently identified. The application greatly improves verification coverage and automation level, and can significantly reduce the labor cost of chip physical verification.

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