A Distributed Network Verification Method and System
By splitting the single-machine UVM verification environment into multiple sub-environments and distributing them on different simulation hosts, and utilizing the DPI mechanism and network communication interface to achieve cross-machine data interaction, the problem of single-machine resource limitations is solved, and efficient multi-chip cluster verification is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING SHUDU INFORMATION TECH CO LTD
- Filing Date
- 2026-04-09
- Publication Date
- 2026-07-17
AI Technical Summary
Existing digital chip verification methods are limited by the resources of a single machine, resulting in extended simulation time, inability to complete complex network verification, and inability to verify multi-chip cluster working scenarios. They also consume a lot of resources, and existing technologies cannot effectively solve these problems.
The single-machine UVM verification environment is split into multiple sub-verification environments, which are deployed on different simulation hosts. The verification components are modified using SystemVerilog's DPI mechanism, and an interactive channel across simulation hosts is established using a network communication interface to achieve distributed parallel computing and data interaction.
It breaks through the bottleneck of single-machine resources, shortens the simulation cycle, reduces the risk of tape-out, improves verification efficiency, supports verification in multi-chip cluster scenarios, and reduces hardware resource requirements and modification costs.
Smart Images
Figure CN122021496B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a distributed networking verification method and system, belonging to the field of chip verification technology. Background Technology
[0002] Existing digital chip verification methods primarily utilize the UVM environment. A corresponding verification environment is developed for the DUT (Device Under Test), consisting of various components that interact with it. Different stimulus sources are then activated to apply various stimuli to the DUT under different scenarios, performing simulations and checking the DUT's state during the simulation to determine if it meets expectations. This process aims to identify design bugs (defects) within the DUT. Before this verification process begins, simulation compilation tools such as VCS / XRUN / MODELSIM are used to compile the DUT and verification environment together to generate a binary executable file. This file is then executed to perform simulation testing.
[0003] However, existing technologies have many shortcomings:
[0004] 1) A test case must be run on one and only one machine. If the machine's hardware resources are insufficient, such as memory or CPU resources being scarce, the simulation time will be extended at best, and in severe cases, the simulation process will hang and the simulation test cannot be completed.
[0005] 2) Complex DUT networking verification cannot be achieved. Even simple networking verification will significantly increase the resource consumption of a single machine, further prolonging the simulation time and making it impossible to reproduce the cluster working scenario of the chip.
[0006] 3) Verification of simple networking scenarios requires rebuilding the verification environment, which further prolongs the compilation and simulation time.
[0007] Among the existing relevant patent documents, the "Multi-chip Link Management Method and Device in Multi-chip Verification Environment" published by CN120822474A can only run on a single machine for chip networking verification. It does not break through the single machine resource limit and cannot be realized when the chip simulation scale is too large. In addition, the information transmission between DUTs requires a third party to forward, resulting in low interaction efficiency.
[0008] The "Multi-threaded DPI task processing method, electronic device, and medium" disclosed in Publication No. CN120909741A aims to improve simulation efficiency. However, this method is based on multi-threading, which means it can only run on a single machine. Verification of multi-chip networks also adopts the traditional single-machine verification method.
[0009] Based on this, the present invention is proposed. Summary of the Invention
[0010] This invention provides a distributed network verification method and system, the specific technical solution of which is as follows:
[0011] Firstly, a distributed networking verification method is provided, applied to UVM simulation verification of digital chips, comprising the following steps:
[0012] Step 1: Provide a standalone UVM verification environment for the DUT. The standalone UVM verification environment includes multiple verification components that interact with the DUT, as well as the information transmission interface between the verification components and the DUT.
[0013] Step 2: Based on the networking verification requirements of the DUT, the single-machine UVM verification environment is divided into at least two sub-verification environments, which are deployed in different simulation hosts capable of network communication.
[0014] Step 3: For verification components that require cross-simulation host interaction in different sub-verification environments, modify the original verification components by calling the network communication interface through SystemVerilog's DPI mechanism, so that the modified verification components can realize cross-simulation host stimulus transmission and data reception.
[0015] Step 4: Establish cross-simulation host interaction channels between each simulation host based on a layered communication architecture. The layered communication architecture decouples the interaction between multiple verification environments from the underlying physical transmission.
[0016] Step 5: Simulate the simulation process of all simulation hosts synchronously. Each sub-verification environment realizes real-time data interaction through the cross-simulation host interaction channel to complete the distributed networking verification of the DUT.
[0017] The mechanism for synchronously starting the simulation processes of all simulation hosts is as follows:
[0018] For example, simulation commands on each simulation host can be called remotely simultaneously via external scripts, or handshake signals between simulation hosts can be used to ensure that all processes are ready before starting the simulation at the same time.
[0019] As a further improvement, the sub-verification environment described in step 2 is a copy of the original standalone UVM verification environment. Only the verification components that interact across simulation hosts are specifically modified, while the other components retain their original functions.
[0020] Further improvements include making the modified verification component in step 3 transparent to the business logic of the original single-machine UVM verification environment. The local signal processing logic of the original verification component does not need to be modified, and cross-machine data local processing is only achieved through the DPI bridging component.
[0021] The DPI bridging component is an interface component developed based on the SystemVerilog DPI mechanism. It includes a data conversion module, a network communication module, and a local signal adaptation module. It is used to modify the verification component and convert cross-machine data into local signal format to achieve local processing.
[0022] A further improvement is that the sub-verification environment includes a DUT and a cascaded interface component connected to the DUT;
[0023] In this case, at least one cascading interface component on the simulation host calls the network communication interface through the SystemVerilog DPI mechanism and is configured to send the output data of the local DUT to another simulation host over the network.
[0024] At least one cascading interface component on another simulation host calls the network communication interface through the SystemVerilog DPI mechanism, and is configured to receive data from other simulation hosts over the network and use it as stimuli to drive the local DUT.
[0025] Among them, the cascading interface component is a verification component that connects to the cascading interface of the DUT, including vip, uvm_agent or a dedicated interface driver module.
[0026] In a further improvement, in step 4, the underlying physical transmission medium includes TCP / IP sockets, shared memory, or semaphores.
[0027] As a further improvement, the network communication interface is a Socket API, and the modified verification component uses the Socket API to achieve bidirectional transmission of excitation and data between different simulation hosts.
[0028] A further improvement is that the layered communication architecture supports both distributed deployment across physical simulation hosts and parallel deployment of multiple processes within the same simulation host. Parallel deployment of multiple processes within the same simulation host uses shared memory as the underlying transmission medium, and resource isolation and synchronization between processes are achieved through semaphores.
[0029] A layered communication architecture can be designed to define a unified send / receive task at the verification environment layer, which calls different underlying driver functions to achieve the interchangeability of the transmission medium.
[0030] A further improvement is made where the DUT is a switch, which includes a USP and a DSP. The authentication component connected to the port is the authentication IP, i.e., the VIP. The VIP that needs to interact across simulation hosts is transformed into a VIP that supports SocketAPI through the DPI mechanism, so as to realize port data interaction between different switch DUTs.
[0031] Further improvements include deploying the sub-verification environment corresponding to each DUT on different simulation hosts when chip cluster scenario verification is required, adding a Socket API communication module to each sub-verification environment, building a distributed cluster verification environment, and realizing chip cluster networking test in the EDA simulation stage.
[0032] A further improvement is that the DUT is a digital chip module with a cascading interface, including a switch chip, a processor chip, or a bus bridge chip.
[0033] Secondly, a distributed network verification system includes at least two simulation hosts, sub-verification environments deployed in each simulation host, a cross-simulation host interaction channel, and a DPI bridging component; the sub-verification environment is obtained by splitting and copying a single-machine UVM verification environment, and the DPI bridging component is used to modify the verification component and realize local processing of cross-machine data; the cross-simulation host interaction channel is established based on a hierarchical communication architecture to realize real-time data transmission between each simulation host.
[0034] Thirdly, a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the aforementioned distributed network verification method.
[0035] The core of this invention lies in deploying multiple verification environments on different simulation hosts or computing nodes, establishing cross-simulation host interaction channels using network communication interfaces, and transmitting and receiving the split interface data in real time. This enables parallel computing and verification of ultra-large-scale systems or multi-chip verification scenarios through the collaborative work of multiple simulation hosts.
[0036] This invention decouples the interaction between multiple verification environments from the underlying physical transmission. This architecture is not limited to any specific underlying transmission mechanism and can support various communication methods such as TCP / IP sockets, shared memory, or semaphores. It supports flexible deployment topologies, including distributed deployment across physical simulation hosts and parallel deployment of multiple processes within the same simulation host.
[0037] This invention designs a bridging component based on SystemVerilog DPI. This bridging component is transparent to the actual SystemVerilog / UVM verification environment, allowing the verification environment, originally designed for single-machine simulation, to handle cross-machine data as if it were a local signal without modifying the business logic.
[0038] The beneficial effects of this invention are:
[0039] 1. Overcoming the bottleneck of single-machine resources: This invention distributes the computational workload of single-machine simulation to multiple machines in a distributed simulation manner. By using distributed parallel computing, it solves the problem of insufficient CPU and memory on a single machine, making multi-system-level verification of ultra-large-scale chips possible.
[0040] 2. Improve verification efficiency and shorten simulation cycle: Utilize the computing power advantage of multiple machines to achieve parallel simulation, which greatly shortens the operation cycle of the whole system simulation. At the same time, there is no need to rebuild the network verification environment. Only the single-machine environment is lightly modified, which reduces the overall compilation and simulation time.
[0041] 3. Verify cluster scenarios in advance to reduce tape-out risks: Cluster networking tests, which could only be conducted in hardware labs after chip delivery, can now be performed in the EDA simulation environment during the design phase. This means that deep-seated logical defects such as cross-chip level deadlocks, flow control errors, and protocol inconsistencies can be discovered and fixed in time before tape-out, greatly reducing the risk of tape-out failure and chip redesign costs.
[0042] 4. Reduce verification environment modification costs: The bridging component based on SystemVerilog DPI is transparent to the business logic of the original UVM environment. There is no need to modify the original verification logic. Only the components that interact across simulation hosts need to be modified, so as to realize the rapid reuse of single-machine environment.
[0043] 5. Supports flexible deployment and communication methods: The layered communication architecture decouples interaction from underlying transmission, supports multiple communication methods such as TCP / IP sockets and shared memory, supports deployment across physical simulation hosts as well as parallel deployment of multiple processes within the same simulation host, and adapts to different verification requirements. Attached Figure Description
[0044] Figure 1 This is a schematic diagram of the original single-machine verification method of testbench;
[0045] Figure 2 This is a schematic diagram of the distributed networking verification method of the present invention;
[0046] Figure 3 This is a schematic diagram of the DUT topology of the switch to be verified in this invention;
[0047] Figure 4 This is a schematic diagram of the verification tb for the switch DUT of the present invention;
[0048] Figure 5 This diagram illustrates two cluster verification environments applicable to this invention. Detailed Implementation
[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0050] Definitions of abbreviations and key terms.
[0051] switch: A hardware device used to expand bus connectivity.
[0052] USP: upstream port, the upstream port in a switch.
[0053] DSP: downstream port, the downstream port in a switch.
[0054] VIP: Verification IP, a component that can be reused for a specific bus's verification IP.
[0055] UVM: A general verification method.
[0056] Verification Components / Platforms: These are completed uvm_env, uvm_agent, uvm_component, etc., with specific functions. They can be stimulus sources that generate stimuli, management modules that monitor outputs, or detection modules that check whether the outputs meet requirements. Specifically: uvm_env: Verification environment; uvm_agent: Driver / monitor combination unit, a collection of components in UVM for specific protocols (such as PCIe, Ethernet); uvm_component: UVM component, the base class in the UVM tree structure, a permanent, hierarchical verification module.
[0057] PCIe: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard.
[0058] Ethernet: Ethernet network.
[0059] DUT: Module to be tested.
[0060] VCS / XRUN / MODELSIM: Compilation and simulation tools provided by different vendors.
[0061] memory: RAM (or memory storage).
[0062] CPU: Central Processing Unit.
[0063] tb: testbench, the verification environment.
[0064] interface: The information transmission interface between the verification component and the DUT.
[0065] HOST: The host machine that performs the simulation calculations; it can also be called the simulation host.
[0066] SystemVerilog: A programming language primarily used for chip simulation and verification.
[0067] Socket API: A network communication interface.
[0068] DPI: Direct Programming Interface.
[0069] TCP / IP: Transmission Control Protocol / Internet Protocol.
[0070] EDA: Electronic Design Automation, refers to the collective term for software tools and methods used to assist in completing tasks such as integrated circuit design, simulation, verification, placement and routing.
[0071] Single-machine simulation: a conventional verification method compared to distributed simulation.
[0072] Distributed simulation: This invention introduces a simulation method in which multiple machines cooperate with each other.
[0073] Example 1
[0074] Figure 1 This illustrates a conventional single-machine simulation verification method. The cascading interface of the DUT is the interface that connects to components 2 and 3. This DUT is quite large, and single-machine compilation / running has reached the hardware resource limit. If you want to perform network cascading simulation of the DUT, single-machine simulation is difficult to achieve.
[0075] Figure 1 It includes the DUT, Component 1, Component 2, Component 3, and Component 4 that interact with the DUT, as well as the information transmission interface between each component and the DUT. It is a conventional UVM single-machine verification architecture, and all components and the DUT are deployed in a single simulation host.
[0076] Components 1-4: Verification components in a standalone UVM verification environment, including excitation sources, monitoring modules, detection modules, etc.
[0077] Will Figure 1 The standalone UVM verification environment is copied twice, named Environment 1 and Environment 2 respectively. Environment 1 is deployed on HOST1, and Environment 2 is deployed on HOST2. The two simulation hosts are guaranteed to be interconnected via network. Figure 2 As shown.
[0078] Modify component 2 in HOST1: Use SystemVerilog's DPI mechanism to call the Socket API network communication interface, enabling component 2 to send the output stimulus of the local DUT to HOST2 via the network.
[0079] Modify component 3 in HOST2: use the same DPI mechanism to call the Socket API network communication interface, so that component 3 can receive the stimulus sent by component 2 in HOST1 and drive the stimulus to the local DUT of HOST2.
[0080] Due to the cascading requirements of the DUT, component 2 in HOST1, which connects to the DUT output interface, needs to be modified into a transmitter, and component 3 in HOST2, which connects to the DUT input interface, needs to be modified into a receiver.
[0081] A cross-emulation host interaction channel is established between HOST1 and HOST2 based on TCP / IP sockets, and the simulation processes of the two simulation hosts are started synchronously to complete the cascaded distributed verification of the two DUTs.
[0082] in, Figure 2 It includes two emulation hosts, HOST1 and HOST2. Both hosts are equipped with a complete sub-verification environment (components 1-4 + DUT + interface). Component 2 of HOST1 and component 3 of HOST2 have been modified using the DPI mechanism to add a Socket API. The two emulation hosts establish a cross-host interaction channel via the Socket API to achieve data transmission. Components 2 and 3 are cascaded interface components that connect to the DUT.
[0083] Example 2: Cross-emulation host cascading verification of switch DUT.
[0084] like Figure 3 The diagram shows a typical switch topology. Figure 3 In this example, switch1 and switch2 are the same DUT. This DUT can be cascaded to form a switch with a richer interface. Due to hardware resource limitations and to shorten simulation time, this embodiment is based on... Figure 3 Switch topology and Figure 4 The verification of the TB structure enables distributed network verification of the switch. Specific steps include:
[0085] like Figure 3 As shown, the DUTs to be verified are Switch1 and Switch2, both of which contain a USP and two DSPs. They need to be cascaded and networked for verification. Due to the limitations of single-machine resources, the distributed network verification method described in this invention is adopted.
[0086] Set up corresponding UVM standalone verification environments for switch1 and switch2 respectively. Deploy the verification environment of switch1 on simulation host A and the verification environment of switch2 on simulation host B. The two simulation hosts are interconnected by network.
[0087] Verification environment for switch1: The USP and DSP1 in switch1 are connected to a regular VIP. The VIP connected to DSP2 is modified through the DPI mechanism, and a Socket API is added so that it can send port data to switch2.
[0088] Verification environment for switch2: Modify the VIP connected to the USP in switch2 using the DPI mechanism, add a Socket API so that it can receive data sent by DSP2 of switch1. DSP1 and DSP2 are connected to regular VIPs.
[0089] Based on a hierarchical communication architecture, a cross-simulation host interaction channel is established between simulation host A and simulation host B through the Socket API, and the simulation processes of the two simulation hosts are started synchronously to complete the cascaded distributed verification of the switch.
[0090] Figure 3 It contains two switch DUTs, switch1 and switch2. Each switch contains one USP (upstream port) and two DSPs (downstream ports), which is a typical switch cascading topology and is a typical application DUT of this invention.
[0091] Figure 4 For adaptation Figure 3 The distributed verification environment deployment structure of the switch DUT topology modifies the VIPs connected to the switch ports using Socket API to enable cross-simulation host data interaction between switch1 and switch2. The VIPs connected to the switch's USP / DSP ports are cascaded interface components.
[0092] Example 3: EDA simulation verification in a chip cluster scenario.
[0093] This embodiment is based on Figure 5 The cluster verification environment advances the cluster testing scenario after chip siliconization to the EDA simulation stage. Specific steps include:
[0094] For actual cluster networking scenarios of chips, prepare multiple identical / different DUTs and build an independent UVM single-machine verification environment for each DUT.
[0095] The verification environment corresponding to each DUT is deployed on different simulation hosts, and all simulation hosts are guaranteed to be interconnected to form a distributed infrastructure.
[0096] Add a Socket API communication module to each verification component that requires cluster interaction in the verification environment, and realize cross-simulation host data interaction of components through the DPI mechanism;
[0097] Based on a hierarchical communication architecture, a multi-node Socket interaction channel is established among all simulation hosts to build a distributed chip cluster verification environment;
[0098] Simultaneously start the simulation process of all simulation hosts to simulate the cluster working scenario after chip silicon, complete the cluster networking verification in the EDA simulation stage, and detect deep logic defects such as deadlock, flow control error, and protocol inconsistency across chips.
[0099] Figure 5 It contains multiple DUTs, each deployed on a different simulation host. All DUTs establish a cluster connection through a Socket interaction channel to form a chip cluster verification environment, realizing cluster scenario simulation in the EDA stage.
[0100] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A distributed network verification method, characterized in that, Includes the following steps: Step 1: Provide a standalone UVM verification environment for the DUT. The standalone UVM verification environment includes multiple verification components that interact with the DUT, as well as the information transmission interface between the verification components and the DUT. Step 2: Based on the networking verification requirements of the DUT, the single-machine UVM verification environment is divided into at least two sub-verification environments, which are deployed in different simulation hosts capable of network communication. Step 3: For verification components that require cross-simulation host interaction in different sub-verification environments, modify the original verification components by calling the network communication interface through SystemVerilog's DPI mechanism, so that the modified verification components can realize cross-simulation host stimulus transmission and data reception. Step 4: Establish cross-simulation host interaction channels between each simulation host based on a layered communication architecture. The layered communication architecture decouples the interaction between multiple verification environments from the underlying physical transmission. Step 5: Simultaneously start the simulation process of all simulation hosts. Each sub-verification environment realizes real-time data interaction through the cross-simulation host interaction channel to complete the distributed networking verification of the DUT. In step 3, the modified verification component is transparent to the business logic of the original single-machine UVM verification environment. The local signal processing logic of the original verification component does not need to be modified. Cross-machine data local processing is only achieved through the DPI bridging component. The DPI bridging component is an interface component developed based on the SystemVerilog DPI mechanism. It includes a data conversion module, a network communication module, and a local signal adaptation module. It is used to modify the verification component and convert cross-machine data into local signal format to achieve localized processing.
2. The distributed network verification method according to claim 1, characterized in that: The sub-verification environment described in step 2 is a copy of the original standalone UVM verification environment. Only the verification components that interact across simulation hosts are modified, while the other components retain their original functions.
3. The distributed network verification method according to claim 1, characterized in that: The sub-verification environment includes a DUT and a cascaded interface component connected to the DUT; In this case, at least one cascading interface component on the simulation host calls the network communication interface through the SystemVerilog DPI mechanism and is configured to send the output data of the local DUT to another simulation host over the network. At least one cascading interface component on another simulation host calls the network communication interface through the SystemVerilog DPI mechanism, and is configured to receive data from other simulation hosts over the network and use it as stimuli to drive the local DUT.
4. The distributed network verification method according to claim 1, characterized in that: The network communication interface is a Socket API. The modified verification component uses the Socket API to achieve bidirectional transmission of excitation and data between different simulation hosts.
5. The distributed network verification method according to claim 1, characterized in that: The layered communication architecture supports both distributed deployment across physical simulation hosts and parallel deployment of multiple processes within the same simulation host.
6. A distributed network verification method according to any one of claims 1 to 5, characterized in that: The DUT is a switch, which includes a USP and a DSP. The verification component connected to the port is a VIP. The VIP that needs to interact across simulation hosts is modified to support Socket API through the DPI mechanism to realize port data interaction between different switch DUTs.
7. A distributed network verification method according to any one of claims 1 to 5, characterized in that: When chip cluster scenario verification is required, the sub-verification environment corresponding to each DUT is deployed on different simulation hosts, and a Socket API communication function module is added to each sub-verification environment to build a distributed cluster verification environment and realize chip cluster networking test in the EDA simulation stage.
8. The distributed network verification method according to claim 1, characterized in that: The DUT is a digital chip module with a cascading interface, including a switch chip, a processor chip, or a bus bridge chip.
9. A distributed network verification system, used to execute the distributed network verification method according to claim 1, characterized in that, It includes at least two simulation hosts, sub-verification environments deployed in each simulation host, cross-simulation host interaction channels, and DPI bridging components; the sub-verification environments are obtained by splitting and copying single-machine UVM verification environments, and the DPI bridging components are used to modify verification components and realize local processing of cross-machine data; the cross-simulation host interaction channels are established based on a hierarchical communication architecture to realize real-time data transmission between simulation hosts.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the distributed network verification method as described in any one of claims 1 to 8.