Semiconductor laser and method for manufacturing a semiconductor laser

Abstract

The embodiment of the present application provides a kind of semiconductor laser and the preparation method of semiconductor laser, it is related to optical chip technical field, the semiconductor laser includes epitaxial wafer, ridge waveguide, insulating medium layer and metal electrode.Ridge waveguide is arranged on epitaxial wafer. Insulating medium layer is arranged on epitaxial wafer, and at least cover ridge waveguide side wall layer.Metal electrode is arranged on ridge waveguide. At least part of the area of insulating medium layer is divided into multiple deposition sections, and the pre-stress σ of multiple deposition sections in non-working state is gradient distribution.Compared with prior art, the insulating medium layer of different pre-stress corresponding to different regions of the corresponding semiconductor laser is arranged in the present application, and the pre-stress is set as the function of working temperature T, the thermal strain of epitaxial wafer, insulating medium layer and metal electrode in working state can be compensated for, so the whole thermal strain compensation of device can be realized, so as to reduce the strain of device, improve the performance and long-term reliability of laser.

Description

Technical Field

[0001] This invention relates to the field of optical chip technology, and more specifically, to a semiconductor laser and a method for fabricating a semiconductor laser. Background Technology

[0002] Because semiconductor lasers typically have low-reflectivity and high-reflectivity coatings on both end faces, most light exits from the low-reflectivity cavity facet, leading to increased heat near the cavity facet. As the temperature rises, the overall strain of the device near the cavity facet also increases. Therefore, during operation, the cavity facet of a conventional semiconductor laser is prone to experiencing significant strain, which can affect laser performance and long-term reliability.

[0003] To address this, current solutions typically involve adding extra structural layers or rigid structures to regulate the stress on the laser, ensuring that the strain generated by the laser is within a reasonable range. This undoubtedly makes the overall laser structure more complex and makes it difficult to effectively reduce device strain. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor laser and a method for fabricating a semiconductor laser, which can achieve overall thermal strain compensation of the device by setting insulating dielectric layers with different stresses in different regions of the corresponding semiconductor laser, without the need for additional structural layers or rigid structures, thereby reducing device strain and improving laser performance and long-term reliability.

[0005] The embodiments of the present invention are implemented through the following scheme:

[0006] In one aspect, embodiments of the present invention provide a semiconductor laser, comprising:

[0007] The epitaxial wafer has a rear cavity surface and a front cavity surface along the cavity length direction;

[0008] A ridge waveguide disposed on the epitaxial wafer, the ridge waveguide extending from the rear cavity surface to the front cavity surface along the cavity length direction;

[0009] An insulating dielectric layer disposed on the epitaxial wafer and at least covering the sidewalls of the ridge waveguide, wherein the insulating dielectric layer extends from the rear cavity surface to the front cavity surface; and a metal electrode disposed on the ridge waveguide;

[0010] Wherein, at least a portion of the insulating dielectric layer is configured to be divided into multiple deposition segments along the cavity length direction, and the prestress σ of the multiple deposition segments in the non-working state is gradient distributed along the cavity length direction, and the prestress σ of each deposition segment is a function of the working temperature T, configured to compensate for the thermal strain of the epitaxial wafer, the insulating dielectric layer and the metal electrode in the working state, wherein the working temperature T is the temperature of the corresponding deposition segment in the working state;

[0011] The prestress σ is expressed as a function of the working temperature T as follows:

[0012] ;

[0013] in, The coefficient of thermal expansion of the insulating dielectric layer (150); The coefficient of thermal expansion of the epitaxial wafer (110) is given by the coefficient of thermal expansion. ΔT is the coefficient of thermal expansion of the metal electrode (170); ΔT is the difference between the working temperature T and the temperature T1 in the non-working state of the corresponding deposition section (151); The Young's modulus of the insulating dielectric layer (150); Thermal strain of the deposition section (151) The corresponding thermal strain of the metal electrode (170) and the corresponding thermal strain of the epitaxial wafer (110) The sum of the values. In an optional embodiment, the prestress σ of each deposition section is a function of the operating temperature T, and the operating temperature T of the plurality of deposition sections gradually increases along the length of the cavity, and the absolute value of the prestress σ of the plurality of deposition sections gradually increases along the length of the cavity.

[0014] In an optional implementation, the thermal strain of the deposition section The corresponding thermal strain of the metal electrode and the corresponding thermal strain of the epitaxial sheet. sum The absolute value is less than or equal to The thermal strain of the deposition section , The value is the Young's modulus of the insulating dielectric layer.

[0015] In an optional embodiment, the prestress σ satisfies the following formula:

[0016] ;

[0017] in, The coefficient of thermal expansion of the insulating dielectric layer; The coefficient of thermal expansion of the epitaxial wafer is denoted as . ΔT is the coefficient of thermal expansion of the metal electrode; ΔT is the difference between the working temperature T and the temperature T1 in the non-working state of the deposition section. The Young's modulus of the insulating dielectric layer.

[0018] In an optional embodiment, a portion of the insulating dielectric layer near the front cavity surface is configured to be divided into multiple deposition segments along the cavity length direction, with the first deposition segment along the cavity length direction spaced apart from the rear cavity surface, and the last deposition segment along the cavity length direction joined to the front cavity surface.

[0019] In an optional embodiment, the operating temperature T of the first deposition section along the cavity length direction is half of the temperature T2 of the front cavity surface in the operating state.

[0020] In an optional embodiment, the operating temperatures T of the plurality of deposition sections along the cavity length direction are arranged in an arithmetic sequence and / or a geometric sequence.

[0021] In an optional embodiment, the difference in prestress between adjacent deposition sections is less than 150 MPa.

[0022] In an optional embodiment, the insulating dielectric layer is a silicon dioxide film layer.

[0023] In an optional embodiment, the thickness of the insulating dielectric layer is less than 1 μm.

[0024] Secondly, embodiments of the present invention provide a method for fabricating a semiconductor laser, used to fabricate the aforementioned semiconductor laser, the method comprising:

[0025] Prepare an epitaxial wafer, wherein the epitaxial wafer has a rear cavity surface and a front cavity surface opposite each other along the cavity length direction;

[0026] A ridge waveguide is etched on the epitaxial wafer, wherein the ridge waveguide extends from the rear cavity surface to the front cavity surface along the cavity length direction;

[0027] An insulating dielectric layer is deposited on the epitaxial wafer to at least cover the sidewalls of the ridge waveguide, wherein the insulating dielectric layer extends from the rear cavity surface to the front cavity surface;

[0028] Metal electrodes are deposited on the ridge waveguide;

[0029] In this configuration, at least a portion of the insulating dielectric layer is divided into multiple deposition sections along the cavity length direction. The prestress σ of the multiple deposition sections in the non-working state is distributed in a gradient along the cavity length direction, and the prestress σ of each deposition section is a function of the working temperature T, which is the temperature of the corresponding deposition section in the working state.

[0030] In an optional embodiment, the step of depositing an insulating dielectric layer on the epitaxial wafer that at least covers the ridge waveguide sidewalls includes:

[0031] At least a portion of the surface of the epitaxial wafer is divided into multiple deposition regions along the cavity length direction;

[0032] The insulating dielectric layer is sequentially deposited in multiple deposition regions using a PT-PECVD process, such that at least a portion of the insulating dielectric layer is configured to be divided into multiple deposition segments along the cavity length direction;

[0033] Specifically, by controlling process parameters, each deposition section is given a prestress σ, the prestress σ of each deposition section is a function of the operating temperature T, and the operating temperature T of multiple deposition sections gradually increases along the cavity length direction, and the absolute value of the prestress σ of multiple deposition sections gradually increases along the cavity length direction.

[0034] In an optional embodiment, the deposition process parameters are as follows: SiH4 / He and N2O are used as plasma gas sources, RF is 13.56MHz, deposition temperature is 250℃-300℃, and deposition RF power is 20W-50W.

[0035] In an optional embodiment, the difference in prestress σ between adjacent deposition sections is less than or equal to a preset process value, so that the prestress σ between adjacent deposition sections transitions smoothly, wherein the preset process value is determined by process capability or stress tolerance; wherein, determining that the difference in prestress σ between adjacent deposition sections is less than or equal to the preset process value includes: determining the deposition section and its corresponding prestress σ; verifying the difference in prestress σ between adjacent deposition sections; when the difference in prestress σ between adjacent deposition sections is greater than the preset process value, dynamically adjusting the deposition section until the difference in prestress σ between adjacent deposition sections is less than or equal to the preset process value, and the prestress σ at the end of the deposition section before adjustment is equal to the prestress σ at the end of the deposition section after adjustment.

[0036] In an optional implementation, the preset process value is 150 MPa.

[0037] The beneficial effects of the embodiments of the present invention include:

[0038] This invention provides a semiconductor laser and its fabrication method. A ridge waveguide is formed on an epitaxial wafer, extending from the rear cavity surface to the front cavity surface along the cavity length direction. An insulating dielectric layer is disposed on the epitaxial wafer and at least covers the sidewalls of the ridge waveguide. A metal electrode is disposed on the ridge waveguide. At least a portion of the insulating dielectric layer is configured to be divided into multiple deposition segments along the cavity length direction. The prestress σ of each deposition segment in the non-operating state is gradient-distributed along the cavity length direction, and the prestress σ of each deposition segment is a function of the operating temperature T. This prestress is configured to compensate for the thermal strain of the epitaxial wafer, the insulating dielectric layer, and the metal electrode in the operating state. The operating temperature T is the temperature of the corresponding deposition segment in the operating state.

[0039] Compared to existing technologies, this invention sets different prestressed insulating dielectric layers for different regions of the semiconductor laser and sets the prestress as a function of the operating temperature T. Without additional structures, it can compensate for the thermal strain of the epitaxial wafer, insulating dielectric layer and metal electrode under the operating state using the essential film layers of the original semiconductor laser. Therefore, it can achieve overall thermal strain compensation of the device, thereby reducing device strain and improving laser performance and long-term reliability. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the semiconductor laser provided in an embodiment of the present invention from a first viewing angle;

[0042] Figure 2 This is a schematic diagram of the semiconductor laser provided in an embodiment of the present invention from a second perspective;

[0043] Figure 3 A schematic diagram of the temperature distribution of a semiconductor laser provided in an embodiment of the present invention.

[0044] Icons: 100 - Semiconductor laser; 110 - Epitaxial wafer; 111 - Front cavity surface; 113 - Back cavity surface; 130 - Ridge waveguide; 150 - Insulating dielectric layer; 151 - Deposition section; 170 - Metal electrode. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0047] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0048] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0049] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0050] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0051] See Figure 1 and Figure 2 The semiconductor laser 100 provided in this embodiment of the invention can achieve overall thermal strain compensation of the device by setting insulating dielectric layers 150 with different prestresses in different regions of the semiconductor laser, without the need for additional structural layers or rigid structures, thereby reducing device strain and improving laser performance and long-term reliability.

[0052] The semiconductor laser 100 provided in this embodiment of the invention includes an epitaxial wafer 110, a ridge waveguide 130, an insulating dielectric layer 150, and a metal electrode 170. The epitaxial wafer 110 has a rear cavity surface 113 and a front cavity surface 111 opposite each other along the cavity length direction. The ridge waveguide 130 is disposed on the epitaxial wafer 110 and extends from the rear cavity surface 113 to the front cavity surface 111 along the cavity length direction. The insulating dielectric layer 150 is disposed on the epitaxial wafer 110 and at least covers the sidewall layer of the ridge waveguide 130, wherein the insulating dielectric layer 150 extends from the rear cavity surface 113 to the front cavity surface 111. The metal electrode 170 is disposed on the ridge waveguide 130. In this embodiment, at least a portion of the insulating dielectric layer 150 is configured to be divided into multiple deposition segments 151 along the cavity length direction. The prestress σ of the multiple deposition segments 151 in the non-working state is distributed in a gradient along the cavity length direction, and the prestress σ of each deposition segment 151 is a function of the working temperature T. It is configured to compensate for the thermal strain of the epitaxial wafer 110, the insulating dielectric layer 150 and the metal electrode 170 in the working state. The working temperature T is the temperature of the corresponding deposition segment 151 in the working state.

[0053] It should be noted that, in this embodiment of the invention, the laser is divided into several regions along the cavity length, and an insulating dielectric layer 150 with different stresses is designed for each region according to the actual operating temperature of different regions during laser operation. Specifically, the design of the insulating dielectric layer 150 with a stress gradient distribution along the cavity length can be achieved by adjusting the material composition and process parameters of the insulating dielectric layer 150. Specifically, by changing the relevant parameters of the deposition process, the insulating dielectric layer 150 is given a preset gradient prestress, and the prestress is set as a function of the operating temperature T. This can compensate for the thermal strain of the epitaxial wafer 110, the insulating dielectric layer 150, and the metal electrode 170 under operating conditions, thus achieving overall thermal strain compensation of the device, thereby reducing device strain and improving laser performance and long-term reliability.

[0054] Therefore, when the laser is working, the temperature near the cavity surface rises, and the strain distribution at different locations of the overall device is uneven. The insulating dielectric layer 150 with stress gradient distribution can compensate for the uneven strain distribution, thereby achieving low strain in the overall structure when the laser is working and achieving uniform stress distribution at different locations of the laser in the working state.

[0055] In some embodiments, the prestress σ of each deposition section 151 is a function of the operating temperature T, and the operating temperature T of multiple deposition sections 151 gradually increases along the cavity length direction, and the absolute value of the prestress σ of multiple deposition sections 151 gradually increases along the cavity length direction. Specifically, based on the cavity temperature distribution during laser operation (e.g., Figure 3The laser can be divided into several regions (1, 2, 3…n), and the insulating dielectric layer 150 can be correspondingly divided into several deposition segments 151. Then, the average temperature (T1, T2, T3…Tn) in each region is calculated. It can be seen that the cavity temperature actually represents the temperature of the corresponding epitaxial wafer 110, and also the temperature of the insulating dielectric layer 150. Therefore, the temperature distribution map inside the cavity can also characterize the temperature distribution of the insulating dielectric layer 150. Thus, the operating temperature T of multiple deposition segments 151 gradually increases along the cavity length direction. Correspondingly, the absolute value of the prestress σ of multiple deposition segments 151 can be designed to gradually increase along the cavity length direction.

[0056] The cavity temperature can be obtained through the following methods: Step 1) Measure the actual temperature of the laser cavity surface during operation using a thermal reflection microscopy system. Since this method can only measure the surface temperature and not the overall temperature distribution, Step 2 can be performed. Step 2) Model the laser structure and perform thermal simulation to obtain the temperature distribution within the laser cavity. Step 3) Calculate the temperature at different locations within the cavity using the surface temperature and the simulated temperature distribution. Note that the method for detecting the cavity temperature here is merely a distance indicator and does not constitute a limitation. It should be noted that the temperature distribution here is based on a simulated structure; a functional expression can be determined based on the surface temperature to calculate the temperature at a specific location.

[0057] In some embodiments, a portion of the insulating dielectric layer 150 near the front cavity surface 111 is configured to be divided into multiple deposition segments 151 along the cavity length direction. The first deposition segment 151 along the cavity length direction is spaced apart from the rear cavity surface 113, and the last deposition segment 151 along the cavity length direction is joined to the front cavity surface 111. Specifically, a portion of the insulating dielectric layer 150 can be divided into multiple deposition segments 151. Since the uneven temperature inside the laser cavity is mainly concentrated near the front cavity surface 111, temperature division can be performed only on a portion of the laser; that is, temperature division is not required for areas where the strain does not exceed a preset value. The size of the preset value can be rationally selected by those skilled in the art according to the actual application scenario.

[0058] Furthermore, in some embodiments, the operating temperature T of the first deposition section 151 along the cavity length direction is half of the temperature T2 of the front cavity surface 111 in the operating state. Specifically, after obtaining the cavity temperature distribution by the above method, the region is divided at the position corresponding to half of the highest temperature in the cavity (i.e., the temperature at the front cavity surface 111) from the exposed surface (i.e., the front cavity surface 111).

[0059] In some embodiments, the operating temperatures T of multiple deposition segments 151 along the cavity length direction are arranged in an arithmetic and / or geometric sequence. Preferably, the operating temperatures T of multiple deposition segments 151 along the cavity length direction can be arranged in an arithmetic sequence by averaging temperature calculations. That is, the region of the laser (and the deposition segments 151) can be divided by equally spaced intervals of the cavity temperature and finding the corresponding cavity location. It should be understood that the determination of the deposition segments 151 can include pre-determination and final determination (i.e., after optimizing the pre-determination). In the pre-determination, the operating temperatures T of multiple deposition segments 151 along the cavity length direction are arranged in an arithmetic and / or geometric sequence, and in the final determination, the operating temperatures T of multiple deposition segments 151 along the cavity length direction can be arranged in an arithmetic and / or geometric sequence.

[0060] It should be noted that the division pattern of the laser region and / or deposition section 151 is not specifically limited here.

[0061] In some embodiments, the thermal strain of deposition section 151 The corresponding thermal strain of the metal electrode 170 And the corresponding thermal strain of epitaxial wafer 110 sum The absolute value is less than or equal to Thermal strain of sedimentary section 151 , The Young's modulus of the insulating dielectric layer is 150.

[0062] Specifically, according to the formula for thermal strain, the thermal strain at a certain location of a device is the sum of the strains of all parts of the device's material, i.e. Where CTE is the coefficient of thermal expansion of the material, and ΔT is the difference between the material's temperature during laser operation and room temperature (which can be considered as 25°C). The goal of this scheme is to ensure that the sum of the material strains in all parts of the device is close to zero during laser operation. .

[0063] Approximately, the overall thermal strain of the laser is the sum of the strains of the epitaxial wafer 110, the insulating dielectric layer 150, and the metal electrode 170. Therefore, when the device is operating, the temperature at a certain location is T. n The actual stress of the insulating dielectric layer 150 at that time is:

[0064] ;

[0065] in For the strain of epitaxial wafer 110, The strain of metal electrode 170. The coefficient of thermal expansion of the epitaxial wafer 110 is given. The coefficient of thermal expansion for the metal electrode is 170. The Young's modulus of the insulating dielectric layer is 150.

[0066] And due to Therefore, it can be further calculated that the actual stress of the insulating dielectric layer 150 at this location when the device is working must satisfy the following:

[0067] ;

[0068] Because typically, only the stress of the insulating dielectric layer 150 at room temperature (T=25°C) can be characterized during the design phase, while Wherein the prestress σ is It can be known that the prestress σ of the insulating dielectric layer at room temperature (150) satisfies the following formula:

[0069] ;

[0070] in, The coefficient of thermal expansion of the insulating dielectric layer is 150. The coefficient of thermal expansion of the epitaxial wafer 110; ΔT is the coefficient of thermal expansion of the metal electrode 170; ΔT is the difference between the working temperature T and the temperature T1 in the non-working state of the corresponding deposition section 151. The Young's modulus of the insulating dielectric layer is 150.

[0071] Based on the temperature at different locations within the laser cavity during operation (i.e., the operating temperature T of different deposition sections 151), the required prestress of the insulating dielectric layer 150 at different locations can be calculated. Different stresses can be achieved by adjusting the deposition-related parameters of the insulating dielectric layer 150. Furthermore, by repeating the three steps of growth, photolithography, and etching of the insulating dielectric layer 150, selective growth of the insulating dielectric layer 150 in each deposition section 151 can be achieved.

[0072] In addition, considering that if the stress difference between the insulating dielectric layer 150 of adjacent deposition areas is too large, it will affect or reduce the yield of the laser / chip in subsequent process flows, a prestress smooth transition can be set, that is, the difference in prestress between adjacent deposition sections 151 is less than 150 MPa.

[0073] In some embodiments, the insulating dielectric layer 150 is a silicon dioxide film layer, and the thickness of the insulating dielectric layer 150 is less than 1 μm. Of course, the material and thickness of the insulating dielectric layer 150 described here are merely illustrative examples and can be adjusted according to actual conditions, and do not serve as any limitation.

[0074] This invention also provides a method for fabricating a semiconductor laser 100, which includes the following steps:

[0075] S1: Prepare an epitaxial wafer 110, wherein the epitaxial wafer 110 has a rear cavity surface 113 and a front cavity surface 111 along the cavity length direction.

[0076] Specifically, epitaxial structures such as waveguides and quantum well active layers can be grown on the substrate, and their basic structure and fabrication principle can refer to the existing laser fabrication process.

[0077] S2: A ridge waveguide 130 is formed by etching on the epitaxial wafer 110, wherein the ridge waveguide 130 extends from the rear cavity surface 113 to the front cavity surface 111 along the cavity length direction.

[0078] Specifically, a wet etching process can be used to form a ridge waveguide 130 on the epitaxial wafer 110.

[0079] S3: An insulating dielectric layer 150 is deposited on the epitaxial wafer 110 to at least cover the sidewalls of the ridge waveguide 130, wherein the insulating dielectric layer 150 extends from the rear cavity surface 113 to the front cavity surface 111.

[0080] Specifically, during actual deposition, at least a portion of the surface of the epitaxial wafer 110 can first be divided into multiple deposition regions along the cavity length direction; then, an insulating dielectric layer 150 is sequentially deposited in the multiple deposition regions using PT-PECVD (Plasma Treatment - Plasma Enhanced Chemical Vapor Deposition) technology, so that at least a portion of the insulating dielectric layer 150 is configured to be divided into multiple deposition segments 151 along the cavity length direction; wherein, by controlling the process parameters, each deposition segment 151 has a prestress σ, the prestress σ of each deposition segment 151 is a function of the operating temperature T, and the operating temperature T of the multiple deposition segments 151 gradually increases along the cavity length direction, and the absolute value of the prestress σ of the multiple deposition segments 151 gradually increases along the cavity length direction.

[0081] After the actual deposition is completed, at least a portion of the insulating dielectric layer 150 is configured to be divided into multiple deposition sections 151 along the cavity length direction. The prestress σ of the multiple deposition sections 151 in the non-working state is distributed in a gradient along the cavity length direction, and the prestress σ of each deposition section 151 is a function of the working temperature T, which is the temperature of the corresponding deposition section 151 in the working state.

[0082] In practice, when depositing the insulating dielectric layer 150, the prestress of each deposition segment 151 can be calculated using the aforementioned formula. Then, the insulating dielectric layer 150 is formed using a PECVD deposition process. By adjusting process parameters such as the deposition composition, the magnitude and thickness of the prestress of the insulating dielectric layer 150 are determined. The insulating dielectric layer 150 for each deposition segment 151 can be prepared separately; that is, the dielectric film outside the deposition segment 151 can be removed by an etching process. To ensure etching accuracy, the etching results can be measured after each deposition and etching process in each deposition segment 151, ensuring that the etching depth error is less than 5%.

[0083] Specifically, the difference in prestress σ between adjacent depositional sections 151 is less than or equal to a preset process value, so as to ensure a smooth transition in prestress σ between adjacent depositional sections 151. The preset process value is determined by process capability or stress tolerance. Specifically, the preset process value is 150 MPa.

[0084] S4: Deposit a metal electrode 170 on the ridge waveguide 130.

[0085] Specifically, photolithography can be performed to etch electrode contact windows on the ridge waveguide 130, and electrode material can be deposited. The deposition process parameters are as follows: SiH4 / He and N2O are used as plasma gas sources, RF 13.56MHz; deposition temperature 250℃-330℃, preferably 250℃-300℃; deposition RF power 20W-80W, preferably 20W-50W.

[0086] The following section uses a 1550nm high-power laser as an example to illustrate the fabrication method in detail. In actual fabrication, the following steps can be used:

[0087] 1) Epitaxial structures such as waveguides and quantum well active layers are grown on an InP substrate to form an epitaxial wafer 110;

[0088] 2) A ridge waveguide 130 structure is formed on the epitaxial wafer 110. The process for forming the ridge waveguide 130 includes dry etching and wet etching.

[0089] 3) Divide the surface of the epitaxial wafer 110 into two deposition regions along the cavity length direction, namely region 1 and region 2;

[0090] 4) Calculate the average temperature of the two regions during laser operation based on empirical values ​​(or simulation values), for example, 30°C and 50°C respectively; here, a silicon oxide layer is used as the insulating dielectric layer 150, therefore its Young's modulus InP epitaxial material with a pressure of 270 GPa Metal electrode 170 The calculated prestress σ of the insulating dielectric layer 150 to be grown in region 1 must satisfy -30MPa≤σ≤-29MPa; the dielectric film stress to be grown in region 2 must satisfy -148MPa≤σ≤-147MPa.

[0091] 5) A silicon oxide layer was deposited using PECVD. First, a 100nm silicon oxide layer was deposited at a stress of -30MPa. After photolithography, the 100nm silicon oxide layer in region 2 was etched away using a photoresist mask, leaving only region 1 with silicon oxide. A second 100nm silicon oxide layer was deposited at a stress of -148MPa. After photolithography, the remaining 100nm silicon oxide layer outside region 2 was etched away using a photoresist mask. To ensure etching accuracy, the etching results were measured for each etching step, ensuring the etching depth error was less than 5%.

[0092] Considering that if the stress difference between the insulating dielectric layer 150 deposited in adjacent areas is too large, it will affect or reduce the yield of the chip in subsequent process flows, a smooth transition can be set, that is, the stress difference of silicon oxide in adjacent areas is limited to less than 150 MPa.

[0093] In one embodiment, to achieve a smooth transition of the insulating dielectric layer 150 and its prestress σ, a predetermined solution can be first determined. This involves designating the target semiconductor laser as a laser structure with a continuous temperature distribution T(z) along the axial direction (coordinate z∈[0,L]), requiring the deposition of a functional insulating dielectric layer 150 on its surface. Since material properties (such as refractive index) change with temperature, the stress of the ideal film should be a function of the operating temperature (T). The design goal is to determine the prestress σ while meeting subsequent constraints. Multiple prestresses σ should closely approximate the ideal stress curve, while also considering controllable manufacturing complexity and a smooth stress transition between adjacent regions at room temperature. Given the temperature distribution function or discrete temperature distribution data, the stress function of the prestress σ relative to the operating temperature T can be determined. During design, the temperature range can be divided into N continuous intervals: [T0,T1), [T1,T2)… [T…]. N 1,T N Then, a constant stress σ is assigned to each interval.

[0094] Among the constraints are smoothness constraints (to avoid abrupt stress changes): the prestress difference between adjacent regions should be less than Δ. max, where Δ The maximum value is determined by the process capability or stress tolerance, for example, it could be 150 MPa. The constraints also include a minimum partition scale constraint, where the physical length or temperature span of each temperature range (i.e., deposition segment 151) must not be less than a threshold. The final output must satisfy all constraints and the approximation error must be within an acceptable range.

[0095] In one embodiment, the method further includes, in achieving a smooth transition of the insulating dielectric layer 150 and its prestress σ:

[0096] Step Sa: Determine the stress value of the deposition section 151 and its corresponding insulating dielectric layer 150.

[0097] Specifically, step Sa includes the following steps: step Sa1: obtain the temperature distribution curve of the semiconductor laser along the cavity length direction; step Sa2: divide the cavity length direction into several deposition segments 151 according to the temperature gradient change characteristics; step Sa3: set the stress value of the corresponding insulating dielectric layer 150 for each deposition segment 151.

[0098] Step Sb: Stress difference verification of adjacent insulating dielectric layers 150.

[0099] Specifically, step Sb includes the following steps: Step Sb1: Determine the upper limit of the stress difference allowed by the process (i.e., the "preset value") as a standard for judging whether adjacent film layers are compatible; Step Sb2: Calculate the difference of prestress between any two adjacent deposition sections 151.

[0100] Step Sc: Dynamically adjust sedimentation section 151.

[0101] Specifically, the dynamic adjustment of the stress values ​​of the deposition section 151 and its corresponding insulating dielectric layer 150 includes the following situations: Sc1) Condition met (iteration terminated): If the stress difference between all adjacent insulating dielectric layers 150 is not greater than the preset value, it is determined that the current deposition section 151 scheme meets the process requirements, no further adjustment is made, and the final coating scheme is output; Sc2) Condition not met (subdivision triggered): If the stress difference between any two adjacent insulating dielectric layers 150 exceeds the preset value, it is determined that the step size of the current temperature partition is too large and cannot be smoothly transitioned; if it is determined that a smooth transition cannot be achieved, the two adjacent deposition sections 151 with excessive stress differences are re-divided according to a smaller temperature step size (or spatial step size).

[0102] Step Sd: Redistribute the prestress to the newly subdivided depositional section 151 and repeat step Sb.

[0103] Repeat steps Sa to Sd until the stress difference between all adjacent insulating dielectric layers 150 is controlled within the preset range.

[0104] It is important to understand that the preset value refers to the maximum allowable stress difference between adjacent film layers, which is determined by the adhesion of the film material and the bearing capacity of the substrate. Smaller temperature step size refers to reducing the original temperature range span during the subdivision process (for example, changing a 10℃ interval to a 5℃ interval), thereby making the stress change between adjacent deposition sections 151 more gradual.

[0105] The above implementation method introduces a stress difference threshold as a constraint condition. On the basis of ensuring process feasibility (smooth stress transition), it finds the deposition scheme of the minimum insulating dielectric layer 150 that meets the conditions through a stepwise subdivision strategy, thereby achieving a balance between process complexity and device performance.

[0106] In one embodiment, the method further includes: when it is detected that there is an excessive stress difference between the Nth sedimentary segment 151 and the (N+1)th sedimentary segment 151 (assuming there are M*N sedimentary segments 151, where M>1), performing the following "non-chain reaction" adjustment operation:

[0107] Step Sm: End prestress locking.

[0108] Specifically, this includes: locking the left boundary: strictly maintaining the starting point of the Nth sedimentary segment 151 (i.e., the Nth... The stress value at the boundary of sedimentary segment 151 remains unchanged; the right boundary is locked: the stress value at the termination end of sedimentary segment 151 (i.e., the boundary with sedimentary segment 151 of the (N+1)th) remains unchanged. This is to physically and logically break the chain reaction and ensure that this adjustment will never change N and N 1. The stress difference between N+1 and N+2.

[0109] Step Sn: Internal interpolation calculation.

[0110] Specifically, this includes: calculating the required transition stress sequence using the end stress of the Nth depositional segment 151 and the beginning stress of the N+1th depositional segment 151 as the starting and ending points; and determining the number k of transitional sub-depositional segments 151 to be inserted based on a preset threshold, so that the stress difference between adjacent transitional sub-depositional segments 151 is less than a preset value.

[0111] Step 10: Spatial subdivision and reorganization.

[0112] Specifically, this includes: inserting K calculated transition sub-depositional segments 151 at the boundary between the Nth and N+1th depositional segments 151; redistributing the physical spatial length of this local area, dismantling or compressing the original Nth and N+1th depositional segments 151 to accommodate the new transitional sequence.

[0113] 6) Perform photolithography and etch electrode contact windows on the ridges to deposit Ti / Au electrodes.

[0114] SiO2 film deposition can be performed using PT-PECVD, with SiH4 / He and N2O as the plasma gas source and RF at 13.56MHz. To ensure the requirements of INP-SiO2 interface states, film adhesion, and density, the deposition temperature is 250℃-300℃. The deposition RF power is 20-50W.

[0115] To avoid adhesion problems caused by changes in the insulating dielectric layer 150 and INP interface due to changes in gas composition during stress conditioning, an NH3·H2O:H2O ratio of 1:10 can be used, followed by a 120-second treatment. Pre-cleaning in the PECVD chamber using an N2 / N2O mixed gas for 2-5 minutes at an RF power of 30-50W is then performed. The stress conditioning process is shown in the table below.

[0116]

[0117] Among them, the composition determines the positive and negative, and the thickness determines the size; the thickness cannot be too thick, less than 1 micrometer, and the thickness can be adjusted within the limits of the composition.

[0118] In summary, this invention provides a semiconductor laser 100 and its fabrication method. A ridge waveguide 130 is formed on an epitaxial wafer 110, extending from the rear cavity surface 113 to the front cavity surface 111 along the cavity length direction. An insulating dielectric layer 150 is disposed on the epitaxial wafer 110 and at least covers the sidewalls of the ridge waveguide 130. A metal electrode 170 is disposed on the ridge waveguide 130. At least a portion of the insulating dielectric layer 150 is configured to be divided into multiple deposition segments 151 along the cavity length direction. The prestress σ of the multiple deposition segments 151 in the non-operating state is gradient-distributed along the cavity length direction, and the prestress σ of each deposition segment 151 is a function of the operating temperature T, configured to compensate for the thermal strain of the epitaxial wafer 110, the insulating dielectric layer 150, and the metal electrode 170 in the operating state. The operating temperature T is the temperature of the corresponding deposition segment 151 in the operating state. By dividing the laser along its cavity length into several regions, and designing insulating dielectric layers 150 with different stresses for each region based on the actual operating temperature of different regions during laser operation, the design of insulating dielectric layers 150 with stress gradient distribution along the cavity length is achieved by adjusting the material composition of the dielectric film. When the laser operates, the temperature near the cavity surface rises, resulting in uneven strain distribution at different locations of the overall device. The stress gradient distribution of the insulating dielectric layer 150 can compensate for this uneven strain distribution, thereby achieving low strain in the overall structure of the laser during operation. Compared to existing technologies, this invention, by setting relevant deposition process parameters to give the insulating dielectric layer 150 a preset gradient prestress, and setting the prestress as a function of the operating temperature T, can compensate for the thermal strain of the epitaxial wafer 110, the insulating dielectric layer 150, and the metal electrode 170 under operating conditions. Therefore, it can achieve overall thermal strain compensation of the device, thereby reducing device strain and improving laser performance and long-term reliability.

[0119] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor laser, characterized in that, include: The epitaxial wafer (110) has a rear cavity surface (113) and a front cavity surface (111) along the cavity length direction. A ridge waveguide (130) is disposed on the epitaxial wafer (110), the ridge waveguide (130) extending from the rear cavity surface (113) to the front cavity surface (111) along the cavity length direction. An insulating dielectric layer (150) disposed on the epitaxial wafer (110) and at least covering the sidewalls of the ridge waveguide (130), wherein the insulating dielectric layer (150) extends from the rear cavity surface (113) to the front cavity surface (111); and, Metal electrodes (170) are disposed on the ridge waveguide (130). In this configuration, at least a portion of the insulating dielectric layer (150) is divided into multiple deposition segments (151) along the cavity length direction. The prestress σ of the multiple deposition segments (151) in the non-working state is gradient distributed along the cavity length direction, and the prestress σ of each deposition segment (151) is a function of the working temperature T to compensate for the thermal strain of the epitaxial wafer (110), the insulating dielectric layer (150), and the metal electrode (170) in the working state, wherein the working temperature T is the temperature of the corresponding deposition segment (151) in the working state. The prestress σ is expressed as a function of the working temperature T as follows: ； in, The coefficient of thermal expansion of the insulating dielectric layer (150); The coefficient of thermal expansion of the epitaxial wafer (110) is given by the coefficient of thermal expansion. ΔT is the coefficient of thermal expansion of the metal electrode (170); ΔT is the difference between the working temperature T and the temperature T1 in the non-working state of the corresponding deposition section (151); The Young's modulus of the insulating dielectric layer (150) is given. Thermal strain of the deposition section (151) The corresponding thermal strain of the metal electrode (170) and the corresponding thermal strain of the epitaxial wafer (110) sum.

2. The semiconductor laser according to claim 1, characterized in that, The prestress σ of each of the deposition sections (151) is a function of the operating temperature T, and the operating temperature T of the plurality of deposition sections (151) gradually increases along the cavity length direction, and the absolute value of the prestress σ of the plurality of deposition sections (151) gradually increases along the cavity length direction.

3. The semiconductor laser according to claim 2, characterized in that, Thermal strain of the deposition section (151) The corresponding thermal strain of the metal electrode (170) and the corresponding thermal strain of the epitaxial wafer (110) sum The absolute value is less than or equal to The thermal strain of the deposition section (151) , The value is the Young's modulus of the insulating dielectric layer.

4. The semiconductor laser according to claim 3, characterized in that, The prestress σ satisfies the following formula: ； in, The coefficient of thermal expansion of the insulating dielectric layer (150); The coefficient of thermal expansion of the epitaxial wafer (110); ΔT is the coefficient of thermal expansion of the metal electrode (170); ΔT is the difference between the working temperature T and the temperature T1 of the corresponding deposition section (151) in the non-working state; The value is the Young's modulus of the insulating dielectric layer.

5. The semiconductor laser according to claim 2, characterized in that, A portion of the insulating dielectric layer (150) near the front cavity surface (111) is configured to be divided into multiple deposition segments (151) along the cavity length direction. The first deposition segment (151) along the cavity length direction is spaced apart from the rear cavity surface (113), and the last deposition segment (151) along the cavity length direction is joined to the front cavity surface (111).

6. The semiconductor laser according to claim 5, characterized in that, The operating temperature T of the first deposition section (151) along the cavity length direction is half of the temperature T2 of the front cavity surface (111) in the operating state; And / or, the operating temperatures T of the plurality of deposition sections (151) along the length of the cavity are arranged in an arithmetic sequence and / or a geometric sequence.

7. The semiconductor laser according to claim 1, characterized in that, The insulating dielectric layer (150) is a silicon dioxide film layer; And / or, the thickness of the insulating dielectric layer (150) is less than 1 μm.

8. A method for fabricating a semiconductor laser, used to fabricate the semiconductor laser as described in any one of claims 1 to 7, characterized in that, The preparation method includes: An epitaxial wafer (110) is prepared, wherein the epitaxial wafer (110) has a rear cavity surface (113) and a front cavity surface (111) along the cavity length direction. A ridge waveguide (130) is etched on the epitaxial wafer (110), wherein the ridge waveguide (130) extends from the rear cavity surface (113) to the front cavity surface (111) along the cavity length direction. An insulating dielectric layer (150) is deposited on the epitaxial wafer (110) to at least cover the sidewalls of the ridge waveguide (130), wherein the insulating dielectric layer (150) extends from the rear cavity surface (113) to the front cavity surface (111). A metal electrode (170) is deposited on the ridge waveguide (130). Wherein, at least a portion of the insulating dielectric layer (150) is configured to be divided into a plurality of deposition segments (151) along the cavity length direction, wherein the prestress σ of the plurality of deposition segments (151) in the non-working state is gradient distributed along the cavity length direction, and the prestress σ of each deposition segment (151) is a function of the working temperature T, wherein the working temperature T is the temperature of the corresponding deposition segment (151) in the working state; The prestress σ is expressed as a function of the working temperature T as follows: ； in, The coefficient of thermal expansion of the insulating dielectric layer (150); The coefficient of thermal expansion of the epitaxial wafer (110) is given by the coefficient of thermal expansion. ΔT is the coefficient of thermal expansion of the metal electrode (170); ΔT is the difference between the working temperature T and the temperature T1 in the non-working state of the corresponding deposition section (151); The Young's modulus of the insulating dielectric layer (150); Thermal strain of the deposition section (151) The corresponding thermal strain of the metal electrode (170) and the corresponding thermal strain of the epitaxial wafer (110) sum.

9. The method for fabricating a semiconductor laser according to claim 8, characterized in that, The step of depositing an insulating dielectric layer (150) on the epitaxial wafer (110) that at least covers the sidewalls of the ridge waveguide (130) includes: At least a portion of the surface of the epitaxial wafer (110) is divided into multiple deposition regions along the cavity length direction; The insulating dielectric layer (150) is sequentially deposited in multiple deposition regions such that at least a portion of the insulating dielectric layer (150) is configured to be divided into multiple deposition segments (151) along the cavity length direction. In this process, each deposition section (151) is given a prestress σ by controlling the deposition process parameters. The prestress σ of each deposition section (151) is a function of the working temperature T. The working temperature T of the multiple deposition sections (151) gradually increases along the cavity length direction, and the absolute value of the prestress σ of the multiple deposition sections (151) gradually increases along the cavity length direction.

10. The method for fabricating a semiconductor laser according to claim 9, characterized in that, The difference in prestress σ between adjacent deposition sections (151) is less than or equal to a preset process value, so that the prestress σ of adjacent deposition sections (151) transitions smoothly, wherein the preset process value is determined by process capability or stress tolerance. Wherein, the difference in prestress σ between adjacent deposition sections (151) is less than or equal to a preset process value, including: Determine the prestress σ of the deposition section (151); Verify the difference in prestress σ between adjacent depositional sections (151); When the difference in prestress σ between adjacent deposition sections (151) is greater than the predetermined process value, the deposition section (151) is dynamically adjusted until the difference in prestress σ between adjacent deposition sections (151) is less than or equal to the preset process value. The prestress σ at the end of the deposition section (151) before adjustment is equal to the prestress σ at the end of the deposition section (151) after adjustment.

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