A method and system for power factor correction of an LED power supply

Abstract

The application relates to the field of power electronics, and discloses a power factor correction method and system of an LED power supply. The method comprises the following steps: constructing an analog-digital hybrid control circuit based on a memristor, using the non-volatile resistance change characteristic of the memristor to adjust PFC loop parameters in real time; collecting operation state data and inputting the data into a control processor; using a genetic algorithm to optimize the configuration of the memristor by taking the power factor, total harmonic distortion rate and efficiency as fitness functions; dynamically applying a voltage pulse to accurately adjust the resistance value of the memristor; and continuously self-tuning based on closed-loop feedback. The system comprises a memristor programmable gain amplifier, a sensor, a control processor and a health monitoring module. Through the above scheme, the application realizes fast, fine and adaptive PFC parameter regulation at the hardware level, and improves the stability of the power factor, the system efficiency and the long-term reliability.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a power factor correction method and system for LED power supplies. Background Technology

[0002] In modern lighting and power electronics systems, LED drivers are key energy conversion devices, and their power quality directly affects grid stability and system energy efficiency. Power factor correction (PFC) technology is widely used to improve the synchronization between input current waveform and voltage to reduce harmonic pollution and meet international energy efficiency standards, and has become a core component in the design of high-performance LED power supplies.

[0003] PFC control strategies typically rely on preset analog or digital control parameters, such as voltage loop and current loop gains, and compensation network coefficients, to optimize the input power factor. However, in practical applications, these parameters often require fine-tuning for different load conditions, input voltage fluctuations, and ambient temperature changes. Traditional methods often use fixed parameters or rely on digital potentiometers for manual adjustment.

[0004] Existing technologies suffer from the following problems when dealing with complex operating conditions: manual debugging is time-consuming and difficult to cover the entire operating range, leading to performance degradation under non-standard operating conditions; conventional digital potentiometers suffer from slow response speed, coarse adjustment steps, and poor long-term stability, failing to support the high dynamic performance requirements of PFC control. Especially in applications with variable loads or wide input voltages, control parameter mismatch can easily cause current distortion, reduced efficiency, or even system instability, severely restricting the intelligence and adaptive capabilities of LED power supplies. Therefore, how to construct a hardware-level adaptive mechanism that can sense changes in operating conditions in real time and autonomously optimize PFC control parameters has become an urgent technical challenge to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a power factor correction method and system for LED power supplies, which can effectively solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides a power factor correction method for an LED power supply, comprising the following steps: A memristor-based analog-digital hybrid control circuit is constructed, in which a memristor array is embedded as a programmable resistor network in the power factor correction control loop for real-time adjustment of voltage loop gain, current loop gain and compensation network coefficients. The system collects power factor correction operating status parameters, acquires input voltage, input current, output voltage, output current and ambient temperature data through sensors, and converts all data into digital signals and sends them to the control processor. Genetic algorithms are used to optimize the memristor configuration. In the control processor, the initial resistance distribution of the memristor array is encoded, selected, crossed over, and mutated using power factor, total harmonic distortion, and system efficiency as fitness functions to generate the optimal resistance configuration scheme. Dynamically write to the memristor array, apply a voltage pulse sequence with specific amplitude and timing to the memristor array according to the optimal resistance configuration scheme, so that its resistance is precisely adjusted to the target value, thereby reconstructing the parameters of the power factor correction control loop; The system performs closed-loop feedback and continuous self-tuning, continuously monitoring the power factor correction performance during LED power supply operation. When changes in operating conditions are detected that cause a decrease in power factor or an increase in total harmonic distortion exceeding a preset threshold, a new round of genetic algorithm optimization and memristor reconfiguration is triggered.

[0007] Preferably, the memristor adopts a nanoscale thin film structure based on titanium dioxide or hafnium oxide, which has multi-level resistance state storage capability, resistance value variation range covers a predetermined range, response time is less than a preset time threshold, and durability is greater than a preset number of cycles.

[0008] Preferably, the analog-digital hybrid control circuit includes an analog front-end conditioning module, a memristor programmable gain amplifier, an analog-to-digital conversion interface, and a digital control logic unit, wherein the memristor programmable gain amplifier is directly integrated into the error amplifier feedback path of the power factor correction controller for dynamically adjusting the loop bandwidth and phase margin.

[0009] Preferably, the sensor includes an isolated voltage transformer, a Hall current sensor, and a digital temperature sensor, with a sampling frequency not less than a preset frequency threshold, voltage measurement accuracy within a preset error range, current measurement accuracy within a preset error range, and temperature resolution better than a preset temperature resolution threshold.

[0010] Preferably, the genetic algorithm uses a real number encoding method, where each memristor unit corresponds to a gene, and the gene value represents its target resistance value. The gene is normalized and mapped to a predetermined range, and then proportionally restored to the actual physical resistance value during the decoding stage.

[0011] Preferably, the fitness function of the genetic algorithm integrates three indicators: power factor, total harmonic distortion rate, and system efficiency. Each indicator is assigned a predetermined weight to guide parameter tuning to optimize energy efficiency while satisfying power quality requirements.

[0012] Preferably, the amplitude and pulse width of the voltage pulse sequence are dynamically determined based on the difference between the target resistance value and the current resistance value, and the application order is based on row and column addressing according to the physical position of the memristor unit in the array to avoid crosstalk effect, and the writing accuracy is controlled within the preset error range of the target resistance value.

[0013] Preferably, the preset threshold includes a power factor less than a preset power factor threshold or a total harmonic distortion rate greater than a preset distortion rate threshold. Once either indicator exceeds the limit, the system immediately starts the self-tuning process, and the entire optimization and reconfiguration cycle does not exceed a preset time threshold.

[0014] Preferably, it also includes a memristor health monitoring step, which periodically detects the resistance drift and failure of each memristor unit. When a unit is detected to have a resistance deviation greater than a preset deviation threshold or to be unable to respond to a write command, it is shielded from the available array and the unit's genes are automatically excluded from the genetic algorithm.

[0015] The present invention also provides a power factor correction system for an LED power supply, comprising: The analog-digital hybrid control circuit based on memristors includes a memristor array as a programmable resistor network, which is embedded in the power factor correction control loop to adjust the voltage loop gain, current loop gain and compensation network coefficient in real time. A multi-source sensing acquisition unit is used to acquire input voltage, input current, output voltage, output current and ambient temperature data; The control processor is used to execute a genetic algorithm to optimize the resistance distribution of the memristor array and generate the optimal resistance configuration scheme using power factor, total harmonic distortion rate and system efficiency as fitness functions. The memristor array driving module is used to apply a voltage pulse sequence to the memristor array according to the optimal resistance configuration scheme, so that its resistance is precisely adjusted to the target value. The closed-loop feedback and self-tuning module is used to continuously monitor the power factor correction performance index during the operation of the LED power supply, and trigger a new round of optimization and reconfiguration when the operating conditions are detected to cause the performance index to exceed the limit.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. By leveraging the programmable physical resistance of memristors, control parameter adjustment is moved from the software level to the hardware level, increasing response speed to the preset time level and finely adjusting step size to the predetermined order of magnitude, completely eliminating the need for manual adjustment; within a wide input voltage and full load range, the power factor is stably maintained above the preset high power factor threshold, and the total harmonic distortion is less than the preset distortion rate threshold, outperforming the performance fluctuations of existing technologies under non-standard operating conditions.

[0017] 2. The genetic algorithm has global search capabilities, which can effectively avoid local optima traps and dynamically match the best control curve; the non-volatility of the memristor array ensures that parameters are not lost after power failure. Combined with health monitoring and fault shielding mechanisms, after the system has been running continuously for a predetermined time in high temperature or high humidity environments, the control accuracy decay is less than the preset decay threshold, which far exceeds the stability performance of traditional digital potentiometers.

[0018] 3. By guiding parameter tuning through a multi-objective fitness function, the system efficiency is maximized while ensuring a high power factor, and the measured full-load efficiency is significantly improved. The closed-loop self-tuning mechanism enables the LED power supply to have autonomous sensing, decision-making and execution capabilities, and can adapt to grid fluctuations, load switching and aging effects without external intervention, providing a highly reliable energy interface for smart lighting and IoT terminals. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the overall technical solution architecture of the present invention; Figure 2 This is a schematic diagram of the core principle framework of the memristor-based analog-digital hybrid control circuit in this invention; Figure 3 This is a flowchart illustrating the logic of the genetic algorithm for optimizing memristor configuration in this invention. Figure 4 This is a schematic diagram of the multi-level interaction relationship and data flow of PFC operation status parameter acquisition and closed-loop feedback self-tuning in this invention; Figure 5 This is a logical flowchart of the dynamic writing and health monitoring mechanism for the memristor array in this invention. Figure 6 This is a schematic diagram of the multi-level interaction relationship and data flow between the non-volatile storage unit and the historical configuration recall strategy in this invention. Detailed Implementation

[0020] refer to Figures 1 to 6 To further illustrate the technical means and effects of the present invention in order to achieve the intended purpose, the following detailed description of the specific implementation methods, structures, features and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0021] Example 1: In modern intelligent lighting systems, LED power supplies need to maintain high power factor and low harmonic distortion continuously under wide input voltage ranges (85V to 265V AC), full load conditions (10% to 100% of rated power), and complex environments (-20℃ to +70℃). Traditional PFC controllers rely on fixed compensation networks or slow digital potentiometers, which are difficult to cope with parameter drift caused by grid fluctuations, load abrupt changes, and device aging. This example provides a hardware-level adaptive PFC correction scheme based on memristors and genetic algorithms to solve the above problems.

[0022] The overall system architecture is as follows Figure 1As shown, it includes a main power conversion module, a memristor-based analog-to-digital hybrid control circuit, a multi-source sensor acquisition unit, a control processor, a memristor array drive module, a health monitoring module, and a non-volatile storage unit. The core innovation lies in the deep integration of the memristor array into the PFC control loop, serving as a programmable resistor network to achieve real-time reconstruction of voltage loop gain, current loop gain, and compensation network coefficients.

[0023] First, a memristor-based analog-digital hybrid control circuit is constructed, the structure of which is as follows: Figure 2 As shown, this memristor-based analog-to-digital hybrid control circuit consists of an analog front-end conditioning module, a memristor programmable gain amplifier (MPGA), an analog-to-digital converter interface (ADCInterface), and a digital control logic unit. The memristor employs a nanoscale thin-film structure based on titanium dioxide (TiO2), with a single memristor unit size of 100nm × 100nm, a resistance range of 1kΩ to 100kΩ, a response time of less than 100 nanoseconds, and a durability greater than 10. 9 The memristor array features a multi-switch cycle and supports 256 levels of resistive state storage, with adjustable steps down to 390Ω. It comprises 64 independently addressable cells arranged in an 8×8 configuration and is monolithically integrated with the PFC controller using CMOS technology.

[0024] The memristor programmable gain amplifier is directly embedded in the error amplifier feedback path of the PFC controller. Specifically, the voltage loop error signal is transmitted via the first group of memristor units (M... 11 To M 18 The gain is set by an adjustable feedback resistor network consisting of a second set of memristors (M). The current loop error signal is then passed through the second set of memristor units (M). 21 To M 28 Adjusting the transconductance gain; the third group of memristor units (M 31 To M 38 This is used to construct the zero and pole locations of the second-order compensation network and dynamically adjust the loop bandwidth and phase margin. The resistance values ​​of all memristor cells are precisely controlled by externally applied voltage pulses, and their non-volatile characteristics ensure that the configuration is not lost after power failure.

[0025] Secondly, high-precision acquisition of PFC operating status parameters is performed. For example... Figure 4As shown, the system deploys three types of sensors: an isolated voltage transformer for measuring AC input voltage, with a measurement range of 0–300Vrms and an accuracy better than ±0.5%; a Hall current sensor for detecting input current, with a range of 0–5A and an accuracy better than ±1%; and a digital temperature sensor (such as DS18B20) mounted near the power MOSFET heatsink, with a temperature resolution of 0.0625℃. All sensors are uniformly set to a sampling frequency of 20kHz to meet the Nyquist sampling theorem's requirement for complete capture of the 50 / 60Hz fundamental frequency and its 50th harmonic. The acquired analog signals are filtered for anti-aliasing and then converted into digital signals by a 16-bit Σ-Δ ADC, which are then fed into a control processor (such as an ARM Cortex-M7 core microcontroller) for further processing.

[0026] Subsequently, the control processor executes a genetic algorithm to optimize the memristor configuration, the process of which is as follows: Figure 3 As shown. The algorithm initializes the population size to 50, the maximum number of iterations to 100 generations, sets the crossover probability to 0.85, and the mutation probability to 0.05. Each individual corresponds to a memristor array with a resistance configuration scheme, using real-number encoding: 64 memristor units correspond to 64 genes, and each gene value... Through linear mapping Restored to the actual physical resistance value. The fitness function F combines three indicators: ; PF is the measured power factor (range 0–1), and THD is the total harmonic distortion (range 0–1). For system efficiency (range 0–1). Weight allocation is as follows: This ensures that energy efficiency is considered while prioritizing power quality (high power factor, low total power consumption). The fitness of each generation of individuals is calculated by sampling after real-time injection of the current memristor configuration and running the PFC closed-loop system for 100ms.

[0027] Genetic operations included: selection using tournament selection (tournament size=3); and crossover using the simulated binary crossover (SBX) operator with a distribution index. The variation employs polynomial variation, with a distribution index of [missing information]. After a maximum of 100 generations of evolution, the algorithm outputs the optimal individual, which is a set of 64-dimensional target resistance vectors. .

[0028] Next, dynamic writing to the memristor array is performed. For example... Figure 5As shown, the control processor generates a voltage pulse sequence, which is applied to the memristor array through row and column drive circuits. Each memristor cell is located at the intersection of row and column lines, using passive matrix addressing. The write pulse amplitude ranges from 0.5V to 3.0V, and the pulse width ranges from 10ns to 1μs. The specific parameters are dynamically determined by looking up a table based on the difference between the target resistance value and the current resistance value. To avoid crosstalk between adjacent cells, the write order follows a "row-by-row scan, column-interval" strategy: first write the first row, columns 1, 3, 5, and 7, then write the first row, columns 2, 4, 6, and 8, and so on. After writing is complete, the system immediately reads back the resistance value of each cell to verify whether the error is within ±1%; if it exceeds the tolerance, the writing is repeated until convergence.

[0029] After initial configuration, the system enters the closed-loop feedback and continuous self-tuning phase. For example... Figure 4 As shown, the control processor continuously monitors PF and THD at 10ms intervals. The preset thresholds are: PF < 0.95 or THD > 10%. Once either indicator exceeds the limit, a new round of genetic algorithm optimization is immediately triggered. The entire self-tuning cycle (from detection to reconfiguration completion) is controlled within 500ms, which is sufficient to handle transient events such as load step changes (e.g., sudden switching on of LED lights) or input voltage drops (e.g., recovery from a momentary power grid interruption).

[0030] In addition, the system integrates a memristor health monitoring module. This module performs a full array resistance scan every 24 hours, recording the historical resistance trajectory of each cell. If a cell's resistance drift rate exceeds 0.1% / day, or if it fails to reach the target value within ±5% after three consecutive write instructions, it is identified as a failed cell. The address of the failed cell is written to a mask register, and its corresponding gene is automatically excluded in the subsequent genetic algorithm encoding. The remaining 63 cells continue to participate in optimization, ensuring the integrity of system functionality.

[0031] Finally, non-volatile memory units (such as FRAM or EEPROM) store the verified optimal configuration. The memory structure contains operating condition tags (input voltage range, load percentage, ambient temperature) and corresponding 64-dimensional resistance vectors. When the system restarts or detects a new operating condition with a matching degree >95% with historical operating conditions, the corresponding configuration is directly retrieved from the memory unit, skipping the genetic algorithm optimization process. This reduces startup time to less than 200ms, significantly improving the user experience.

[0032] Through the above mechanism, this embodiment achieves the following in laboratory tests: PF≥0.985, THD≤8%, and full-load efficiency of 94.2% under all operating conditions, which is 2.1 percentage points higher than the traditional fixed-parameter PFC solution. After aging at 70℃ for 1000 hours, the control accuracy decays by <0.5%, which is far superior to the 5% decay of the digital potentiometer solution.

[0033] Example 2: Building upon Example 1, this example proposes an enhanced memristor fault tolerance and multi-objective weight adaptive adjustment mechanism for high-reliability industrial lighting scenarios (such as underground mines and chemical plants). These high-reliability industrial lighting scenarios have extremely high requirements for long-term system stability and safety redundancy, and the power grid harmonic background is complex, necessitating the maintenance of PFC performance under extreme conditions.

[0034] Unlike Example 1, this example uses hafnium oxide. The base memristor has an extended resistance range of 500Ω–200kΩ, supports 1024 resistance states, and has an adjustment step fine to 195Ω. The memristor array size has been upgraded to 16×16 (256 units), divided into four functional subarrays: subarray A (64 units) is dedicated to voltage loop gain adjustment, subarray B (64 units) is used for current loop gain, subarray C (64 units) constructs a third-order compensation network, and subarray D (64 units) serves as a redundant backup unit.

[0035] The key difference lies in the introduction of a dynamic weight adjustment mechanism in the fitness function of the genetic algorithm. The system analyzes the input voltage spectrum in real time, and if the content of the 5th or 7th harmonic is detected to be greater than 5%, the THD weight is automatically increased. Reduce efficiency weight to Prioritize the suppression of specific subharmonics. The adjustment is implemented by the digital signal processing module through Fast Fourier Transform (FFT), with 1024 FFT points, a Hanning window function, and an update period of 100ms.

[0036] Furthermore, the health monitoring module has been upgraded to a predictive maintenance mechanism. In addition to resistance drift, it also monitors characteristic parameters such as the set / reset voltage offset of the memristor and the nonlinearity of the IV curve. Using a support vector machine (SVM) classifier trained on historical data, it predicts potential failure units 72 hours in advance. The prediction results trigger "preventive remapping": migrating the function of the unit about to fail to a healthy unit in the redundant subarray D, without waiting for complete failure.

[0037] In terms of the writing strategy, this embodiment employs the differential pulse writing method. For each target resistance value... First, a coarse adjustment pulse is applied to approximate the accuracy to within ±10%, and then multiple fine adjustment pulses (amplitude <0.3V, width <50ns) are applied to gradually converge the accuracy, improving the write accuracy to ±0.3%. At the same time, the cell current is monitored in real time during the write process. If an abnormal spike (>10μA) occurs, the operation is immediately terminated and the cell is marked as suspicious.

[0038] In the closed-loop self-tuning trigger condition, an "efficiency drop" criterion is added: if the system efficiency drops by more than 3 percentage points within 1 second, the optimization process is initiated even if the power factor (PF) and total electrical discharge (THD) do not exceed the limits, in order to deal with hidden faults such as heat dissipation failure or electrolytic capacitor aging.

[0039] Tests showed that under harsh conditions, including an input voltage containing 15% fifth harmonic and an ambient temperature of 85°C, this embodiment still maintained a power factor (PF) of ≥0.97 and a total harmonic density (THD) of ≤12%. Furthermore, even when a single memristor subarray completely failed, the system maintained basic power factor (PFC) functionality through redundant switching, with a PF of not less than 0.90, meeting industrial safety standards.

[0040] Example 3: This example is for low-cost consumer-grade LED driver power supplies, focusing on simplifying the hardware structure and reducing algorithm complexity while retaining core adaptive capabilities. It is suitable for cost-sensitive scenarios such as smart bulbs and table lamps that require ENERGYSTAR certification.

[0041] Unlike the previous two embodiments, this embodiment uses a 4×4 memristor array (16 units), adjusting only key parameters: 4 units for voltage loop gain, 4 units for current loop peak limiting threshold, and 8 units to form a first-order compensation network. A simplified version of the memristor is used. The structure features a resistance range of 2kΩ–50kΩ, supports 64 levels of resistance, and has a response time relaxed to 500ns to reduce manufacturing costs.

[0042] The genetic algorithm is significantly simplified: the population size is reduced to 20, the maximum number of iterations is 30, and binary encoding replaces real number encoding. Each memristor unit is represented by a 6-bit binary number. The gene length is 96 bits. The fitness function retains only the PF and THD terms, with fixed weights. , The efficiency term was removed to reduce the burden of real-time sampling.

[0043] For parameter acquisition, the independent temperature sensor was eliminated and replaced with an internal temperature sensor of the microcontroller (accuracy ±2℃); current sampling adopted a low-cost shunt resistor in conjunction with a 12-bit ADC, with an accuracy of ±2%. The sampling frequency was reduced to 5kHz to capture only the fundamental frequency and major low-order harmonics.

[0044] The self-tuning trigger mechanism has been changed to event-driven: optimization is only initiated when the system is powered on, the load change is greater than 20%, or the input voltage crosses the 110V / 220V threshold. No periodic monitoring is performed during daily operation, which significantly reduces the processor load.

[0045] Non-volatile storage only saves three typical operating condition configurations: light load (<30%), half load (30%–70%), and heavy load (>70%). After each optimization, the corresponding configuration is automatically categorized and overwritten based on the current load.

[0046] Despite the hardware simplification, this embodiment still achieves PF≥0.96 and THD≤15% under standard testing conditions, meeting the ENERGYSTARV2.1 requirements, and the BOM cost is reduced by 40% compared to Embodiment 1, making it suitable for the large-scale consumer market.

[0047] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

[0048] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0049] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A power factor correction method for an LED power supply, characterized in that, Includes the following steps: A memristor-based analog-digital hybrid control circuit is constructed, in which a memristor array is embedded as a programmable resistor network in the power factor correction control loop for real-time adjustment of voltage loop gain, current loop gain and compensation network coefficients. The system collects power factor correction operating status parameters, acquires input voltage, input current, output voltage, output current and ambient temperature data through sensors, and converts all data into digital signals to be sent to the control processor. Genetic algorithms are used to optimize the memristor configuration. In the control processor, the initial resistance distribution of the memristor array is encoded, selected, crossed over, and mutated using power factor, total harmonic distortion, and system efficiency as fitness functions to generate the optimal resistance configuration scheme. Dynamically write to the memristor array, apply a voltage pulse sequence with specific amplitude and timing to the memristor array according to the optimal resistance configuration scheme, so that its resistance is precisely adjusted to the target value, thereby reconstructing the parameters of the power factor correction control loop; The system performs closed-loop feedback and continuous self-tuning, continuously monitoring the power factor correction performance index during the operation of the LED power supply. When a change in operating conditions is detected that causes a decrease in power factor or an increase in total harmonic distortion rate that exceeds a preset threshold, a new round of genetic algorithm optimization and memristor reconfiguration is triggered. The analog-digital hybrid control circuit includes an analog front-end conditioning module, a memristor programmable gain amplifier, an analog-to-digital converter interface, and a digital control logic unit. The memristor programmable gain amplifier is directly integrated into the error amplifier feedback path of the power factor correction controller for dynamically adjusting the loop bandwidth and phase margin. The genetic algorithm uses a real-number encoding method, with each memristor unit corresponding to a gene. The gene value represents its target resistance value, which is normalized and mapped to a predetermined range, and then proportionally restored to the actual physical resistance value during the decoding stage. The fitness function of the genetic algorithm integrates three indicators: power factor, total harmonic distortion rate, and system efficiency. Each indicator is allocated according to a predetermined weight to guide parameter tuning to optimize energy efficiency while meeting power quality requirements. The preset thresholds include a preset power factor threshold or a preset distortion rate threshold. Once either indicator exceeds the limit, the system immediately initiates a self-tuning process, and the entire optimization and reconfiguration cycle does not exceed a preset time threshold.

2. The power factor correction method for an LED power supply according to claim 1, characterized in that, The memristor adopts a nanoscale thin film structure based on titanium dioxide or hafnium oxide, which has multi-level resistance state storage capability, resistance value variation range covers a predetermined range, response time is less than a preset time threshold, and durability is greater than a preset number of cycles.

3. The power factor correction method for an LED power supply according to claim 2, characterized in that, The sensor includes an isolated voltage transformer, a Hall current sensor, and a digital temperature sensor. The sampling frequency is not less than a preset frequency threshold, the voltage measurement accuracy is within a preset error range, the current measurement accuracy is within a preset error range, and the temperature resolution is better than a preset temperature resolution threshold.

4. The power factor correction method for an LED power supply according to claim 3, characterized in that, The amplitude and pulse width of the voltage pulse sequence are dynamically determined based on the difference between the target resistance value and the current resistance value. The application order is based on row and column addressing according to the physical position of the memristor unit in the array to avoid crosstalk effects. The write accuracy is controlled within the preset error range of the target resistance value.

5. The power factor correction method for an LED power supply according to claim 4, characterized in that, It also includes a memristor health monitoring step, which periodically detects the resistance drift and failure of each memristor cell. When a cell's resistance deviation is found to be greater than a preset deviation threshold or it cannot respond to a write command, it is shielded from the available array, and the cell's genes are automatically excluded from the genetic algorithm.

6. A power factor correction system for an LED power supply, characterized in that, include: The analog-digital hybrid control circuit based on memristors includes a memristor array as a programmable resistor network, which is embedded in the power factor correction control loop to adjust the voltage loop gain, current loop gain and compensation network coefficients in real time. A multi-source sensing acquisition unit is used to acquire input voltage, input current, output voltage, output current and ambient temperature data; The control processor is used to execute a genetic algorithm to optimize the resistance distribution of the memristor array and generate the optimal resistance configuration scheme using power factor, total harmonic distortion rate and system efficiency as fitness functions. The memristor array driving module is used to apply a voltage pulse sequence to the memristor array according to the optimal resistance configuration scheme, so that its resistance is precisely adjusted to the target value. The closed-loop feedback and self-tuning module is used to continuously monitor the power factor correction performance index during the operation of the LED power supply. When the power factor decreases or the total harmonic distortion rate increases beyond the preset threshold due to changes in operating conditions, a new round of genetic algorithm optimization and memristor reconfiguration is triggered. The analog-digital hybrid control circuit includes an analog front-end conditioning module, a memristor programmable gain amplifier, an analog-to-digital converter interface, and a digital control logic unit. The memristor programmable gain amplifier is directly integrated into the error amplifier feedback path of the power factor correction controller for dynamically adjusting the loop bandwidth and phase margin. The genetic algorithm uses a real-number encoding method, with each memristor unit corresponding to a gene. The gene value represents its target resistance value, which is normalized and mapped to a predetermined range, and then proportionally restored to the actual physical resistance value during the decoding stage. The fitness function of the genetic algorithm integrates three indicators: power factor, total harmonic distortion rate, and system efficiency. Each indicator is allocated according to a predetermined weight to guide parameter tuning to optimize energy efficiency while meeting power quality requirements. The preset thresholds include a preset power factor threshold or a preset distortion rate threshold. Once either indicator exceeds the limit, the system immediately initiates a self-tuning process, and the entire optimization and reconfiguration cycle does not exceed a preset time threshold.

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