Millimeter wave wideband agile frequency receive channel assembly

Abstract

The application relates to the radio frequency technical field and discloses a millimeter wave wideband frequency-agile receiving channel component which comprises the following: a duplex power dividing circuit used for receiving a reference clock signal, outputting a first reference clock signal, a second reference clock signal and a third reference clock signal; a self-checking coupling circuit used for receiving a radio frequency input signal and the second reference clock signal, generating a K-band radio frequency signal; a receiving frequency synthesizer circuit used for receiving the third reference clock signal, outputting a local oscillation signal and a frequency synthesizer locking indication signal; a receiving frequency conversion circuit used for receiving the K-band radio frequency signal and the local oscillation signal, obtaining a first intermediate frequency signal; a power control circuit used for receiving the first intermediate frequency signal, obtaining a second intermediate frequency signal; and a reference detection circuit used for receiving the first reference clock signal, obtaining a reference detection signal. The application can realize wide radio frequency bandwidth, high spurious suppression, fast frequency hopping speed, small frequency hopping step and BIT self-checking function support.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and in particular to a millimeter-wave broadband frequency agile receiving channel component. Background Technology

[0002] With the development of satellite communication technology, satellite communication speeds are constantly improving. The millimeter-wave band, as the mainstream operating frequency band for broadband satellite communication, possesses abundant spectrum resources and offers advantages such as supporting a larger number of connected users, lower user access latency, and wider bandwidth. However, because satellites are exposed in space and have fixed orbits, they are more susceptible to threats from reconnaissance, interception, and interference from all directions. Therefore, satellite communication systems typically employ communication anti-jamming technologies based on broadband high-speed frequency hopping. Broadband frequency hopping technology uses pseudo-random hopping of the transmission carrier over a large bandwidth. The frequency hopping patterns of both the transmitter and receiver are designed with special long periods and nonlinearity, making it difficult for the interfering party to predict the communication frequency. Combined with the short dwell time per hop, this makes tracking jamming difficult to implement, making it the mainstream anti-jamming technology for current satellite communication systems.

[0003] Satellite communication transceiver channels need to support larger channel bandwidth to meet the transmission capabilities of communication systems, such as more users accessing the system, faster transmission rates, and lower access latency. Simultaneously, they need to support faster frequency hopping rates to improve the anti-interference capability of the communication system. Therefore, designing a millimeter-wave broadband anti-interference receiving channel with excellent technical performance is crucial for improving the transmission and anti-interference performance of satellite communication systems. Summary of the Invention

[0004] To address the issues of narrow operating bandwidth, slow frequency hopping speed, and large frequency hopping step size in traditional satellite communication receiving channel components, this application provides a millimeter-wave broadband frequency agile receiving channel component, which features wide RF bandwidth, fast frequency hopping speed, small frequency hopping step size, and support for BIT self-test function, thereby improving the operating bandwidth and frequency hopping performance of the receiving channel.

[0005] This application discloses a millimeter-wave broadband frequency-agile receiving channel component, which includes a self-test coupling circuit, a receiving frequency conversion circuit, a power control circuit, a duplex power divider circuit, a reference detector circuit, and a receiving frequency synthesizer circuit; the self-test coupling circuit, the receiving frequency conversion circuit, the power control circuit, and the duplex power divider circuit are connected in sequence; the duplex power divider circuit is also connected to the reference detector circuit, the receiving frequency synthesizer circuit, and the self-test coupling circuit respectively.

[0006] The duplex power divider circuit is used to receive the reference clock signal REF_IN and perform a first process on it, outputting a first reference clock signal REF1, a second reference clock signal REF2, and a third reference clock signal REF3; the first process includes attenuation, matching, filtering, and power division;

[0007] The self-test coupling circuit is used to receive the radio frequency input signal RF_IN and the second reference clock signal REF2, generate the K-band radio frequency signal RF1 and input it into the receiving frequency conversion circuit;

[0008] The receiving frequency synthesizer circuit is used to receive the third reference clock signal REF3, and outputs the local oscillator signal LO and the frequency synthesizer lock-in indicator signal PLL_JC with high and low levels through DDS mixing and segmented switching filtering. Based on the frequency synthesizer lock-in indicator signal PLL_JC, it determines whether the receiving frequency synthesizer circuit is working properly, and inputs the local oscillator signal LO into the receiving frequency converter circuit.

[0009] The receiving frequency conversion circuit is used to receive the K-band radio frequency signal RF1 and the local oscillator signal LO. The local oscillator signal LO is power-divided to obtain two local oscillator signals. One local oscillator signal undergoes a second processing to obtain a first signal, and the other local oscillator signal undergoes a third processing to obtain a second signal. The K-band radio frequency signal RF1 undergoes a fourth processing to obtain a third signal. The first and third signals are mixed, and the mixed signal undergoes a fifth processing to obtain a fourth signal. The second and fourth signals are then mixed to obtain a first intermediate frequency signal IF1. The second processing includes frequency multiplication, filtering, and attenuation; the third processing includes filtering, amplification, and attenuation; the fourth processing includes filtering, amplification, and attenuation; and the fifth processing includes attenuation, amplification, and filtering.

[0010] The power control circuit is used to receive the first intermediate frequency signal IF1 and perform a sixth process on it to obtain the second intermediate frequency signal IF2, which is then input into the duplex power divider circuit; the sixth process includes filtering, amplification, and attenuation.

[0011] The reference detection circuit is used to receive the first reference clock signal REF1 and perform a seventh processing on it to obtain the reference detection signal RFE_JC; the reference detection signal RFE_JC is used to detect whether the first reference clock signal REF1 is normal.

[0012] Furthermore, the duplex power divider circuit is also used to receive the second intermediate frequency signal IF2 and perform an eighth processing on it to output a third intermediate frequency signal IF_OUT, which is the output of the receiving channel component; the eighth processing includes standing wave adjustment and filtering.

[0013] Furthermore, the self-test coupling circuit is used for:

[0014] In normal operating mode, it receives the RF input signal RF_IN and outputs the K-band RF signal RF1 directly.

[0015] In debug self-test mode, the second reference clock signal REF2 is received, and a K-band RF self-test signal RF_ZJ is generated through phase-locked loop. After filtering and coupling, the K-band RF signal RF1 is output. The K-band RF self-test signal RF_ZJ is used to detect whether the receiving channel component is working properly. When the RF self-test signal enters the receiving channel, if the receiving channel can output an intermediate frequency signal normally, it indicates that the receiving channel is working properly; otherwise, it indicates that the receiving channel is malfunctioning.

[0016] Input the K-band radio frequency signal RF1 into the receiving frequency converter circuit.

[0017] Furthermore, the self-test coupling circuit includes a phase-locked unit, a control unit, a filtering unit, and an RF coupler; the control unit is connected sequentially through the phase-locked unit, the filtering unit, and the RF coupler.

[0018] The FPGA of the control unit sends frequency control word information to the phase-locked unit to configure the registers inside the phase detector of the phase-locked unit;

[0019] The phase-locked unit is used to receive the second reference clock signal REF2. Internally, it consists of a phase detector, a voltage-controlled oscillator, and a loop filter to form a negative feedback loop to achieve frequency synthesis and output the K-band radio frequency self-test signal RF_ZJ.

[0020] The filtering unit is used to filter out harmonic signals and spurious signals in the K-band radio frequency self-test signal RF_ZJ;

[0021] The radio frequency coupler is used to couple the filtered signal output by the filter unit to achieve self-test signal coupling, and output the K-band radio frequency signal RF1 to the receiver frequency conversion circuit.

[0022] Furthermore, the duplex power divider circuit includes a first π-type attenuator, a reference clock signal branch, an intermediate frequency signal branch, and a reference branch; the reference clock signal branch includes a first inductor, a low-pass filter, and a second π-type attenuator connected in sequence; the reference branch is composed of a power divider.

[0023] The intermediate frequency signal branch includes a first capacitor C1, a high-pass filter, and a third π-type attenuator connected in sequence; the second intermediate frequency signal is output as an intermediate frequency output signal IF_OUT after passing through the intermediate frequency signal branch and the first π-type attenuator.

[0024] The input terminal of the first π-type attenuator is used to receive the reference clock signal REF_IN, and the output terminal is connected to the first inductor and the first capacitor C1 respectively; the input terminal of the power divider is connected to the output terminal of the second π-type attenuator, and the output terminal is used to output the first reference clock signal REF1, the second reference clock signal REF2 and the third reference clock signal REF3.

[0025] Furthermore, the first π-type attenuator, the second π-type attenuator, and the third π-type attenuator are all used to adjust the power of the reference clock signal and the second intermediate frequency signal IF2, as well as the standing wave ratio of the input and output signals.

[0026] The first inductor and the first capacitor C1 are both used to adjust the phase matching between the reference clock signal and the second intermediate frequency signal in order to reduce the transmission loss between the reference clock signal and the second intermediate frequency signal.

[0027] The low-pass filter is used to suppress out-of-band spurious signals of the reference clock signal, and the high-pass filter is used to suppress out-of-band spurious signals of the second intermediate frequency signal IF2.

[0028] Furthermore, the reference detection circuit includes a fourth π-shaped attenuator, a detection diode, and an FPGA chip connected in sequence;

[0029] The fourth π-shaped attenuator is used to adjust the power of the first reference clock signal REF1 to obtain a power-adjusted clock signal and input it into the detector diode.

[0030] The detector diode is used to zero-bias the power-adjusted clock signal to obtain the detector voltage and input it into the FPGA chip.

[0031] The A / D circuit inside the FPGA chip is used to sample the detection voltage. If the level of the sampled signal is greater than or equal to a preset value, an LVTTL high-level reference detection signal RFE_JC is output. The LVTTL high-level reference detection signal RFE_JC is used to indicate that the first reference clock signal REF1 is normal. If the level of the sampled signal is less than the preset value, an LVTTL low-level reference detection signal RFE_JC is output. The LVTTL low-level reference detection signal RFE_JC is used to indicate that the first reference clock signal REF1 is abnormal.

[0032] Furthermore, the receiving frequency synthesizer circuit includes an intermediate frequency branch, a local oscillator branch, a radio frequency branch, and a control circuit;

[0033] The intermediate frequency branch includes a DDS, a π-shaped attenuator, and a bandpass filter connected in sequence;

[0034] The local oscillator branch includes a phase-locked loop (PLL) and a power divider connected in sequence;

[0035] The radio frequency branch includes a mixer, a switched filter bank, an attenuator, and a temperature-compensated attenuator connected in sequence.

[0036] The control circuitry includes an FPGA, which is used to configure the DDS and the phase-locked loop (PLL).

[0037] The FPGA configures the phase-locked loop (PLL), which generates a local oscillator (LO) signal based on the third reference clock signal REF3. This LO signal is split into two outputs by the power divider. One output is input to the DDS as its external clock, and the other is used to receive the LO signal mixed internally by the frequency synthesizer circuit. The frequency-hopping signal output by the DDS passes through a π-shaped attenuator and a bandpass filter to suppress its spurious signals. Then, it enters the mixer of the RF branch and is mixed with the LO signal. The mixed signal is then passed through a switching filter bank for local oscillator leakage uncorrelated spurious filtering and combined correlated spurious filtering. Finally, it is attenuated by a digitally controlled attenuator and a temperature-compensated attenuator to output the LO signal.

[0038] The phase-locked loop (PLL) is used to output the frequency lock-in indicator signal PLL_JC. If the frequency lock-in indicator signal PLL_JC is at a logic high level, it indicates that the PLL is working normally. If the frequency lock-in indicator signal PLL_JC is at a logic low level, it indicates that the PLL is malfunctioning.

[0039] Furthermore, the receiving frequency conversion circuit includes a radio frequency link, two intermediate frequency links, a single local oscillator link, and two local oscillator links;

[0040] The radio frequency link includes a first bandpass filter, a first low-noise amplifier, a low-pass filter, and a K-band mixer that implements the first stage of mixing, connected in sequence.

[0041] The two intermediate frequency links include a first fixed attenuator, a second low-noise amplifier, a second bandpass filter, a temperature-compensated attenuator, and a C-band mixer that realizes the second-stage mixing, connected in sequence.

[0042] The local oscillator link includes a third fixed attenuator, a fourth frequency multiplier, a fourth bandpass filter, and a fourth fixed attenuator connected in sequence;

[0043] The dual local oscillator link includes a third bandpass filter, a third low-noise amplifier, and a second fixed attenuator connected in sequence.

[0044] The first local oscillator link and the second local oscillator link share the same power divider; the input of the power divider is used to receive the local oscillator signal LO, and the output is connected to the input of the third fixed attenuator and the third bandpass filter, respectively.

[0045] The K-band radio frequency signal RF1 is filtered by the first bandpass filter to suppress the image frequency interference signal, the first low noise amplifier to reduce the noise figure of the receiving channel component, and the low pass filter to suppress the spurious signal of the transmitting band. Then it enters the K-band mixer that realizes the first stage of mixing and is mixed with the first local oscillator reference signal output by the first local oscillator link to obtain the mixed signal and input it into the first fixed attenuator of the second intermediate frequency link.

[0046] The mixed signal passes sequentially through the first fixed attenuator and the second low-noise amplifier to adjust the link level. Then, it passes through the second bandpass filter to filter out the combined spurious signals and harmonic spurious signals of the two intermediate frequency links. The temperature-compensated attenuator compensates for the gain changes of the receiving channel components at different temperatures. Then, it enters the C-band mixer that implements the second-stage mixing and mixes with the second local oscillator reference signal output from the two local oscillator links to obtain the first intermediate frequency signal IF1.

[0047] Wherein, the first local oscillator link and the second local oscillator link share the same local oscillator signal LO. The local oscillator signal LO passes through the power divider, the fourth frequency multiplier, and the fourth bandpass filter that suppresses the third and fifth harmonics to output a fourth frequency multiplier signal. The fourth frequency multiplier signal is then leveled by the fourth fixed attenuator to output the first local oscillator reference signal.

[0048] The local oscillator signal LO is passed through the power divider, the third bandpass filter, the third low-noise amplifier, and the second fixed attenuator to adjust the level of the local oscillator signal LO and output the second local oscillator reference signal.

[0049] Furthermore, the power control circuit includes a first low-pass filter, a fourth low-noise amplifier, a digitally controlled attenuator, a surface acoustic wave filter, a fifth low-noise amplifier, a fifth fixed attenuator, and a second low-pass filter connected in sequence.

[0050] The first intermediate frequency signal IF1 is sequentially filtered by the first low-pass filter, amplified by the fourth low-noise amplifier, attenuated by the digitally controlled attenuator, filtered by the surface acoustic wave filter, amplified by the fifth low-noise amplifier, attenuated by the fifth fixed attenuator, and filtered by the second low-pass filter to output the second intermediate frequency signal IF2.

[0051] Due to the adoption of the above technical solution, this application has the following advantages:

[0052] 1. Wide operating bandwidth: This application adopts a two-frequency conversion design method, so that during the first and second frequency conversion processes, the local oscillator leakage signal with a large power level is located outside the corresponding radio frequency range. The combination design of bandpass filter and low-pass filter can effectively filter out the uncorrelated spurious local oscillator leakage and the harmonic spurious of the output signal.

[0053] 2. Short frequency hopping time: This application uses a DDS to output a frequency hopping signal with good spurious suppression, and then outputs the local oscillator (LO) signal required by the receiving frequency conversion channel through a mixing and segmented filtering method. During the frequency hopping process, the receiving frequency synthesizer circuit receives the frequency code information that is about to be updated in advance. The FPGA inside the frequency synthesizer module decodes and pre-configures the internal registers of the DDS. When the trigger control signal for switching the frequency is received, the DDS starts to respond and outputs the frequency-hopped signal, which then passes through the internal mixer of the frequency synthesizer, the switching filter bank, and the receiving frequency conversion circuit until a new intermediate frequency signal is output.

[0054] 3. This application supports BIT self-test: This application detects the input reference signal level through a reference signal detector circuit, generates a receiving frequency band self-test signal through a self-test coupling circuit, determines whether the receiving frequency converter circuit is working properly by detecting the output status of the receiving intermediate frequency signal, and outputs a frequency synthesizer lock-in indication signal through the receiving frequency synthesizer circuit.

[0055] 4. This application has good scalability. It can be applied to different broadband anti-jamming satellite communication platforms by updating and upgrading the internal configuration program of the receiving channel component and replacing the filters of the corresponding links, according to actual performance requirements. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0057] Figure 1 This is a schematic diagram of a millimeter-wave broadband frequency-agile receiving channel component according to an embodiment of this application;

[0058] Figure 2 This is a schematic diagram of the duplex power divider circuit according to an embodiment of this application;

[0059] Figure 3 This is a schematic diagram of the reference detector circuit in an embodiment of this application;

[0060] Figure 4 This is a schematic diagram of the receiving frequency synthesizer circuit according to an embodiment of this application;

[0061] Figure 5 This is a schematic diagram of the self-test coupling circuit in an embodiment of this application;

[0062] Figure 6 This is a schematic diagram of the receiving frequency conversion circuit according to an embodiment of this application;

[0063] Figure 7This is a schematic diagram of the power control circuit in an embodiment of this application. Detailed Implementation

[0064] The present application will be further described in conjunction with the accompanying drawings and embodiments. The described embodiments are only some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of the present application.

[0065] See Figure 1 This application provides an embodiment of a millimeter-wave broadband frequency-agile receiving channel component, which includes a self-test coupling circuit, a receiving frequency conversion circuit, a power control circuit, a duplex power divider circuit, a reference detector circuit, and a receiving frequency synthesizer circuit; the self-test coupling circuit, the receiving frequency conversion circuit, the power control circuit, and the duplex power divider circuit are connected in sequence; the duplex power divider circuit is also connected to the reference detector circuit, the receiving frequency synthesizer circuit, and the self-test coupling circuit respectively.

[0066] The duplex power divider circuit is used to receive the reference clock signal REF_IN and perform a first processing on it, outputting a first reference clock signal REF1, a second reference clock signal REF2, and a third reference clock signal REF3; the first processing includes attenuation, matching, filtering, and power division;

[0067] The self-test coupling circuit is used to receive the RF input signal RF_IN and the second reference clock signal REF2, generate the K-band RF signal RF1 and input it into the receiving frequency converter circuit;

[0068] The receiving frequency synthesizer circuit is used to receive the third reference clock signal REF3. It outputs the local oscillator signal LO and the frequency synthesizer lock-in indicator signal PLL_JC with high and low levels through DDS mixing and segmented switching filtering. Based on the frequency synthesizer lock-in indicator signal PLL_JC, it determines whether the receiving frequency synthesizer circuit is working properly and inputs the local oscillator signal LO into the receiving frequency converter circuit.

[0069] The receiving frequency conversion circuit receives the K-band radio frequency signal RF1 and the local oscillator signal LO. It performs power distribution on the local oscillator signal LO to obtain two local oscillator signals. One of the local oscillator signals undergoes a second processing step to obtain a first signal, and the other local oscillator signal undergoes a third processing step to obtain a second signal. The K-band radio frequency signal RF1 undergoes a fourth processing step to obtain a third signal. The first and third signals are then mixed. The mixed signal undergoes a fifth processing step to obtain a fourth signal. The second and fourth signals are then mixed to obtain a first intermediate frequency signal IF1. The second processing step includes frequency multiplication, filtering, and attenuation; the third processing step includes filtering, amplification, and attenuation; the fourth processing step includes filtering, amplification, and attenuation; and the fifth processing step includes attenuation, amplification, and filtering.

[0070] The power control circuit receives the first intermediate frequency signal IF1 and performs a sixth process on it to obtain the second intermediate frequency signal IF2, which is then input into the duplex power divider circuit. The sixth process includes filtering, amplification, and attenuation.

[0071] The reference detector circuit is used to receive the first reference clock signal REF1 and process it to obtain the reference detector signal RFE_JC; the reference detector signal RFE_JC is used to detect whether the first reference clock signal REF1 is normal.

[0072] Optionally, see Figure 2 The duplex power divider circuit is also used to receive the second intermediate frequency signal IF2 and perform the eighth processing on it, outputting the third intermediate frequency signal IF_OUT. The third intermediate frequency signal IF_OUT is the output of the receiving channel component; the eighth processing includes standing wave adjustment and filtering.

[0073] Optionally, see Figure 5 The self-test coupling circuit is used for:

[0074] In normal operating mode, it receives the RF input signal RF_IN and outputs the K-band RF signal RF1 directly.

[0075] In debug self-test mode, the second reference clock signal REF2 is received, and a K-band RF self-test signal RF_ZJ is generated through phase-locked loop. After filtering and coupling, the K-band RF signal RF1 is output. The K-band RF self-test signal RF_ZJ is used to detect whether the receiving channel component is working properly. When the RF self-test signal enters the receiving channel, if the receiving channel can output the intermediate frequency signal normally, it indicates that the receiving channel is working properly; otherwise, it indicates that the receiving channel is malfunctioning.

[0076] Input the K-band radio frequency signal RF1 into the receiving frequency converter circuit.

[0077] Optionally, see Figure 5 The self-test coupling circuit includes a phase-locked unit, a control unit, a filter unit, and an RF coupler; the control unit is connected in sequence through the phase-locked unit, the filter unit, and the RF coupler.

[0078] The FPGA of the control unit sends frequency control word information to the phase-locked unit to configure the registers inside the phase detector of the phase-locked unit;

[0079] The phase-locked unit is used to receive the second reference clock signal REF2. Its internal components consist of a phase detector, a voltage-controlled oscillator, and a loop filter to form a negative feedback loop to achieve frequency synthesis and output the K-band RF self-test signal RF_ZJ.

[0080] The filtering unit is used to filter out harmonic and spurious signals in the K-band radio frequency self-test signal RF_ZJ;

[0081] The radio frequency coupler is used to couple the filtered signal output by the filter unit to achieve self-test signal coupling, and output the K-band radio frequency signal RF1 to the receiver's frequency conversion circuit.

[0082] Optionally, see Figure 2 The duplex power divider circuit includes a first π-type attenuator (π-attenuator 1), a reference clock signal branch, an intermediate frequency signal branch, and a reference branch; the reference clock signal branch includes a first inductor L1, a low-pass filter, and a second π-type attenuator (π-attenuator 2) connected in sequence; the reference branch is composed of a power divider.

[0083] The intermediate frequency (IF) signal branch includes a first capacitor C1, a high-pass filter, and a third π-type attenuator (π-attenuation 3) connected in sequence; the second IF signal is output as an IF output signal IF_OUT after passing through the IF signal branch and the first π-type attenuator.

[0084] The input of the first π-type attenuator is used to receive the reference clock signal REF_IN, and its output is connected to the first inductor L1 and the first capacitor C1 respectively; the input of the power divider is connected to the output of the second π-type attenuator, and its output is used to output the first reference clock signal REF1, the second reference clock signal REF2 and the third reference clock signal REF3.

[0085] Optionally, the first π-type attenuator, the second π-type attenuator, and the third π-type attenuator are all used to adjust the power of the reference clock signal and the second intermediate frequency signal IF2, as well as the standing wave ratio of the input and output signals.

[0086] The first inductor L1 and the first capacitor C1 are both used to adjust the phase matching between the reference clock signal and the second intermediate frequency signal in order to reduce the transmission loss between the reference clock signal and the second intermediate frequency signal.

[0087] The low-pass filter is used to suppress out-of-band spurious signals of the reference clock signal, and the high-pass filter is used to suppress out-of-band spurious signals of the second intermediate frequency signal IF2.

[0088] Optionally, see Figure 3 The reference detector circuit includes a fourth π-shaped attenuator (π attenuator), a detector diode, and an FPGA chip connected in sequence.

[0089] The fourth π-shaped attenuator is used to adjust the power of the first reference clock signal REF1, obtain the power-adjusted clock signal, and input it into the detector diode;

[0090] The detector diode is used to zero-bias the power-adjusted clock signal to obtain the detector voltage and input it into the FPGA chip.

[0091] The A / D circuit inside the FPGA chip is used to sample the detection voltage. If the level of the sampled signal is greater than or equal to a preset value, it outputs an LVTTL (Low Voltage Transistor-Transistor Logic) high-level reference detection signal RFE_JC. The LVTTL high-level reference detection signal RFE_JC is used to indicate that the first reference clock signal REF1 is normal. If the level of the sampled signal is less than the preset value, it outputs an LVTTL low-level reference detection signal RFE_JC. The LVTTL low-level reference detection signal RFE_JC is used to indicate that the first reference clock signal REF1 is abnormal.

[0092] Optionally, see Figure 4 The receiving frequency synthesizer circuit includes an intermediate frequency branch, a local oscillator branch, a radio frequency branch, and a control circuit.

[0093] The intermediate frequency branch includes a DDS, a π-shaped attenuator, and a bandpass filter connected in sequence;

[0094] The local oscillator branch includes a phase-locked loop (PLL) and a power divider connected in sequence;

[0095] The radio frequency branch includes a mixer, a switched filter bank, a digitally controlled attenuator, and a temperature-compensated attenuator connected in sequence.

[0096] The control circuitry includes an FPGA, which is used to configure the DDS and the phase-locked loop (PLL).

[0097] The FPGA configures the phase-locked loop (PLL), which generates a local oscillator (LO) signal based on the third reference clock signal REF3. This LO signal is split into two outputs by the power divider. One output is input to the DDS as its external clock, and the other is used to receive the LO signal mixed internally by the frequency synthesizer circuit. The frequency-hopping signal output by the DDS passes through a π-shaped attenuator and a bandpass filter to suppress its spurious signals. Then, it enters the mixer of the RF branch and is mixed with the LO signal. The mixed signal is then passed through a switching filter bank for local oscillator leakage uncorrelated spurious filtering and combined correlated spurious filtering. Finally, it is attenuated by a digitally controlled attenuator and a temperature-compensated attenuator to output the LO signal.

[0098] The phase-locked loop (PLL) is used to output the frequency lock-in indicator signal PLL_JC. If the frequency lock-in indicator signal PLL_JC is at a logic high level, it indicates that the PLL is working normally. If the frequency lock-in indicator signal PLL_JC is at a logic low level, it indicates that the PLL is malfunctioning.

[0099] The receiving frequency synthesizer circuit of this application embodiment can output a local oscillator signal with small steps, large bandwidth, and low spurious emissions through mixing and segmented switching filtering, while simultaneously outputting high and low level frequency synthesizer lock-in indication signals.

[0100] Optionally, see Figure 4 The switched filter bank includes SDT switches, π-type attenuators, bandpass filters, and SDT switches.

[0101] Optionally, see Figure 4 A π-type attenuator, bandpass filter, and amplifier can be connected between the switching filter bank and the digitally controlled attenuator. An amplifier and bandpass filter can also be connected after the temperature-compensated attenuator.

[0102] Optionally, see Figure 6 The receiving frequency conversion circuit includes a radio frequency link, two intermediate frequency links, a single local oscillator link, and two local oscillator links;

[0103] The radio frequency link includes a first bandpass filter, a first low-noise amplifier, a low-pass filter, and a K-band mixer that implements the first stage of mixing, connected in sequence.

[0104] The two intermediate frequency links include a first fixed attenuator, a second low-noise amplifier, a second bandpass filter, a temperature-compensated attenuator, and a C-band mixer that realizes the second-stage mixing, connected in sequence.

[0105] A single oscillator link includes a third fixed attenuator, a fourth frequency multiplier, a fourth bandpass filter, and a fourth fixed attenuator connected in sequence;

[0106] The two-way oscillator link includes a third bandpass filter, a third low-noise amplifier, and a second fixed attenuator connected in sequence.

[0107] The local oscillator link and the second local oscillator link share the same power divider; the input of the power divider is used to receive the local oscillator signal LO, and the output is connected to the input of the third fixed attenuator and the third bandpass filter, respectively.

[0108] The K-band radio frequency signal RF1 is filtered by a first bandpass filter to suppress the image frequency interference signal, a first low-noise amplifier to reduce the noise figure of the receiving channel components, and a low-pass filter to suppress the spurious signal of the transmitting band. Then it enters the K-band mixer that performs the first stage of mixing and is mixed with the first local oscillator reference signal output from the local oscillator link to obtain the mixed signal and input it into the first fixed attenuator of the second intermediate frequency link.

[0109] The mixed signal passes through the first fixed attenuator and the second low-noise amplifier to adjust the link level. Then, it passes through the second bandpass filter to filter out the combined spurious signals and harmonic spurious signals of the two intermediate frequency links. The gain change of the receiving channel component at different temperatures is compensated by the temperature-compensated attenuator. Then, it enters the C-band mixer that realizes the second-stage mixing and mixes with the second local oscillator reference signal output from the two local oscillator links to obtain the first intermediate frequency signal IF1.

[0110] Among them, the first local oscillator link and the second local oscillator link share the same local oscillator signal LO. The local oscillator signal LO passes through a power divider, a frequency quadrupler, and a fourth bandpass filter that suppresses the third and fifth harmonics to output a frequency quadrupler signal. The frequency quadrupler signal is then leveled by a fourth fixed attenuator to output the first local oscillator reference signal.

[0111] The local oscillator signal LO is passed through a power divider, a third bandpass filter, a third low-noise amplifier, and a second fixed attenuator to adjust the level of the local oscillator signal LO and output a second local oscillator reference signal.

[0112] Optionally, see Figure 7 The power control circuit includes a first low-pass filter, a fourth low-noise amplifier, a digitally controlled attenuator, a surface acoustic wave filter, a fifth low-noise amplifier, a fifth fixed attenuator, and a second low-pass filter connected in sequence.

[0113] The first intermediate frequency signal IF1 is sequentially filtered by the first low-pass filter, amplified by the fourth low-noise amplifier, attenuated by the digitally controlled attenuator, filtered by the surface acoustic wave filter, amplified by the fifth low-noise amplifier, attenuated by the fifth fixed attenuator, and filtered by the second low-pass filter to output the second intermediate frequency signal IF2.

[0114] Small frequency hopping step: This application uses DDS as the frequency hopping source, and the formula for calculating the DDS output frequency is as follows:

[0115]

[0116] in, FTW is the frequency control word (48 bits) for DDS output frequency. The DDS serves as an external clock for the DSS, offering frequency accuracy up to 48 bits and a minimum step size on the order of 10⁻⁵ Hz. The DDS uses a 4.6 GHz system clock, and the minimum frequency hopping step for the RF output signal is ≤1 Hz.

[0117] The channel component in this application supports receiving radio frequency signals with a bandwidth of 3.5 GHz in the K-band, and has both in-band and out-of-band spurious rejection of ≥60 dBc.

[0118] The frequency hopping time of the channel component in this application, from the start of receiving the trigger signal to the final output of a stable intermediate frequency signal, is ≤150ns.

[0119] The channel component in this application example can be visually checked using the BIT self-test query command on the host computer to see whether the receiving channel itself is working properly and whether the external reference input is normal.

[0120] Supports BIT self-test: This application detects the input reference signal level through a reference signal detector circuit, generates a receiving frequency band self-test signal through a self-test coupling circuit, determines the normal operation of the receiving frequency converter circuit by detecting the output status of the receiving intermediate frequency signal, and outputs a frequency synthesizer lock-in indication signal through the receiving frequency synthesizer circuit. The channel component in this embodiment can be visually viewed using the BIT self-test query command on the host computer to check whether the receiving channel itself is operating normally and whether the external reference input is normal.

[0121] This application has good scalability. It can be applied to different broadband anti-jamming satellite communication platforms by updating and upgrading the internal configuration program of the receiving channel component and replacing the corresponding link filters, according to actual performance requirements.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and not to limit them. Although this application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this application. Any modifications or equivalent substitutions that do not depart from the spirit and scope of this application should be covered within the protection scope of the claims of this application.

Claims

1. A millimeter-wave broadband frequency-agile receiving channel component, characterized in that, It includes a self-test coupling circuit, a receiving frequency conversion circuit, a power control circuit, a duplex power divider circuit, a reference detector circuit, and a receiving frequency synthesizer circuit; the self-test coupling circuit, the receiving frequency conversion circuit, the power control circuit, and the duplex power divider circuit are connected in sequence; the duplex power divider circuit is also connected to the reference detector circuit, the receiving frequency synthesizer circuit, and the self-test coupling circuit respectively. The duplex power divider circuit is used to receive the reference clock signal REF_IN and perform a first process on it, outputting a first reference clock signal REF1, a second reference clock signal REF2, and a third reference clock signal REF3; the first process includes attenuation, matching, filtering, and power division; The self-test coupling circuit is used to receive the radio frequency input signal RF_IN and the second reference clock signal REF2, generate the K-band radio frequency signal RF1 and input it into the receiving frequency conversion circuit; The receiving frequency synthesizer circuit is used to receive the third reference clock signal REF3, and outputs the local oscillator signal LO and the frequency synthesizer lock-in indicator signal PLL_JC with high and low levels through DDS mixing and segmented switching filtering. Based on the frequency synthesizer lock-in indicator signal PLL_JC, it determines whether the receiving frequency synthesizer circuit is working properly, and inputs the local oscillator signal LO into the receiving frequency converter circuit. The receiving frequency conversion circuit is used to receive the K-band radio frequency signal RF1 and the local oscillator signal LO. The local oscillator signal LO is power-divided to obtain two local oscillator signals. One local oscillator signal undergoes a second processing to obtain a first signal, and the other local oscillator signal undergoes a third processing to obtain a second signal. The K-band radio frequency signal RF1 undergoes a fourth processing to obtain a third signal. The first and third signals are mixed, and the mixed signal undergoes a fifth processing to obtain a fourth signal. The second and fourth signals are then mixed to obtain a first intermediate frequency signal IF1. The second processing includes frequency multiplication, filtering, and attenuation; the third processing includes filtering, amplification, and attenuation; the fourth processing includes filtering, amplification, and attenuation; and the fifth processing includes attenuation, amplification, and filtering. The power control circuit is used to receive the first intermediate frequency signal IF1 and perform a sixth process on it to obtain the second intermediate frequency signal IF2, which is then input into the duplex power divider circuit; the sixth process includes filtering, amplification, and attenuation. The reference detection circuit is used to receive the first reference clock signal REF1 and perform a seventh processing on it to obtain the reference detection signal RFE_JC; the reference detection signal RFE_JC is used to detect whether the first reference clock signal REF1 is normal.

2. The millimeter-wave broadband frequency-agile receiving channel component according to claim 1, characterized in that, The duplex power divider circuit is also used to receive the second intermediate frequency signal IF2 and perform an eighth processing on it to output the third intermediate frequency signal IF_OUT, which is the output of the receiving channel component; the eighth processing includes standing wave adjustment and filtering.

3. The millimeter-wave broadband frequency-agile receiving channel component according to claim 1, characterized in that, The self-test coupling circuit is used for: In normal operating mode, it receives the RF input signal RF_IN and outputs the K-band RF signal RF1 directly. In debug self-test mode, the second reference clock signal REF2 is received, and a K-band RF self-test signal RF_ZJ is generated through phase-locked loop. After filtering and coupling, the K-band RF signal RF1 is output. The K-band RF self-test signal RF_ZJ is used to detect whether the receiving channel component is working properly. When the RF self-test signal enters the receiving channel, if the receiving channel can output an intermediate frequency signal normally, it indicates that the receiving channel is working properly; otherwise, it indicates that the receiving channel is malfunctioning. Input the K-band radio frequency signal RF1 into the receiving frequency converter circuit.

4. The millimeter-wave broadband frequency-agile receiving channel component according to claim 1, characterized in that, The self-test coupling circuit includes a phase-locked unit, a control unit, a filter unit, and an RF coupler; the control unit is connected in sequence through the phase-locked unit, the filter unit, and the RF coupler. The FPGA of the control unit sends frequency control word information to the phase-locked unit to configure the registers inside the phase detector of the phase-locked unit; The phase-locked unit is used to receive the second reference clock signal REF2. Internally, it consists of a phase detector, a voltage-controlled oscillator, and a loop filter to form a negative feedback loop to achieve frequency synthesis and output the K-band radio frequency self-test signal RF_ZJ. The filtering unit is used to filter out harmonic signals and spurious signals in the K-band radio frequency self-test signal RF_ZJ; The radio frequency coupler is used to couple the filtered signal output by the filter unit to achieve self-test signal coupling, and output the K-band radio frequency signal RF1 to the receiver frequency conversion circuit.

5. The millimeter-wave broadband frequency-agile receiving channel component according to claim 1, characterized in that, The duplex power divider circuit includes a first π-type attenuator, a reference clock signal branch, an intermediate frequency signal branch, and a reference branch; the reference clock signal branch includes a first inductor, a low-pass filter, and a second π-type attenuator connected in sequence; the reference branch is composed of a power divider. The intermediate frequency signal branch includes a first capacitor C1, a high-pass filter, and a third π-type attenuator connected in sequence; the second intermediate frequency signal is output as an intermediate frequency output signal IF_OUT after passing through the intermediate frequency signal branch and the first π-type attenuator. The input terminal of the first π-type attenuator is used to receive the reference clock signal REF_IN, and the output terminal is connected to the first inductor and the first capacitor C1 respectively; the input terminal of the power divider is connected to the output terminal of the second π-type attenuator, and the output terminal is used to output the first reference clock signal REF1, the second reference clock signal REF2 and the third reference clock signal REF3.

6. The millimeter-wave broadband frequency-agile receiving channel component according to claim 5, characterized in that, The first π-type attenuator, the second π-type attenuator, and the third π-type attenuator are all used to adjust the power of the reference clock signal and the second intermediate frequency signal IF2, as well as the standing wave ratio of the input and output signals. The first inductor and the first capacitor C1 are both used to adjust the phase matching between the reference clock signal and the second intermediate frequency signal in order to reduce the transmission loss between the reference clock signal and the second intermediate frequency signal. The low-pass filter is used to suppress out-of-band spurious signals of the reference clock signal, and the high-pass filter is used to suppress out-of-band spurious signals of the second intermediate frequency signal IF2.

7. The millimeter-wave broadband frequency-agile receiving channel component according to claim 1, characterized in that, The reference detection circuit includes a fourth π-type attenuator, a detector diode, and an FPGA chip connected in sequence. The fourth π-type attenuator is used to adjust the power of the first reference clock signal REF1 to obtain a power-adjusted clock signal and input it into the detector diode. The detector diode is used to zero-bias the power-adjusted clock signal to obtain the detector voltage and input it into the FPGA chip. The A / D circuit inside the FPGA chip is used to sample the detection voltage. If the level of the sampled signal is greater than or equal to a preset value, an LVTTL high-level reference detection signal RFE_JC is output. The LVTTL high-level reference detection signal RFE_JC is used to indicate that the first reference clock signal REF1 is normal. If the level of the sampled signal is less than the preset value, an LVTTL low-level reference detection signal RFE_JC is output. The LVTTL low-level reference detection signal RFE_JC is used to indicate that the first reference clock signal REF1 is abnormal.

8. The millimeter-wave broadband frequency-agile receiving channel component according to claim 1, characterized in that, The receiving frequency synthesizer circuit includes an intermediate frequency branch, a local oscillator branch, a radio frequency branch, and a control circuit; The intermediate frequency branch includes a DDS, a π-type attenuator, and a bandpass filter connected in sequence. The local oscillator branch includes a phase-locked loop (PLL) and a power divider connected in sequence; The radio frequency branch includes a mixer, a switched filter bank, a digitally controlled attenuator, and a temperature-compensated attenuator connected in sequence. The control circuitry includes an FPGA, which is used to configure the DDS and the phase-locked loop (PLL). The FPGA configures the phase-locked loop (PLL), which generates a local oscillator (LO) signal based on the third reference clock signal REF3. This LO signal is split into two outputs by the power divider. One output is input to the DDS as its external clock, and the other is used to receive the LO signal mixed internally by the frequency synthesizer circuit. The frequency-hopping signal output by the DDS passes through a π-type attenuator and a bandpass filter to suppress its spurious signals. Then, it enters the mixer of the RF branch and is mixed with the LO signal. The mixed signal is then passed through a switching filter bank for local oscillator leakage uncorrelated spurious filtering and combined correlated spurious filtering. Finally, it is attenuated by a digitally controlled attenuator and a temperature-compensated attenuator to output the LO signal. The phase-locked loop (PLL) is used to output the frequency lock-in indicator signal PLL_JC. If the frequency lock-in indicator signal PLL_JC is at a logic high level, it indicates that the PLL is working normally. If the frequency lock-in indicator signal PLL_JC is at a logic low level, it indicates that the PLL is malfunctioning.

9. The millimeter-wave broadband frequency-agile receiving channel component according to claim 1, characterized in that, The receiving frequency conversion circuit includes a radio frequency link, two intermediate frequency links, a local oscillator link, and two local oscillator links; The radio frequency link includes a first bandpass filter, a first low-noise amplifier, a low-pass filter, and a K-band mixer that implements the first stage of mixing, connected in sequence. The two intermediate frequency links include a first fixed attenuator, a second low-noise amplifier, a second bandpass filter, a temperature-compensated attenuator, and a C-band mixer that realizes the second-stage mixing, connected in sequence. The local oscillator link includes a third fixed attenuator, a fourth frequency multiplier, a fourth bandpass filter, and a fourth fixed attenuator connected in sequence; The dual local oscillator link includes a third bandpass filter, a third low-noise amplifier, and a second fixed attenuator connected in sequence. The first local oscillator link and the second local oscillator link share the same power divider; the input of the power divider is used to receive the local oscillator signal LO, and the output is connected to the input of the third fixed attenuator and the third bandpass filter, respectively. The K-band radio frequency signal RF1 is filtered by the first bandpass filter to suppress the image frequency interference signal, the first low noise amplifier to reduce the noise figure of the receiving channel component, and the low pass filter to suppress the spurious signal of the transmitting band. Then it enters the K-band mixer that realizes the first stage of mixing and is mixed with the first local oscillator reference signal output by the first local oscillator link to obtain the mixed signal and input it into the first fixed attenuator of the second intermediate frequency link. The mixed signal passes sequentially through the first fixed attenuator and the second low-noise amplifier to adjust the link level. Then, it passes through the second bandpass filter to filter out the combined spurious signals and harmonic spurious signals of the two intermediate frequency links. The temperature-compensated attenuator compensates for the gain changes of the receiving channel components at different temperatures. Then, it enters the C-band mixer that implements the second-stage mixing and mixes with the second local oscillator reference signal output from the two local oscillator links to obtain the first intermediate frequency signal IF1. Wherein, the first local oscillator link and the second local oscillator link share the same local oscillator signal LO. The local oscillator signal LO passes through the power divider, the fourth frequency multiplier, and the fourth bandpass filter that suppresses the third and fifth harmonics to output a fourth frequency multiplier signal. The fourth frequency multiplier signal is then leveled by the fourth fixed attenuator to output the first local oscillator reference signal. The local oscillator signal LO is passed through the power divider, the third bandpass filter, the third low-noise amplifier, and the second fixed attenuator to adjust the level of the local oscillator signal LO and output the second local oscillator reference signal.

10. The millimeter-wave broadband frequency-agile receiving channel component according to claim 1, characterized in that, The power control circuit includes a first low-pass filter, a fourth low-noise amplifier, a digitally controlled attenuator, a surface acoustic wave filter, a fifth low-noise amplifier, a fifth fixed attenuator, and a second low-pass filter connected in sequence. The first intermediate frequency signal IF1 is sequentially filtered by the first low-pass filter, amplified by the fourth low-noise amplifier, attenuated by the digitally controlled attenuator, filtered by the surface acoustic wave filter, amplified by the fifth low-noise amplifier, attenuated by the fifth fixed attenuator, and filtered by the second low-pass filter to output the second intermediate frequency signal IF2.

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