Trench field effect transistor semiconductor device and method of manufacturing the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ANJIAN TECH (SHENZHEN) CO LTD
- Filing Date
- 2026-04-13
- Publication Date
- 2026-07-21
AI Technical Summary
When the cell size of existing shielded trench MOSFET devices is reduced, the on-resistance increases, the uniformity of the switching threshold deteriorates, the conduction area of the drift region decreases, and wafer warping and reliability issues arise in the manufacturing process.
A dual-layer trench structure is adopted, including first-type and second-type trenches. Source contact hole trenches are formed through a self-aligned process. Combined with the design of different doping regions, the trench spacing and doping concentration distribution are optimized to increase the trench density and reduce surface stress.
This achieves lower on-resistance, better switching threshold uniformity, and a larger safe operating area, while improving device reliability and manufacturing yield.
Smart Images
Figure CN122028476B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to power semiconductor devices, particularly the structure and manufacturing method of shielded gate trench field-effect transistor devices. Background Technology
[0002] Shielded trench MOSFETs are characterized by low on-resistance and fast switching speed. An existing shielded trench MOSFET structure is as follows: Figure 1 As shown. Figure 1 The left side of the image shows a schematic diagram of a traditional N-type shielded gate trench field-effect transistor (FET). To further reduce the on-resistance of the shielded gate trench FET, it is necessary to increase the doping concentration in the drift region and reduce the drift region resistance. Correspondingly, the inter-cell trench distance (B) needs to be reduced in the device structure to maintain the breakdown voltage. However, as... Figure 1 The top view of the device structure is shown on the right. The distance between cell trenches (B) is limited by the width of the source contact hole trench (C) and the distance between the cell trench and the source contact hole trench (A) (referred to as trench spacing (A)). Generally, the cell trenches and the source contact hole trenches are formed by two separate photolithography processes. Due to the limitations of photolithography precision, alignment deviations between the two photolithography processes can easily cause the trench spacing (A) to become too close. This results in the P+ contact doping region formed below the source contact trench affecting the doping concentration of the corresponding cell trench channel region, thereby affecting the device's on-resistance and switching threshold. Therefore, in the above structure, the trench spacing (A) limits further reduction in cell size.
[0003] Figure 2 This is a schematic diagram of an existing improved N-type shielded trench field-effect transistor. Figure 1 Compared to the previous structure, the source contact trench is formed using a self-aligned method by utilizing a pre-formed hard mask insulating layer 111. There is no gap between the formed source contact trench and the cell trench. This structure can solve the limitation of cell size on photolithography precision. However, the following problems still exist in this structure: the morphology of the N+ doped source region results in a large contact resistance between it and the metal in the source contact trench; in addition, although the distance from the P+ contact doped region to the adjacent cell trench can be adjusted by increasing the etching angle and etching depth of the source contact trench to avoid affecting the doping concentration of the channel region, as the cell size shrinks, the width (C) of the corresponding source contact trench becomes narrower, making the above method difficult to implement. Therefore, it is difficult to avoid the P+ contact doped region affecting the doping concentration of the channel region, resulting in an increase in the on-resistance of the device (especially the on-resistance at low switching thresholds) and a deterioration in the uniformity of the switching threshold.
[0004] Furthermore, reducing the trench spacing (B) leads to a smaller conduction area in the drift region, which is detrimental to further reducing the drift region resistance. Additionally, reducing the cell size of shielded-gate trench MOSFETs results in higher channel density, reducing the safe operating area for linear applications. Therefore, appropriately reducing channel density is beneficial for increasing the safe operating area. Finally, increased trench density in shielded-gate trench MOSFETs can easily lead to wafer warping due to high surface stress, which is detrimental to manufacturing processes and device reliability, and limits the thickness reduction and yield of the thinning process. Summary of the Invention
[0005] To address the aforementioned problems, this invention provides a trench-type field-effect transistor semiconductor device, comprising a first conductivity type semiconductor. The upper surface of the first conductivity type semiconductor has a series of first-type trenches spaced apart along the X-direction and extending along the Z-direction. The first-type trenches are filled with a gate electrode located above the trench and a first-type shielding gate electrode located below the trench and spaced apart from the gate electrode. An upper surface metal is provided above the first conductivity type semiconductor. Between the upper surface of the first conductivity type semiconductor and the first-type trenches, a series of second-type trenches extending discontinuously along the Z-direction are provided. A groove is formed on the upper surface of the second-type trenches, and the upper surface metal fills downward into the groove. Inside, a second type of shielding gate electrode is provided in the second type of trench, and the second type of shielding gate electrode and the trench sidewall are separated by a second oxide layer; a first type of conductive heavy doped source region is also provided between the trenches on the upper surface of the first type of conductive semiconductor, a second type of conductive doped body region is provided below the first type of conductive heavy doped source region, and a second type of conductive contact heavy doped region is also provided between the second type of conductive doped body region and the lower outer sidewall of the trench. The upper surface metal and the first type of conductive heavy doped source region and the second type of conductive contact heavy doped region form an ohmic contact and are connected to the lower second type of shielding gate electrode. The second type of conductive contact heavy doped region is connected to the second type of conductive doped body region and the first type of conductive heavy doped source region.
[0006] Furthermore, the width of the second conductive contact heavily doped region in the X direction is within 0.15 μm.
[0007] Furthermore, the height of the upper surface of the second oxide layer is lower than the height of the upper surface of the second type of shielding gate electrode, forming a semi-annular groove.
[0008] Furthermore, the second type of trench is a polygon with a width C” in the Z direction greater than the width C’ in the X direction;
[0009] Alternatively, the second type of groove may be a regular polygon or a circle.
[0010] Furthermore, the first trench spacing B' is greater than or equal to the second trench spacing B.
[0011] Furthermore, the second trench spacing B” is smaller than the width of the second conductive contact heavily doped region between the second type of trenches in the Z direction, so that the second conductive contact heavily doped regions are interconnected in the Z direction.
[0012] Furthermore, a first conductive heavy doping current diffusion region is provided below the second conductive doped region, wherein the doping concentration of the first conductive heavy doping current diffusion region is higher than that of the drift region.
[0013] Furthermore, the first type of trench extending along the X direction is also provided between the upper surface of the first conductive semiconductor and a portion of the second type of trench.
[0014] Furthermore, the depth of the second type of trench is less than that of the first type of trench.
[0015] Furthermore, the lower part of the first conductivity type semiconductor forms two or more doped regions with different doping concentrations.
[0016] Furthermore, the doped region includes a first drift region located above, between the second type of trench and the first type of trench adjacent in the X direction and between the second type of trench adjacent in the Z direction, and a second drift region located below the second type of trench, between the first type of trench adjacent in the X and Z directions, wherein the doping concentration of the first drift region is higher than that of the second drift region.
[0017] Furthermore, the first type of shielding gate electrode in the first type of trench has a structure that is larger at the top and smaller at the bottom.
[0018] Furthermore, the width of the second type of trench is narrower than that of the first type of trench; or a second conductive shielding doped region is provided below the first type of trench.
[0019] Furthermore, the upper surface height of the second oxide layer is higher than the upper surface height of the second type of shielding gate electrode, and the resulting groove is a hole-shaped groove.
[0020] Furthermore, the first conductivity type heavily doped source region at the first trench spacing B' is deeper than the first conductivity type heavily doped source region at the second trench spacing B”.
[0021] Furthermore, no first conductivity type heavily doped source region is set between adjacent second type trenches.
[0022] The present invention also provides a method for manufacturing a trench field-effect transistor semiconductor device, the method comprising the following steps:
[0023] The first step is to form a first type of trench and a second type of trench on the upper surface of the first conductive semiconductor, and to form a second oxide layer, a first type of shielding gate electrode, and a second type of shielding gate electrode in the trench. Then, a gate oxide layer and a gate electrode are formed in the first type of trench, wherein the height of the upper surface of the gate electrode is 0.3-1 μm from the height of the upper surface of the semiconductor.
[0024] The second step is to perform first conductivity type ion implantation to form a deep first conductivity type heavily doped source region on the sidewall of the first type of trench and a shallow first conductivity type heavily doped source region on the upper surface of the semiconductor near the second type of trench.
[0025] The third step is to fill the trench with insulating material to form an insulating filling layer;
[0026] The fourth step is to perform photolithography to etch the insulating filling layer and the second oxide layer at the top of the second type of trench, exposing the first type of conductive heavily doped source region, the second type of conductive doped body region, and the second type of shielding gate electrode.
[0027] The fifth step is to perform ion implantation to form a second type of conductive contact heavily doped region on the sidewall of the second type of trench;
[0028] The sixth step is to fill the upper surface with metal and form the device.
[0029] Furthermore, in the fifth step, prior to ion implantation, a semiconductor etching step is first performed to remove the exposed shallow first conductivity heavily doped source region.
[0030] This invention proposes a novel shielded trench field-effect transistor (FET) device structure and manufacturing process. Compared to existing device structures, it achieves a higher trench density, lower on-resistance, better switching threshold uniformity, a larger safe operating range, and improved device reliability. Attached Figure Description
[0031] Figure 1 This is a conventional N-type shielded trench field-effect transistor structure;
[0032] Figure 2 This is a schematic diagram of an existing improved N-type shielded trench field-effect transistor.
[0033] Figure 3 This is a schematic diagram of the structure of the device according to Embodiment 1 of the present invention after the upper surface metal has been removed;
[0034] Figure 4 This is a top view of the structure of embodiment 1 of the device of the present invention;
[0035] Figure 5 This is a schematic cross-sectional view of Embodiment 1 of the device of the present invention along the X and Z directions, respectively, and corresponds to Figure 4Tangents L1 and L2;
[0036] Figure 6 This is a top view of the structure of embodiment 6 of the device of the present invention;
[0037] Figure 7 A top view of the structure of the first type of trench 201 and the second type of trench 202 in Embodiment 7 of the invention device;
[0038] Figure 8 This is a schematic diagram of the structure of the device in embodiment 8 of the present invention;
[0039] Figure 9 This is a schematic diagram of the structure of the device in embodiment 14 of the present invention;
[0040] Figure 10 This is a top view of the structure of the first type of trench 201 and the second type of trench 202 in embodiment 15 of the present invention;
[0041] Figure 11 This is a schematic cross-sectional view of embodiment 15 of the device of the present invention along the X and Z directions, respectively, and corresponds to Figure 10 Tangents L1' and L2';
[0042] Figures 12 to 17 For the present invention Figure 11 Key steps of a manufacturing method for an embodiment of the device. Detailed Implementation
[0043] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0044] It should be noted that the positional terms used in this document, such as "up," "down," "left," "right," "front," "back," "vertical," "horizontal," and "vertical," correspond to the relative positions shown in the reference illustrations. No fixed orientation is restricted in actual implementation. It should also be noted that the devices in the accompanying drawings are not necessarily drawn to scale. The straight lines representing the boundaries of doped regions and trenches in the drawings, as well as the sharp angles formed by these boundaries, are generally not straight lines or precise angles in practical applications.
[0045] It should be noted that in the following description of the shielded gate trench field-effect transistor device and its manufacturing method of the present invention, the semiconductor substrate of the shielded gate trench field-effect transistor device is considered to be made of silicon (Si) material. However, the substrate may also be made of any other material suitable for manufacturing shielded gate trench field-effect transistors, such as gallium nitride (GaN), silicon carbide (SiC), etc.
[0046] In the following description, the conductivity type of the semiconductor region is divided into P-type (second conductivity type) and N-type (first conductivity type). A P-type conductivity semiconductor region can be formed by doping the original semiconductor region with one or more impurities. These impurities can be, but are not limited to, boron (B), aluminum (Al), gallium (Ga), etc. An N-type conductivity semiconductor region can also be formed by doping the original semiconductor region with one or more impurities. These impurities can be, but are not limited to, phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), proton (H) + (etc.). In the following description, heavily doped P-type conductive semiconductor regions are labeled as P+ regions, and heavily doped N-type conductive semiconductor regions are labeled as N+ regions. For example, in a silicon substrate, unless otherwise specified, the impurity concentration of a heavily doped region is typically 1 × 10⁻⁶. 19 cm -3 Up to 1×10 22 cm -3 Between. Those skilled in the art should know that the P-type (second conductivity type) and N-type (first conductivity type) described in this invention are interchangeable. Example 1
[0047] Figures 3 to 5 This is a schematic diagram of the structure of the first embodiment of the device of the present invention.
[0048] in, Figure 3 This is a schematic diagram of the device after the metal on its upper surface has been removed. Figure 4 The image shows a top view of the structure of the first type of trench 201 and the second type of trench 202. Figure 5 This is a schematic diagram of cross-sections along the X and Z directions, and corresponds to... Figure 4 Tangents L1 and L2.
[0049] like Figure 3 The semiconductor field-effect transistor device includes:
[0050] A series of first-type trenches 201 located on the upper surface of the N-type semiconductor 200, spaced apart along the X direction and extending in the Z direction;
[0051] The first type of trench 201 is filled with an upper gate electrode 210 and a lower first type of shielded gate electrode 220. The gate electrode 210 is isolated from its corresponding trench sidewall by a gate oxide layer; the first type of shielded gate electrode 220 is isolated from its corresponding trench sidewall by a second oxide layer 231; and the gate electrode 210 and the first type of shielded gate electrode 220 are isolated by an inter-electrode isolation oxide layer. An insulating filling layer 211 is provided above the gate electrode 210 within the first type of trench 201.
[0052] Between adjacent first-type trenches 201, there is a series of second-type trenches 202 that extend discontinuously along the Z direction on the upper surface of the N-type semiconductor 200;
[0053] The second type of trench 202 includes a second type of shielding gate electrode 230 and a second oxide layer 231 between the sidewall of the second type of trench 202 and the second type of shielding gate electrode 230. The upper surface of the second oxide layer 231 of the second type of trench 202 is lower than the upper surface of the second type of shielding gate electrode 230, forming a semi-annular groove 221.
[0054] The N+ doped source region 204 is located between the trenches on the upper surface of the N-type semiconductor 200;
[0055] The P-doped body region 203 is located below the N+ doped source region 204;
[0056] P+ contact doped region 205 located on the lower outer wall of semi-annular groove 221;
[0057] The upper surface metal 222 is located above the N-type semiconductor 200;
[0058] The upper surface metal 222 forms an ohmic contact with the N+ doped source region 204 and the P+ contact doped region 205 on the sidewall of the semi-annular groove 221 through the semi-annular groove 221, and is connected to the lower second type shielding gate electrode 230. The P+ contact doped region 205 is connected to the P doped body region 203 and the N+ doped source region 204.
[0059] Typically, the second oxide layer 231 is thicker than the gate oxide layer.
[0060] Typically, the depth of the semi-annular groove 221, which is also the height of the upper surface of the second oxide layer 231 of the second type of trench 202, lies between the height of the upper surface and the lower surface of the P-doped region 203.
[0061] Typically, the width of the first type of trench 201 in the X direction is between 0.2 and 1.5 μm; the width of the second type of trench 202 in the X direction is between 0.1 and 1.5 μm.
[0062] Typically, the spacing in the X direction between the first type of trench 201 and the second type of trench 202 (the first trench spacing B') is between 0.15 and 0.6 μm.
[0063] like Figure 4 As shown, the opening shape of the second type of trench 202 is rectangular. The width of the second type of trench 202 is the same in both the X and Z directions.
[0064] The first trench spacing B' (the spacing in the X direction between the first type of trench 201 and the second type of trench 202) is equal to the second trench spacing B” (the spacing in the Z direction between adjacent second type of trenches 202).
[0065] The width of the P+ contact doped region 205 in the X direction is less than 0.15 μm to prevent affecting the doping concentration of the P-type channel at the first type trench 201. Example 2
[0066] In some embodiments, the width C” of the second type of groove 202 in the Z direction may be larger than the width C' in the X direction. This setting helps to prevent problems in the groove filling process during manufacturing and helps to increase the process window. Example 3
[0067] In some variations, B' may also be greater than B”. This setting may slightly reduce the overall device breakdown voltage, but it can concentrate the reverse current at the location between the second type of trenches 202, which is beneficial to improving the device's UIS capability. In a practical variation, B” is 80%-100% of B'. Example 4
[0068] In some variations, the second trench spacing B” may be smaller than the width of the P+ contact doped region 205 between the second type of trenches 202 in the Z direction, so that the P+ contact doped regions 205 are interconnected in the Z direction. Example 5
[0069] In some embodiments, an N+ doped current diffusion region 206 is provided below the P-doped region 203, and the doping concentration of the N+ doped current diffusion region 206 is higher than that of the drift region. This helps to prevent excessive current concentration in the XZ plane, prevent thermal failure, and reduce device resistance. It also facilitates better control of the P-type channel length during the manufacturing process.
[0070] Compared to traditional structures, the above-described device, due to the introduction of two types of trenches, has a smaller trench spacing B' and an increased trench density, which is beneficial for further increasing the drift region concentration and reducing drift region resistance. Furthermore, the second type of trenches 202, spaced out in the Z direction, increases the drift region area, further reducing drift region resistance. Simultaneously, in this invention, the channel density (density of the first type of trench 201) does not increase synchronously with the trench density (density of the first type of trench 201 and the second type of trench 202), thus increasing the safe operating area of the device. Additionally, the discontinuous distribution of the second type of trenches 202 in the Z direction helps mitigate the high surface stress caused by the increase in trench density in the X direction, reducing wafer warpage and other problems. Example 6
[0071] Figure 6 A top view of the structure of a second type of trench 202 in a variation of the device of the present invention is shown.
[0072] Compared with the aforementioned embodiments, this embodiment differs in that the opening shape of the second type of trench 202 is circular, which helps to further reduce surface stress and reduce wafer warpage. Example 7
[0073] Figure 7 A top view of the structure of a first type of trench 201 and a second type of trench 202 in another variation of the device of the present invention is shown. Compared to the previous embodiment, this embodiment differs in that a portion of the first type of trenches 201 in the cell is arranged in a crisscross pattern (part of the first type of trenches extends along the X direction) and surrounds the second type of trench 202. This structure facilitates increased channel density and further reduces on-resistance. Example 8
[0074] Figure 8 Another embodiment of the device of the present invention is shown. Compared to the previous embodiment, this embodiment differs in that the depth of the second type of trench 202 is shallower than that of the first type of trench 201. This arrangement helps to reduce surface stress and reduce the output capacitance of the device. Example 9
[0075] exist Figure 8 In a variation of the embodiment, the semiconductor drift region comprises at least two doped regions, such as: a first drift region 207 located above, between the second type trench 202 and the first type trench 201 adjacent in the X direction and between the second type trench 202 adjacent in the Z direction; and a second drift region 208 located below, between the first type trench 201 adjacent in both the X and Z directions, wherein the doping concentration of the first drift region 207 is higher than that of the second drift region 208. This arrangement is beneficial for increasing the breakdown voltage of the device. Example 10
[0076] Furthermore, in some embodiments, a third drift region 209 may be present below the first type of trench 201, the doping concentration of the third drift region being lower than the doping concentration of the semiconductor drift region between the trenches. This arrangement is beneficial for further increasing the breakdown voltage of the device. Example 11
[0077] exist Figure 8 In a variation of the embodiment based on the previous one, the first type of shielding gate electrode 220 in the first type of trench 201 has a structure that is larger at the top and smaller at the bottom, which is beneficial to further reduce the output capacitance of the device. Example 12
[0078] exist Figure 8 In a variation of the embodiment based on the previous one, the width of the second type of trench 202 is narrower than that of the first type of trench 201, which is beneficial to further increase the trench density of the device. Example 13
[0079] exist Figure 8 In a variation of the embodiment based on the previous one, a P-type shielding doped region 212 is provided below the first type of trench 201, which is beneficial to further increase the breakdown voltage of the device. Example 14
[0080] Figure 9 Another embodiment of the device of the present invention is shown. Compared to the previous embodiment, this embodiment differs in that the height of the second oxide layer 231 located above the second type of trench 202 is higher than that of the second type of shielding gate electrode 230. Compared to the semi-annular groove 221 formed in the previous embodiment, this structure forms a hole-like groove 223 that is deep in the middle and shallow around the edges, which is beneficial for metal filling during the manufacturing process and prevents voids. It also helps improve the consistency of the ion implantation process for forming the P+ contact doped region 205 within the wafer.
[0081] The method for forming the hole-shaped groove 223 may be as follows: after forming the insulating filling layer 211, first etch back the second oxide layer 231 located on the upper part of the second type of trench 202, and then etch back the second type of shielding gate electrode 230. Example 15
[0082] Figure 10-11 Another embodiment of the device of the present invention is shown, wherein... Figure 10 The image shows a top view of the structure of the first type of trench 201 and the second type of trench 202. Figure 11 This is a schematic diagram of cross-sections along the X and Z directions, and corresponds to... Figure 10 The tangent lines are L1' and L2'. Compared to the previous embodiment, this embodiment differs in that the N+ doped source region 204 has different depths at different locations. Between the first type of trench 201 and the second type of trench 202, i.e., at position B', is a deep N+ doped source region 214; between adjacent second type trenches 202, i.e., at position B”, is a shallow N+ doped source region 224. This arrangement is beneficial for improving the UIS performance of the device. Example 16
[0083] In some variations, N+ doped source regions 204 may not be provided between adjacent second type trenches 202 to further improve the UIS performance of the device. Example 17
[0084] Figures 12 to 16 The above were shown Figure 11Key steps in a manufacturing method of the device in the embodiment:
[0085] The first step involves forming a first type of trench 201 and a second type of trench 202 on the upper surface of the N-type semiconductor 200. A second oxide layer 231, a first type of shielded gate electrode 220, and a second type of shielded gate electrode 230 are formed within the trenches. Then, a gate oxide layer 219 and a gate electrode 210 are formed within the first type of trench 201. The height of the upper surface of the gate electrode 210 from the upper surface of the semiconductor is 0.3-1 μm. Figure 12 As shown.
[0086] The gate electrode 210 may be formed by first depositing polysilicon and then etching it back.
[0087] The second step involves N-type ion implantation, forming a deep N+ doped source region 214 on the sidewall of the first type trench 201, and a shallow N+ doped source region 224 on the semiconductor upper surface near the second type trench 202. Figure 13 As shown.
[0088] In the above steps, since the gate electrode 210 is 0.3-1 μm above the upper surface in the first type of trench 201, it forms a groove with the semiconductor sidewall. The ion implantation depth of the groove sidewall is determined by the groove depth and is deeper than that of planar implantation. Therefore, the N-type ion implantation step forms a deep N+ doped source region 214 on the sidewall of the first type of trench 201 and a shallow N+ doped source region 224 on the upper surface of the semiconductor near the second type of trench 202.
[0089] N-type ion implantation may involve a tilt angle to increase the implantation depth at the semiconductor sidewalls.
[0090] The third step is to fill the trench with insulating material to form an insulating filling layer 211, such as... Figure 14 As shown.
[0091] The fourth step involves photolithography, etching the insulating filling layer 211 and the second oxide layer 231 at the top of the second type trench 202, exposing the N+ doped source region 204, the P doped body region 203, and the second type shielding gate electrode 230. (Example:) Figure 15 As shown.
[0092] In some embodiments, this step may involve a chemical polishing process followed by etching back to increase the uniformity of the etching.
[0093] The fifth step involves P-type ion implantation to form a P+ contact doped region 205 on the sidewall of the second type of trench 202, as shown below. Figure 16 As shown.
[0094] The sixth step is to fill the upper surface with metal and form the device.
[0095] The P-type ion implantation may be angled to increase the implantation depth at the semiconductor sidewalls. Typically, the P-type implantation concentration is lower than that of the N-type ion implantation in the third step. Example 18
[0096] In some embodiments, in the fifth step described above, a semiconductor etching step may be performed before P-type ion implantation to remove the exposed shallow N+ doped source region 224, such as... Figure 17 As shown. This approach helps to further enhance the device's UIS capability and reduce the device's on-resistance.
[0097] Those skilled in the art will understand that the above manufacturing steps only list the key steps and do not show the complete process for forming the device. Specific detailed manufacturing steps can be obtained and appropriately added to or modified based on common manufacturing processes and general knowledge in the art. For example, the inter-electrode insulating layer (IPD) may be formed by deposition or oxidation methods; the P-doped region 203 may be formed before or after the trench; and the N+-doped current diffusion region 206 may be formed by ion implantation or epitaxy.
[0098] Furthermore, those skilled in the art should understand that the structural features and process steps mentioned in the various embodiments of the present invention can be combined with each other to form more embodiment device structures and manufacturing processes.
Claims
1. A trench-type field-effect transistor semiconductor device, comprising a first conductivity type semiconductor, wherein the upper surface of the first conductivity type semiconductor is provided with a series of first-type trenches spaced apart along the X direction and extending along the Z direction, wherein the first-type trenches are filled with a gate electrode located above the trenches and a first-type shielding gate electrode located below the trenches and spaced apart from the gate electrode; an upper surface metal is provided above the first conductivity type semiconductor, characterized in that, A series of second-type trenches extending discontinuously along the Z-direction are provided between the upper surface of the first conductive semiconductor and the first type of trenches. A groove is formed on the upper surface of the second-type trenches, and the upper surface metal is filled downward into the groove. A second-type shielding gate electrode is provided in the second-type trench, and the second-type shielding gate electrode and the trench sidewall are separated by a second oxide layer. A first-type heavily doped source region is also provided between the trenches on the upper surface of the first conductive semiconductor. A second-type doped body region is provided below the first-type heavily doped source region. A second-type contact heavily doped region is also provided between the second-type doped body region and the lower outer sidewall of the groove. The upper surface metal, the first-type heavily doped source region, and the second-type contact heavily doped region form an ohmic contact and are connected to the lower second-type shielding gate electrode. The second-type contact heavily doped region is connected to the second-type doped body region and the first-type heavily doped source region.
2. The trench field-effect transistor semiconductor device as described in claim 1, characterized in that, The width of the second conductive contact heavily doped region in the X direction is less than 0.15 μm.
3. The trench field-effect transistor semiconductor device as described in claim 1, characterized in that, The height of the upper surface of the second oxide layer is lower than the height of the upper surface of the second type of shielding gate electrode, forming a semi-annular groove.
4. The trench field-effect transistor semiconductor device as described in claim 1, characterized in that, The second type of trench is a polygon whose width C” in the Z direction is greater than its width C' in the X direction; Alternatively, the second type of groove may be a regular polygon or a circle.
5. The trench field-effect transistor semiconductor device as described in claim 1, characterized in that, The distance between the first type of trench and the second type of trench in the X direction is the first trench spacing B', and the distance between adjacent second type of trenches in the Z direction is the second trench spacing B', where the first trench spacing B' is greater than or equal to the second trench spacing B'.
6. The trench field-effect transistor semiconductor device as described in claim 5, characterized in that, The second trench spacing B” is less than the width of the second conductive contact heavily doped region in the Z direction between the second type of trenches, so that the second conductive contact heavily doped regions are connected to each other in the Z direction.
7. The trench field-effect transistor semiconductor device as described in claim 1, characterized in that, Below the second conductivity doped region is a first conductivity heavily doped current diffusion region, wherein the doping concentration of the first conductivity heavily doped current diffusion region is higher than that of the drift region.
8. The trench field-effect transistor semiconductor device as described in claim 1, characterized in that, The first type of conductive semiconductor is further provided with a first type of trench extending in the X direction between the upper surface of the first type of conductive semiconductor and a portion of the second type of trench.
9. The trench field-effect transistor semiconductor device as described in claim 1, characterized in that, The second type of trench is less deep than the first type of trench.
10. The trench field-effect transistor semiconductor device as described in claim 9, characterized in that, The lower part of the first conductivity type semiconductor forms two or more doped regions with different doping concentrations.
11. The trench field-effect transistor semiconductor device as described in claim 10, characterized in that, The doped region includes a first drift region located above, between the second type of trench and the first type of trench adjacent in the X direction and between the second type of trench adjacent in the Z direction, and a second drift region located below the second type of trench, between the first type of trench adjacent in the X and Z directions. The doping concentration of the first drift region is higher than that of the second drift region.
12. The trench field-effect transistor semiconductor device as described in claim 9, characterized in that, The first type of shielding gate electrode in the first type of trench has a structure that is larger at the top and smaller at the bottom.
13. The trench field-effect transistor semiconductor device as described in claim 9, characterized in that, The width of the second type of trench is narrower than that of the first type of trench; or Below the first type of trench, there is also a second conductive shielding doped region.
14. The trench field-effect transistor semiconductor device as described in claim 1, characterized in that, The upper surface height of the second oxide layer is higher than the upper surface height of the second type of shielding gate electrode, forming a pore-shaped groove.
15. The trench field-effect transistor semiconductor device as described in claim 1, characterized in that, The distance between the first type of trench and the second type of trench in the X direction is the first trench spacing B', and the distance between adjacent second type of trenches in the Z direction is the second trench spacing B”, wherein the first conductivity type heavily doped source region at the first trench spacing B' position is deeper than the first conductivity type heavily doped source region at the second trench spacing B” position.
16. The trench field-effect transistor semiconductor device as described in claim 1, characterized in that, No first conductivity type heavily doped source region is set between adjacent second type trenches.
17. A method for manufacturing a trench field-effect transistor semiconductor device as described in any one of claims 1-16, characterized in that, The manufacturing method includes the following steps: The first step is to form a first type of trench and a second type of trench on the upper surface of the first conductive semiconductor, and to form a second oxide layer, a first type of shielding gate electrode, and a second type of shielding gate electrode in the trench. Then, a gate oxide layer and a gate electrode are formed in the first type of trench, wherein the height of the upper surface of the gate electrode is 0.3-1 μm from the height of the upper surface of the semiconductor. The second step is to perform first conductivity type ion implantation to form a deep first conductivity type heavily doped source region on the sidewall of the first type of trench and a shallow first conductivity type heavily doped source region on the upper surface of the semiconductor near the second type of trench. The third step is to fill the trench with insulating material to form an insulating filling layer; The fourth step is to perform photolithography to etch the insulating filling layer and the second oxide layer at the top of the second type of trench, exposing the first type of conductive heavily doped source region, the second type of conductive doped body region, and the second type of shielding gate electrode. The fifth step is to perform ion implantation to form a second type of conductive contact heavily doped region on the sidewall of the second type of trench; The sixth step is to fill the upper surface with metal and form the device.
18. A method for manufacturing a trench field-effect transistor semiconductor device as described in claim 17, characterized in that, In the fifth step, prior to ion implantation, a semiconductor etching step is first performed to remove the exposed shallow first conductivity heavily doped source region.