A semiconductor device having a gate dielectric stack and a method of fabricating the same

By introducing a non-volatile charge storage structure with a high dielectric constant layer and a tunneling layer in the vertical MOSFET, the transconductance limitation and leakage problems caused by the lateral uniformity of gate stacking in the prior art are solved, and more efficient power device switching performance is achieved.

CN122028479BActive Publication Date: 2026-07-21SAIJING ASIA PACIFIC SEMICON TECH (ZHEJIANG) CO LTD +1
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2026-04-15
Publication Date
2026-07-21

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Abstract

The present application relates to a kind of semiconductor devices with engineering gate dielectric stack and its preparation method;Semiconductor substrate top surface is provided with gate stack layer, gate stack layer extends from adjacent one source to another source and covers drift region and channel laterally;Gate stack layer includes high dielectric constant layer, tunneling layer, also includes the floating dielectric layer covering high dielectric constant layer and tunneling layer, the second dielectric layer covering floating dielectric layer, the control gate layer covering second dielectric layer;Gate stack layer is wrapped with interlayer dielectric;Interlayer dielectric is wrapped with source metal layer;Semiconductor substrate bottom surface is provided with back metal layer;Through the semiconductor device with engineering gate dielectric stack is proposed to solve the technical problems in the prior art that gate stack is generally uniform on channel and drift region, and combining programming requirements with on-state behavior, which will limit transconductance, increase gate leakage under voltage of power device.
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Citation Information

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