A trench SiC JFET device structure with an asymmetric gate and its fabrication method
By constructing highly doped conductive channels in trench SiC JFET devices, the problem of controlling trench etching precision was solved, the current density and production yield of the devices were improved, the specific on-resistance was reduced, and a high process window was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING THIRD GENERATION SEMICON TECH INNOVATION CENT CO LTD
- Filing Date
- 2026-04-14
- Publication Date
- 2026-06-19
AI Technical Summary
In the manufacturing process of existing trench-type SiC JFET devices, the accuracy of trench etching is difficult to control, which affects the conduction and blocking characteristics of the device, leading to increased reverse leakage current or deterioration of on-resistance.
A trench SiC JFET device structure with an asymmetric gate is adopted. By constructing a highly doped conductive channel through ion implantation in the channel region, the device structure is optimized and the manufacturing process controllability of the trench SiC JFET device is improved.
This improved the device's current density and production yield, reduced the specific on-resistance, and achieved a high process window and high production yield.
Smart Images
Figure CN122028480B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronic device technology, and in particular to a trench SiC JFET device structure with an asymmetric gate and its manufacturing method. Background Technology
[0002] Silicon carbide junction field-effect transistors (SiC JFETs) have a gate oxide-free structure, high operating temperature, low specific on-resistance, and high reliability, making them valuable for applications in solid-state circuit breakers, peak load regulators, electronic fuses, and other fields.
[0003] Trench-type SiC JFETs have the advantages of small cell size and high current density. (See attached image) Figure 1 As shown, in the existing technology, the working principle of a conventional symmetrical gate trench SiC JFET device is as follows: when the gate-source voltage V... GS ≥threshold voltage V (GS)TH When V is open, the channel is open, and current flows through the first conductivity type channel layer; when V GS <threshold voltage V (GS)TH At that time, the ditch was closed.
[0004] Existing trench-type SiC JFET devices face manufacturing challenges in controlling trench etching precision, including trench depth, trench width, and trench angle. The device's conduction and blocking characteristics are closely related to the trench dimensions. For example, when the trench depth is too shallow, the channel pinch-off effect is weakened, and reverse leakage current increases; conversely, a deeper trench results in deteriorated on-resistance. Summary of the Invention
[0005] Technical Objective: To address the shortcomings of existing technologies in controlling trench etching precision, this invention provides a trench SiC JFET device structure with an asymmetric gate and its manufacturing method. By optimizing the device structure, namely by precisely constructing highly doped conductive channels in the channel region through ion implantation, the controllability of the trench SiC JFET device manufacturing process is improved, and the device current density is further increased.
[0006] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution.
[0007] A method for fabricating an asymmetric gate trench SiC JFET device structure includes the following steps:
[0008] Step 1: Sequentially grow the first conductivity type withstand voltage layer, the first conductivity type current spreading layer, and the first conductivity type channel layer material from bottom to top on the first conductivity type substrate;
[0009] Step 2: Form a source region material of the first conductivity type on the channel layer material of the first conductivity type;
[0010] Step 3: Form a mask on the first conductivity type source region material, and etch the first conductivity type channel layer material and the first conductivity type source region material based on the mask to form trenches and the first conductivity type channel layer and the first conductivity type source region located in the trenches. The trenches on both sides of the first conductivity type channel layer and the first conductivity type source region are the first feature trench and the second feature trench, respectively.
[0011] Step 4: Perform tilted ion implantation on the first conductivity type channel layer, so that a second conductivity type sidewall gate region is formed on the sidewall of the first conductivity type channel layer near the second feature trench.
[0012] Step 5: Form a bottom gate region of the second conductivity type on the surface of the first conductivity type current extension layer at the bottom of the trench by vertical ion implantation;
[0013] Step 6: Perform tilted ion implantation on the first conductivity type channel layer, so that a first conductivity type highly doped channel is formed on the sidewall of the first conductivity type channel layer near the first feature trench; the first conductivity type highly doped channel connects the first conductivity type source region and the first conductivity type current spread layer;
[0014] Step 7: Remove the mask to form dielectric sidewalls located on the sidewalls of the first feature trench and the second feature trench; the dielectric sidewalls mask the highly doped channel of the first conductivity type and the sidewall gate region of the second conductivity type, exposing the bottom gate region of the second conductivity type and the source region of the first conductivity type;
[0015] Step 8: Form a source alloy at the top of the source region of the first conductivity type; form a gate alloy at the bottom of the trench and at the top of the bottom gate region of the second conductivity type;
[0016] Step 9: Form a passivation dielectric layer that fills the trench;
[0017] Step 10: Form a source metal electrode on the passivation dielectric layer and the source alloy; form a drain metal electrode at the bottom of the first conductivity type substrate.
[0018] Preferably, in step 4, the tilted ion implantation angle ranges from 7° to 45°, the implantation energy ranges from 10 keV to 500 keV, and the implantation dose is 5 E12 / cm². 2 -1E14 / cm 2 .
[0019] Preferably, in step 6, the tilted ion implantation angle ranges from 7° to 45°, the implantation energy ranges from 50 keV to 700 keV, and the implantation dose is 5E12 / cm². 2 -1E14 / cm 2 .
[0020] Preferably, the tilted ion implantation in steps 4 and 6 is carried out in the form of multiple implantations.
[0021] Preferably, in step 5, the implantation energy of vertical ion implantation is ≥30 keV, and the implantation dose range is 1E13 / cm. 2 -1E15 / cm 2 .
[0022] Preferably, the source metal electrode, drain metal electrode, gate alloy, and source alloy are made of one or more combinations of Ti, Al, Ni, Pt, and Ag metals.
[0023] Preferably, the passivation dielectric layer material is silicon nitride, silicon oxide, or a composite dielectric of silicon nitride and silicon oxide.
[0024] Preferably, the doping concentration range of the first conductivity type withstand layer is 1e14cm. -3 ~5e16cm -3 The doping concentration range of the first conductivity type current spreading layer is 1e15cm. -3 ~1e17cm -3 The doping concentration range of the first conductivity type channel layer is 1e14cm. -3 ~5e16cm -3 The doping concentration range of the source region for the first conductivity type is 1e17cm. -3 ~ 1e19cm -3 .
[0025] Preferably, the width of the first conductive type channel layer is in the range of 0.2μm-2μm.
[0026] This invention also discloses an asymmetric gate trench SiC JFET device structure, fabricated by any of the above-described methods for manufacturing an asymmetric gate trench SiC JFET device structure, comprising:
[0027] Drain metal electrode; a first conductivity type substrate located on the drain metal electrode; a first conductivity type withstand layer located on the first conductivity type substrate; a first conductivity type current spreading layer located on the first conductivity type withstand layer;
[0028] A first conductivity type channel layer is located above the first conductivity type current extension layer; a first conductivity type source region is located above the first conductivity type channel layer; trenches are located on both sides of the first conductivity type channel layer and the first conductivity type source region, which are respectively the first characteristic trench and the second characteristic trench;
[0029] The second conductivity type sidewall gate region is located on the sidewall of the first conductivity type channel layer near the second feature trench.
[0030] The second conductivity type bottom gate region is located on the surface of the first conductivity type current extension layer, on both sides of the first conductivity type channel layer, and at the bottom of the trench;
[0031] A first conductivity type highly doped channel is located on the sidewall of the first conductivity type channel layer near the first feature trench. The first conductivity type highly doped channel connects the first conductivity type source region and the first conductivity type current spread layer.
[0032] Dielectric sidewalls located on both sides of the first conductivity type channel layer;
[0033] The source alloy located above the source region of the first conductivity type; the gate alloy located above the bottom gate region of the second conductivity type and at the bottom of the trench;
[0034] A passivation dielectric layer that fills the trench and sits on top of the gate alloy;
[0035] The source metal electrode is located above the passivation dielectric layer and above the source alloy.
[0036] Beneficial effects:
[0037] 1. This invention precisely constructs highly doped conductive channels in the channel region through ion implantation, thereby solving the problem that traditional trench SiC JFET device structures are sensitive to channel thickness, height, and angle. It has strong manufacturability and is a SiC JFET device structure and manufacturing method with high process window and high production yield.
[0038] 2. Compared with traditional double-sidewall gate trench SiC JFET devices, its channel width can be narrower, and its cell size can be smaller, thereby increasing current density and reducing specific on-resistance. Attached Figure Description
[0039] Figure 1 This is a schematic diagram of a gate-symmetric trench SiC JFET device structure in the prior art;
[0040] Figure 2 This is a schematic diagram of an asymmetric gate trench SiC JFET device structure according to an embodiment of the present invention.
[0041] Figures 3-16 This is a schematic diagram of a manufacturing process for a trench SiC JFET device structure with an asymmetric gate, as shown in the embodiment.
[0042] The components are as follows: 1. First conductivity type substrate; 2. First conductivity type withstand voltage layer; 3. First conductivity type current spread layer; 4. First conductivity type channel layer; 4'. First conductivity type channel layer material; 4-1. First feature trench; 4-2. Second feature trench; 5. First conductivity type source region; 5'. First conductivity type source region material; 6. Mask; 7. Second conductivity type sidewall gate region; 7-1. Second conductivity type doped region one; 7-2. Second conductivity type doped region two; 8. Second conductivity type bottom gate region; 9. First conductivity type highly doped channel; 10. Dielectric sidewall; 10'. Dielectric layer material; 11-1. Source alloy; 11-2. Gate alloy; 12. Passivation dielectric layer; 12'. Passivation dielectric layer material; 13. Source metal electrode; 14. Drain metal electrode. Detailed Implementation
[0043] The present invention will be further explained and described below with reference to the accompanying drawings and embodiments.
[0044] The embodiments are for illustrative purposes only and do not constitute a limitation on the scope of the claims. Other alternative means that can be conceived by those skilled in the art are all within the scope of the claims of this invention.
[0045] Furthermore, in the description of this invention, it should be noted that the terms "central," "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0046] Example: As attached Figure 3 - Appendix Figure 16 As shown, this invention discloses a method for manufacturing a trench SiC JFET device structure with an asymmetric gate, comprising the following steps:
[0047] Step 1: Sequentially grow the following layers on the first conductivity type substrate 1: first conductivity type withstand voltage layer 2, first conductivity type current spreading layer 3, and first conductivity type channel layer material 4' from bottom to top.
[0048] The thickness of the first conductive type withstand voltage layer 2 is determined by the device withstand voltage requirements, as shown in Table 1; the thickness of the first conductive type current spreading layer 3 is generally 0.5μm-3μm, and the thickness of the first conductive type channel layer material 4' is generally 1μm-5μm.
[0049] Table 1 Recommended Thickness of the First Conductivity Type Voltage-Resistant Layer 2
[0050]
[0051] like Figure 3 and Figure 4 As shown, a first conductivity type withstand voltage layer 2 is formed on a first conductivity type substrate 1 by epitaxial growth. The doping concentration range of the first conductivity type withstand voltage layer 2 is generally 1e14cm. -3 ~5e16cm -3 The first conductivity type substrate 1 is a first conductivity type SiC substrate, and the first conductivity type withstand voltage layer 2 is a first conductivity type SiC epitaxial layer. The semiconductor material can be 3C-SiC, 4H-SiC, or 6H-SiC. Then, a first conductivity type current spreading layer 3 is formed by epitaxial growth of the first conductivity type withstand voltage layer 2. Its doping concentration is higher than that of the first conductivity type withstand voltage layer 2, and the range is generally 1e15cm. -3 ~1e17cm -3 The first conductivity type current spreading layer 3 is a first conductivity type SiC epitaxial layer, and the semiconductor material can be 3C-SiC, 4H-SiC, or 6H-SiC. Then, a first conductivity type channel layer material 4' is formed by epitaxial growth of the first conductivity type current spreading layer 3, and its doping concentration is lower than that of the first conductivity type current spreading layer 3, typically ranging from 1e14cm. -3 ~5e16cm -3 The first conductivity type channel layer 4 is a first conductivity type SiC epitaxial layer, and the semiconductor material can be 3C-SiC, 4H-SiC or 6H-SiC;
[0052] Step 2: Form a first conductivity type source region material 5' on the first conductivity type channel layer material 4';
[0053] like Figure 5 As shown, on the surface of the SiC wafer prepared in step 1, an ion implantation process is used to form a source region material 5' of the first conductivity type on the surface of the first conductivity type channel layer material 4', with a doping concentration ranging from 1e17cm. -3 ~ 1e19cm -3 .
[0054] Step 3: Form a mask 6 on the first conductivity type source region material 5', and etch the first conductivity type channel layer material 4' and the first conductivity type source region material 5' based on the mask 6 to form trenches and the first conductivity type channel layer 4 and the first conductivity type source region 5 located in the trenches. The first conductivity type channel layer 4 and the first conductivity type source region 5 are both columnar and have the same width as the mask 6. The trenches on both sides of the first conductivity type channel layer 4 and the first conductivity type source region 5 are the first feature trench 4-1 and the second feature trench 4-2, respectively.
[0055] like Figure 6 As shown, on the surface of the SiC wafer prepared in step 2, a mask layer is grown by chemical vapor deposition. Then, the mask layer is patterned by photolithography and etching processes to form mask 6, which serves as an etching and implantation mask. Next, the exposed first conductivity type source region material 5' and first conductivity type channel layer material 4' are etched to form a first feature trench 4-1 and a second feature trench 4-2, as well as a columnar first conductivity type channel layer 4 and a first conductivity type source region 5 located between the first feature trench 4-1 and the second feature trench 4-2. The width of the first conductivity type channel layer 4 and the first conductivity type source region 5 is the same as the width of mask 6, with a width Wch typically ranging from 0.2 μm to 2 μm. The thickness of the first conductivity type channel layer 4 ranges from 1 μm to 5 μm.
[0056] Step 4: Perform tilted ion implantation on the first conductivity type channel layer 4, so that the first conductivity type channel layer 4 forms a second conductivity type sidewall gate region 7 on one side wall near the second feature trench 4-2; In this invention, the second conductivity type sidewall gate region 7 is a single-sided structure, which is different from the structure of conventional JFETs where both sides are second conductivity type sidewall gate regions 7.
[0057] like Figure 7 As shown, on the SiC wafer surface prepared in step 3, a second conductivity type sidewall gate region 7 is formed on the sidewall of the first conductivity type channel layer 4 near the second feature trench 4-2 by tilted ion implantation. At this time, due to the shadowing effect, a second conductivity type doped region is also formed on the top of part of the first conductivity type current extension layer 3, including a second conductivity type doped region 7-1 located at the bottom of the first feature trench 4-1 and a second conductivity type doped region 7-2 located at the bottom of the second feature trench 4-2; the second conductivity type doped region 7-2 is connected to the second conductivity type sidewall gate region 7; the tilted ion implantation angle range is 7°-45°, the implantation energy range is 10keV-500keV, and the implantation dose is 5E12 / cm. 2 -1E14 / cm 2 In step 4, the tilted ion implantation can be performed in multiple implantations. In this invention, the second conductivity type sidewall gate region 7 contacts the first conductivity type source region 5 to form a PN junction.
[0058] Step 5: Form a second conductivity type bottom gate region 8 on the surface of the first conductivity type current extension layer 3 at the bottom of the trench by vertical ion implantation;
[0059] like Figure 8As shown, on the SiC wafer surface prepared in step 4, a second conductivity type bottom gate region 8 is formed at the bottom of the first feature trench 4-1 and the second feature trench 4-2, i.e., on the surface of the first conductivity type current extension layer 3, by vertical ion implantation. The implantation energy is ≥30keV, and the implantation dose range is 1E13 / cm. 2 -1E15 / cm 2 ,from Figure 8 As can be seen, the second conductivity type doped region is covered as the second conductivity type bottom gate region 8, and the vertical ion implantation in step 5 can be carried out in the form of multiple implantations.
[0060] Step 6: Perform tilted ion implantation on the first conductivity type channel layer 4, so that a first conductivity type highly doped channel 9 is formed on the side wall of the first conductivity type channel layer 4 near the first feature trench 4-1; the first conductivity type highly doped channel 9 connects the first conductivity type source region 5 and the first conductivity type current extension layer 3;
[0061] like Figure 9 As shown, on the SiC wafer surface prepared in step 5, a first conductivity type highly doped channel 9 is formed on the sidewall of the first conductivity type channel layer 4 near the first feature trench 4-1 by tilted ion implantation. This channel connects the first conductivity type source region 5 and the first conductivity type current extension layer 3. The tilted ion implantation angle ranges from 7° to 45°, the implantation energy ranges from 50 keV to 700 keV, and the implantation dose is 5E12 / cm. 2 -1E14 / cm 2 In step 6, the tilted ion implantation can be performed in multiple implantations. This invention introduces a first conductivity type highly doped channel 9, decoupling the relationship between channel resistance and Wch. Compared with the requirement in conventional JFET devices that Wch cannot be too small, otherwise the channel resistance will be very large, the channel resistance of this invention is only related to the first conductivity type highly doped channel 9 and is basically unrelated to Wch. Therefore, the width of the first conductivity type channel layer in this invention can be narrower.
[0062] Step 7: Remove mask 6 to form dielectric sidewall 10 located on the sidewalls of the first feature trench 4-1 and the second feature trench 4-2; dielectric sidewall 10 masks the first conductivity type highly doped channel 9 and the second conductivity type sidewall gate region 7, and exposes the second conductivity type bottom gate region 8 and the first conductivity type source region 5;
[0063] like Figure 10 , Figure 11As shown, on the surface of the SiC wafer prepared in step 6, the mask 6 is removed by a wet process, and then the dielectric layer material 10' is deposited by a chemical vapor deposition process. Then, the wafer is reverse-etched by anisotropic etching process, leaving the dielectric sidewalls 10 on both sides of the first characteristic trench 4-1 and the second characteristic trench 4-2, that is, the first conductivity type channel layer 4. The first conductivity type source region 5 and the second conductivity type bottom gate region 8 are exposed. The dielectric sidewalls 10 mask the sidewalls, that is, they mask the first conductivity type highly doped channel 9 and the second conductivity type sidewall gate region 7.
[0064] Step 8: Form source alloy 11-1 at the top of the first conductivity type source region 5; form gate alloy 11-2 at the bottom of the trench and the top of the second conductivity type bottom gate region 8;
[0065] like Figure 12 As shown, on the SiC wafer surface prepared in step 7, ohmic metal is deposited by sputtering or evaporation and then annealed to form metal silicides in the exposed first conductivity type source region 5 and second conductivity type bottom gate region 8, which are source alloy 11-1 and gate alloy 11-2, respectively. The dielectric sidewall 10 cannot form metal silicides with the ohmic metal, and the ohmic metal that has not formed metal silicides is removed by a wet process. In this invention, the second conductivity type sidewall gate region 7 is electrically connected to the gate alloy 11-2. The gate alloy 11-2 is used to lead out the second conductivity type sidewall gate region 7 through metal so that when the device is applied to the circuit, the signal can be applied to the second conductivity type sidewall gate region 7.
[0066] Step 9: Form a passivation dielectric layer 12 that fills the trench;
[0067] like Figure 13 and attached Figure 14 As shown, on the surface of the SiC wafer prepared in step 8, a passivation dielectric layer material 12' is deposited by chemical vapor deposition to fill the first feature trench 4-1 and the second feature trench 4-2, and to cover the source alloy 11-1. Then, the passivation dielectric layer material 12' is reverse-etched using anisotropic etching, with an etching thickness of 1.1 to 1.5 times the thickness of the passivation dielectric layer 12, exposing the source alloy 11-1. The thickness of the passivation dielectric layer material 12' ranges from 3 μm to 5 μm. The thickness of the passivation dielectric layer material 12' is greater than the etching depth of the trenches, typically 0.2 to 1.5 times the etching depth. The passivation dielectric layer material 12' is generally silicon nitride, silicon oxide, or a composite dielectric of silicon nitride and silicon oxide.
[0068] Step 10: Form a source metal electrode 13 on the passivation dielectric layer 12 and the source alloy 11-1; form a drain metal electrode 14 at the bottom of the first conductivity type substrate 1;
[0069] like Figure 15 and Figure 16 As shown, on the surface of the SiC wafer prepared in step 9, a source metal electrode 13 is deposited by sputtering or evaporation; on the bottom layer of the SiC wafer prepared in step 9, i.e. the bottom of the first conductivity type substrate 1, an ohmic metal is deposited by sputtering or evaporation and then annealed to form a drain metal electrode 14.
[0070] In this embodiment, the source metal electrode 13, drain metal electrode 14, gate alloy and source alloy are made of one or more combinations of metals such as Ti, Al, Ni, Pt and Ag; the ohmic metal is made of a different material than the source metal electrode 13 and drain metal electrode 14, and is generally made of titanium, nickel, cobalt, platinum, tungsten or a combination thereof.
[0071] As attached Figure 2 As shown, this embodiment also discloses an asymmetric gate trench SiC JFET device structure, which is manufactured using the above method, including:
[0072] Drain metal electrode 14;
[0073] A first conductivity type substrate 1 is located on the drain metal electrode 14; the first conductivity type substrate 1 is a first conductivity type SiC substrate.
[0074] A first conductivity type withstand layer 2 is located on a first conductivity type substrate 1; the first conductivity type withstand layer 2 is a first conductivity type SiC epitaxial layer.
[0075] A first conductivity type current spreading layer 3 is located on top of the first conductivity type withstand voltage layer 2; the first conductivity type current spreading layer 3 is a first conductivity type SiC epitaxial layer.
[0076] A first conductivity type channel layer 4 located above the first conductivity type current extension layer 3; a first conductivity type source region 5 located above the first conductivity type channel layer 4;
[0077] The first conductivity type channel layer 4 and the first conductivity type source region 5 are trenches on both sides, namely the first characteristic trench 4-1 and the second characteristic trench 4-2, respectively.
[0078] The second conductive type sidewall gate region 7 is located on the sidewall of the first conductive type channel layer 4 near the second feature trench 4-2;
[0079] The second conductive type bottom gate region 8 is located on the surface of the first conductive type current extension layer 3, on both sides of the first conductive type channel layer 4, and at the bottom of the trench;
[0080] A first conductivity type highly doped channel 9 is located on the side wall of the first conductivity type channel layer 4 near the first feature trench 4-1. The first conductivity type highly doped channel 9 connects the first conductivity type source region 5 and the first conductivity type current extension layer 3.
[0081] Dielectric sidewalls 10 located on both sides of the first conductivity type channel layer 4;
[0082] Source alloy 11-1 located above source region 5 of the first conductivity type;
[0083] Gate alloy 11-2 located above the bottom gate region of the second conductivity type and at the bottom of the trench;
[0084] A passivation dielectric layer 12, located above the gate alloy 11-2 and filling the trench;
[0085] The source metal electrode 13 is located above the passivation dielectric layer 12 and above the source alloy 11-1.
[0086] In this invention, the first conductivity type is N-type or P-type, and the second conductivity type is P-type or N-type. The cell arrangement can be in the form of bars, hexagons, squares, or atomic lattices, etc.
[0087] The working principle of the device in this embodiment is as follows:
[0088] When the gate-source voltage V GS <threshold voltage V (GS)TH At that time, the ditch was closed.
[0089] When the gate-source voltage V GS ≥threshold voltage V (GS)TH When the channel is turned on, because the doping concentration of the highly doped channel 9 of the first conductivity type is much higher than that of the channel layer 4 of the first conductivity type, current flows through the highly doped channel 9 of the first conductivity type. The benefit is that the channel on-resistance characteristics after the channel is turned on are determined by the highly doped channel of the first conductivity type. Because it is formed by ion implantation, it has precise and controllable process and is not sensitive to the width of the first conductivity type channel layer, sidewall angle, doping concentration, and the sidewall gate region of the second conductivity type. In contrast, traditional trench SiC JFET devices are very sensitive to the width of the first conductivity type channel layer, sidewall angle, doping concentration, and the sidewall gate region of the second conductivity type, and have a narrow process window. Therefore, this invention has the characteristic of high production yield. At the same time, because a single sidewall gate region is used, the width of the first conductivity type channel layer can be narrower, thereby reducing the cell size and increasing the current density. Therefore, this invention also has the characteristic of high performance.
[0090] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A method for manufacturing a trench SiC JFET device structure with an asymmetric gate, characterized in that: Includes the following steps: Step 1: Sequentially grow the first conductivity type withstand voltage layer, the first conductivity type current spreading layer, and the first conductivity type channel layer material from bottom to top on the first conductivity type substrate; Step 2: Form a source region material of the first conductivity type on the channel layer material of the first conductivity type; Step 3: Form a mask on the first conductivity type source region material, and etch the first conductivity type channel layer material and the first conductivity type source region material based on the mask to form trenches and the first conductivity type channel layer and the first conductivity type source region located in the trenches. The trenches on both sides of the first conductivity type channel layer and the first conductivity type source region are the first feature trench and the second feature trench, respectively. Step 4: Perform tilted ion implantation on the first conductivity type channel layer, so that a second conductivity type sidewall gate region is formed on the sidewall of the first conductivity type channel layer near the second feature trench. Step 5: Form a bottom gate region of the second conductivity type on the surface of the first conductivity type current extension layer at the bottom of the trench by vertical ion implantation; Step 6: Perform tilted ion implantation on the first conductivity type channel layer, so that a first conductivity type highly doped channel is formed on the sidewall of the first conductivity type channel layer near the first feature trench; the first conductivity type highly doped channel connects the first conductivity type source region and the first conductivity type current spread layer; the doping concentration of the first conductivity type highly doped channel is much higher than that of the first conductivity type channel layer. Step 7: Remove the mask to form dielectric sidewalls located on the sidewalls of the first feature trench and the second feature trench; the dielectric sidewalls mask the highly doped channel of the first conductivity type and the sidewall gate region of the second conductivity type, exposing the bottom gate region of the second conductivity type and the source region of the first conductivity type; Step 8: Form a source alloy on top of the source region of the first conductivity type; A gate alloy is formed at the bottom of the trench and at the top of the bottom gate region of the second conductivity type; Step 9: Form a passivation dielectric layer that fills the trench; Step 10: Form a source metal electrode on the passivation dielectric layer and the source alloy; form a drain metal electrode at the bottom of the first conductivity type substrate.
2. The method for manufacturing an asymmetric gate trench SiC JFET device structure according to claim 1, characterized in that: In step 4, the tilted ion implantation angle ranges from 7° to 45°, the implantation energy ranges from 10 keV to 500 keV, and the implantation dose is 5 E12 / cm². 2 -1E14 / cm 2 .
3. The method for manufacturing an asymmetric gate trench SiC JFET device structure according to claim 1, characterized in that: In step 6, the tilted ion implantation angle ranges from 7° to 45°, the implantation energy ranges from 50 keV to 700 keV, and the implantation dose is 5 E12 / cm². 2 -1E14 / cm 2 .
4. The method for manufacturing an asymmetric gate trench SiC JFET device structure according to claim 1, characterized in that: The tilted ion implantation in steps 4 and 6 is performed in multiple implantation steps.
5. The method for manufacturing an asymmetric gate trench SiC JFET device structure according to claim 1, characterized in that: In step 5, the vertical ion implantation energy is ≥30 keV, and the implantation dose range is 1E13 / cm. 2 -1E15 / cm 2 .
6. The method for manufacturing an asymmetric gate trench SiC JFET device structure according to claim 1, characterized in that: The source metal electrode, drain metal electrode, gate alloy, and source alloy are made of one or more combinations of Ti, Al, Ni, Pt, and Ag metals.
7. The method for manufacturing an asymmetric gate trench SiC JFET device structure according to claim 1, characterized in that: The passivation dielectric layer material is silicon nitride, silicon oxide, or a composite dielectric of silicon nitride and silicon oxide.
8. The method for manufacturing an asymmetric gate trench SiC JFET device structure according to claim 1, characterized in that: The doping concentration range of the first conductivity type withstand layer is 1e14cm. -3 ~5e16cm -3 The doping concentration range of the first conductivity type current spreading layer is 1e15cm. -3 ~1e17cm -3 The doping concentration range of the first conductivity type channel layer is 1e14cm. -3 ~5e16cm -3 The doping concentration range of the source region for the first conductivity type is 1e17cm. -3 ~ 1e19cm -3 .
9. The method for manufacturing an asymmetric gate trench SiC JFET device structure according to claim 1, characterized in that: The width of the first conductivity type channel layer ranges from 0.2 μm to 2 μm.
10. A trench SiC JFET device structure with an asymmetric gate, manufactured by the method for manufacturing an asymmetric gate trench SiC JFET device structure as described in any one of claims 1-9, characterized in that, include: Drain metal electrode; A first conductivity type substrate located above the drain metal electrode; A first conductivity type withstand layer located on a first conductivity type substrate; A first conductivity type current spreading layer located above a first conductivity type withstand voltage layer; A first conductivity type channel layer located above a first conductivity type current extension layer; A first conductivity type source region is located above a first conductivity type channel layer; the first conductivity type channel layer and the first conductivity type source region are trenches on both sides, namely a first characteristic trench and a second characteristic trench, respectively; The second conductivity type sidewall gate region is located on the sidewall of the first conductivity type channel layer near the second feature trench. The second conductivity type bottom gate region is located on the surface of the first conductivity type current extension layer, on both sides of the first conductivity type channel layer, and at the bottom of the trench; A first conductivity type highly doped channel is located on the sidewall of the first conductivity type channel layer near the first feature trench. The first conductivity type highly doped channel connects the first conductivity type source region and the first conductivity type current spread layer. Dielectric sidewalls located on both sides of the first conductivity type channel layer; Source alloy located above the source region of the first conductivity type; Gate alloy located above the bottom gate region of the second conductivity type and at the bottom of the trench; A passivation dielectric layer that fills the trench and sits on top of the gate alloy; The source metal electrode is located above the passivation dielectric layer and above the source alloy.