A gallium integrated circuit chip and a method of manufacturing the same

Abstract

This invention discloses a gallium integrated circuit chip and its fabrication method, belonging to the field of semiconductor device integration technology. The gallium integrated circuit chip includes a basic circuit module composed of a primary transistor and a secondary transistor connected together. The drain of the secondary transistor is connected to the gate of the primary transistor, and their sources are connected together. The gates of the primary and secondary transistors receive inverted input signals. When the primary transistor experiences gate voltage ringing due to switching coupling of adjacent circuits, the conducting secondary transistor provides a discharge path for its gate charge, suppressing mis-conduction. Preferably, the secondary transistor and primary transistor are monolithically integrated, employing a high-reliability device structure including a cylindrical P-GaN region, dual gates, and a field plate. Furthermore, the chip can integrate an inverter composed of GaN devices to locally generate inverted control signals, simplifying external driving. This invention also provides a corresponding fabrication method. This invention effectively solves the ringing problem of gallium nitride power integrated circuits without sacrificing switching speed, significantly improving system reliability and integration.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a gallium integrated circuit chip and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) high electron mobility transistors (HEMTs) exhibit tremendous application potential in power electronics due to their superior material properties, such as wide bandgap, high critical breakdown electric field, and high electron saturation drift velocity. Compared to traditional silicon-based power devices, GaN HEMTs can achieve higher switching frequencies and power densities, thereby significantly reducing the size of passive components and improving the efficiency and power density of power systems.

[0003] However, the extremely high switching speed of GaN devices also brings severe technical challenges, one of the most prominent being voltage and current ringing during the switching process. This phenomenon mainly stems from the unavoidable parasitic inductance and capacitance in the power circuit, which together form a high-frequency LC resonant circuit. When the device switches at high speed within nanoseconds, the drastic changes in its voltage and current excite this resonant circuit, thereby inducing strong high-frequency damped oscillations, i.e., ringing, on the switching waveform. Strong voltage ringing can lead to a series of serious consequences: First, it may cause the device gate voltage to be coupled up and exceed the threshold voltage, triggering false turn-on, causing a shoot-through short circuit in the bridge circuit, and in severe cases, even burning out the device; second, repeated voltage overshoot and oscillations increase the switching losses of the device and reduce the overall system efficiency; third, increased voltage stress accelerates device degradation and affects long-term reliability.

[0004] To suppress ringing, existing technologies typically employ external passive snubber circuits (such as RC snubber networks or RCD clamping circuits) or add negative voltage turn-off or resistive damping to the gate drive path. However, these methods have significant drawbacks: external snubber circuits increase the number of additional components, size, and cost, and their losses negate the high-frequency and high-efficiency advantages of GaN devices; while increasing the gate resistance can slow down the switching speed and suppress ringing, it also significantly increases switching losses, negating the speed advantage of GaN; and complex multi-level gate drives increase system complexity and control difficulty.

[0005] Therefore, how to effectively suppress ringing and prevent false turn-on from within the chip while maintaining the high-speed switching advantage of GaN devices has become a key issue that urgently needs to be addressed in the current development of GaN power integrated circuit technology. Summary of the Invention

[0006] To address the voltage ringing and mis-conduction issues caused by parasitic parameters in existing gallium nitride power devices during high-speed switching applications, this invention provides a gallium integrated circuit chip and its fabrication method. By integrating an auxiliary circuit with active discharge function and optimizing the device structure within the chip, ringing is suppressed from within without sacrificing switching speed, thereby improving the reliability and integration of the circuit.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A gallium integrated circuit chip includes a basic circuit module consisting of a main transistor and a secondary transistor connected together. The main transistor is an enhancement-mode gallium nitride (GaN) device, and the secondary transistor is a field-effect semiconductor switch adapted to the function of the main transistor. The drain of the secondary transistor is connected to the gate of the main transistor and externally connected to a first input signal. The gate of the secondary transistor is externally connected to a second input signal. The first and second input signals are out of phase. The drain of the main transistor is configured as the drain terminal of the basic circuit module, and the source of the main transistor is connected to the source of the secondary transistor and configured as the source terminal of the basic circuit module.

[0009] The secondary transistor is configured to turn on in response to the second input signal when the gate potential of the primary transistor rises due to voltage ringing caused by external circuit coupling, so as to discharge the gate charge of the primary transistor and make its gate-source voltage lower than the threshold voltage, thereby suppressing the mis-turn-on of the primary transistor.

[0010] Specifically, the secondary device is an enhancement-mode gallium nitride device, and it is integrated with the primary device on the same epitaxial structure of the wafer.

[0011] Specifically, the main control device and / or the secondary control device include:

[0012] Substrate;

[0013] A nitride semiconductor stack formed on the substrate, the nitride semiconductor stack comprising at least a channel layer and a barrier layer;

[0014] At least two separate columnar P-GaN regions are formed in the gate region above the barrier layer;

[0015] A gate dielectric stack covering the cylindrical P-GaN region and the region between it;

[0016] A first gate electrode is formed on the gate dielectric stack and located between at least two of the cylindrical P-GaN regions.

[0017] Specifically, the controlling device further includes:

[0018] Etching grooves formed in the barrier layer near the drain side of the gate region;

[0019] A second gate electrode is formed within the etched groove, and the second gate electrode is electrically connected to the first gate electrode.

[0020] Specifically, the main transistor device further includes a first field plate structure located between its gate and source, and the secondary transistor device further includes a second field plate structure located between its gate and drain.

[0021] Specifically, the spacing between the cylindrical P-GaN regions is greater than the width of a single cylindrical P-GaN region.

[0022] Furthermore, the basic circuit module also includes a control unit, which is connected to the gate of the secondary transistor device and is used to provide the second input signal;

[0023] The control unit includes an inverter circuit, the output of which is connected to the gate of the secondary transistor device;

[0024] The inverter circuit is configured to receive a third input signal and output a logic signal that is inverted from the first input signal as the second input signal.

[0025] Specifically, the inverter circuit includes a depletion-type gallium nitride transistor and an enhancement-type gallium nitride transistor connected in series.

[0026] On the other hand, based on the above structure, the present invention also provides a method for fabricating the above-mentioned gallium integrated circuit chip, comprising the following steps:

[0027] S1. Provide a substrate, and sequentially epitaxially grow a buffer layer, a channel layer, an insertion layer, a barrier layer and a P-GaN layer on the substrate;

[0028] S2. Pattern the P-GaN layer to form at least two sets of separate cylindrical P-GaN regions, corresponding to the gate regions of the main transistor and the secondary transistor, respectively.

[0029] S3. Deposit a first dielectric layer on the barrier layer and the cylindrical P-GaN region;

[0030] S4. Deposit a second dielectric layer on the first dielectric layer;

[0031] S5. In the gate region corresponding to the main device, the first dielectric layer, the second dielectric layer and a portion of the barrier layer are selectively etched to form an etched groove;

[0032] S6. Deposit a third dielectric layer covering the second dielectric layer and the etched grooves;

[0033] S7. Form source contact holes and drain contact holes that penetrate the dielectric layer to the barrier layer, and form source electrodes and drain electrodes;

[0034] S8. A first gate electrode is formed in the region corresponding to the cylindrical P-GaN region, and a second gate electrode is formed in the etched groove, and the first gate electrode and the second gate electrode are electrically connected; and a first gate electrode is formed in the gate region of the sub-device;

[0035] S9. A passivation layer covering the electrode and a top interconnect metal are formed to achieve electrical connection between the main tube device and the secondary tube device, thus forming the basic circuit module.

[0036] Specifically, in step S8, a first field plate structure connected to the source of the main transistor and a second field plate structure connected to the drain of the secondary transistor are formed simultaneously.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] (1) By integrating a secondary transistor device connected in parallel with the gate of the main transistor and applying inverse control, the present invention can actively open the discharge path when the ringing voltage occurs, which can quickly and effectively pull down the gate voltage of the main transistor, fundamentally avoiding the risk of false turn-on caused by voltage overshoot, and significantly improving the safety and reliability of power circuits (especially half-bridge structures).

[0039] (2) The ringing suppression mechanism of the present invention is activated on demand and only operates during dangerous periods when mis-conduction may occur (main tube is turned off and adjacent tube is turned on). During normal switching transients and conduction phases, the secondary tube device does not work. Therefore, it does not introduce additional switching delay or loss as with increasing the gate resistance, thus maximizing the high speed and high efficiency advantages of GaN devices.

[0040] (3) By integrating the ringing suppression function with the power switching device on a single chip, the present invention eliminates the need for discrete components such as resistors, capacitors, and diodes required by the external buffer circuit, simplifies the layout, reduces the system size and cost, and the optimized control unit further simplifies the external drive requirements and reduces the overall system design complexity.

[0041] (4) The device structures such as the cylindrical P-GaN region, dual gate structure and field plate structure adopted in this invention not only ensure the realization of circuit functions, but also improve the breakdown voltage, threshold voltage stability and anti-interference ability of a single GaN HEMT from a physical level. Through the synergistic optimization of circuit design and device physics, the chip can achieve excellent dynamic performance while also having stronger static reliability.

[0042] (5) The preparation method of the present invention is based on the mature GaN HEMT manufacturing process. The added steps (such as forming columnar P-GaN regions, selective etching grooves, etc.) can all be achieved by standard photolithography, dry etching and atomic layer deposition technology, which has good process compatibility and repeatability and is suitable for mass production. Attached Figure Description

[0043] Figure 1 This is a circuit schematic diagram of the basic circuit module of Embodiment 1 of the present invention.

[0044] Figure 2 This is a schematic diagram of the cross-sectional structure of Embodiment 1 of the present invention.

[0045] Figure 3 This is a circuit schematic diagram of Embodiment 2 of the present invention.

[0046] Figures 4a to 4j This is a schematic diagram of the preparation process of the structure in Example 1 of the present invention.

[0047] Figure 5 This is a comparison diagram of the simulated switching process in Embodiment 2 of the present invention.

[0048] Figure 6 This is a comparison diagram of the simulated gate-source voltage in Embodiment 2 of the present invention.

[0049] Figure 7 This is a circuit schematic diagram of Embodiment 3 of the present invention. Detailed Implementation

[0050] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0051] Example 1

[0052] This embodiment provides a gallium integrated circuit chip and its fabrication method. For example... Figure 1 As shown, the gallium integrated circuit chip includes a basic circuit module composed of a main power switch and a secondary power switch connected together. In this embodiment, both the main power switch and the secondary power switch are enhancement-mode gallium nitride (GaN) devices. The main power switch is represented by N1 and serves as the core power switch, while the secondary power switch is represented by N2 and serves as the ringing suppression switch. The drain of the main power switch N1 is configured as the drain terminal of the basic circuit module, denoted as D. The source of the main power switch N1 is connected to the source of the secondary power switch N2 and configured as the source terminal of the basic circuit module, denoted as S. The drain of the secondary power switch N2 is connected to the gate of the main power switch N1 and together they lead out to an external first input signal Vin1. The gate of the secondary power switch N2 is independently connected to a second input signal Vin2. The first and second input signals are inversely related; for example, when Vin1 is high, Vin2 is low, and vice versa.

[0053] The secondary transistor is configured to turn on in response to the second input signal when the gate potential of the primary transistor rises due to voltage ringing caused by external circuit coupling. This discharges the gate charge of the primary transistor, lowering its gate-source voltage below a threshold voltage, thereby suppressing mis-turn-on of the primary transistor. Its operating principle is as follows: When the chip is in a shutdown state (Vin1 is low, primary transistor N1 is off), and an adjacent power module (such as the upper transistor in a half-bridge) is turned on at high speed, its voltage change is coupled to the gate of primary transistor N1 through circuit parasitic parameters, generating positive voltage ringing. If not suppressed, this voltage may exceed the threshold voltage Vth of primary transistor N1, causing mis-turn-on of primary transistor N1. In this embodiment, Vin2 is at a high level, which is the opposite of Vin1. The secondary device N2 is turned on. The turn on of N2 provides a low-impedance discharge path from the gate node of N1 to the source, which quickly discharges the charge coupled to it, thereby clamping the gate-source voltage Vgs of N1 at a low level (far below the threshold voltage Vth) and effectively preventing false turn-on.

[0054] To achieve high performance and high integration, the main transistor N1 and the secondary transistor N2 are manufactured on the same GaN epitaxial wafer using a monolithic integration process. The fabrication process is detailed below with reference to the accompanying drawings.

[0055] Firstly, as Figure 4a As shown, a substrate 1 is provided, located at the bottom of the entire device, and can be a sapphire substrate, a silicon-based substrate, or a silicon carbide-based substrate. A buffer layer 2, a channel layer 3, an insertion layer 4, a barrier layer 5, and a P-GaN layer 6 are sequentially epitaxially grown on the substrate 1 using metal-organic chemical vapor deposition (MOCVD) technology. Specifically, the buffer layer 2 is located on the surface of the substrate 1 and is made of AlN / AlGaN or a superlattice structure of AlGaN and GaN. Different materials for the buffer layer 2 are selected depending on the substrate 1, with AlGaN being the preferred material. The channel layer 3 is located on the surface of the buffer layer 2 and is made of GaN / AlGaN / InGaN, preferably AlGaN or InGaN. The insertion layer 4 is located on the surface of the channel layer 3 and is made of AlN with a thickness of 1-5 nm, preferably 2 nm. The barrier layer 5 is located directly above the insertion layer and is made of AlGaN / AlN, preferably AlGaN. The P-GaN layer 6 is located on the surface of the barrier layer and is a Mg-doped GaN layer with a thickness of 50-100 nm, preferably 80 nm.

[0056] Next, isolation is performed on the active regions of the device, such as... Figure 4bAs shown. Using inductively coupled plasma (ICP) dry etching technology, etching was performed in the middle right region of the epitaxial portion, extending into the channel layer 3. The etching thickness was the sum of the thicknesses of the channel layer, insertion layer, barrier layer, and P-GaN layer, forming two electrically isolated mesa regions. These regions were used to fabricate the active regions of the primary device N1 (left) and the secondary device N2 (right), respectively. From bottom to top, the left portion consists of substrate 1, buffer layer 2, first channel layer 31, first insertion layer 41, first barrier layer 51, and first P-GaN layer 61. The right portion, from bottom to top, consists of substrate 1, buffer layer 2, second channel layer 32, second insertion layer 42, second barrier layer 52, and second P-GaN layer 62.

[0057] Then, define the gate region. For example... Figure 4c As shown, the P-GaN layer 6 is patterned into two sets of separate cylindrical structures at the gate location in each mesa region using photolithography and ICP etching. For the main transistor N1, a first cylindrical P-GaN region 63 and a second cylindrical P-GaN region 64 are formed; for the secondary transistor N2, a third cylindrical P-GaN region 65 and a fourth cylindrical P-GaN region 66 are formed. During etching, the spacing between the two pillars is controlled to be greater than the width of a single pillar (e.g., twice the width) to optimize the subsequent gate electric field.

[0058] Subsequently, using an atomic layer deposition (ALD) device, an ultrathin first dielectric layer 7, made of SiN / AlN / Al2O3, with a thickness of 1-5 nm, was uniformly deposited on the surface of the P-GaN layer. This layer covered all areas and naturally filled the gaps between the columnar P-GaN regions, forming dielectric sublayers 71, 72, and 73. Figure 4c As shown, the second dielectric sublayer 72 is located between the first cylindrical P-GaN region 63 and the second cylindrical P-GaN region 64, the third dielectric sublayer 73 is located between the third cylindrical P-GaN region 65 and the fourth cylindrical P-GaN region 66, and the first dielectric sublayer 71 covers other positions on the surfaces of the first P-GaN layer 61 and the second P-GaN layer 62, and covers the upper surfaces of the first cylindrical P-GaN region 63, the second cylindrical P-GaN region 64, the third cylindrical P-GaN region 65 and the fourth cylindrical P-GaN region 66.

[0059] Next, a second dielectric layer 8, made of AlN / Al2O3 with a thickness of 10-20 nm, was deposited using ALD, forming three sublayers: sublayer 81 (filler layer 1), sublayer 82 (filler layer 2), and sublayer 83 (filler layer 3). Figure 4dAs shown, the first filling sublayer 81 covers the first dielectric sublayer 71, the second filling sublayer 82 covers the second dielectric sublayer 72, and the third filling sublayer 83 covers the third dielectric sublayer 73. The dielectric stack formed by the first dielectric layer 7 and the second dielectric layer 8 serves as a high-quality gate dielectric. For example, the stacked structures of the second filling sublayer 82 and the second dielectric sublayer 72, and the stacked structures of the third filling sublayer 83 and the third dielectric sublayer 73, can reduce the gate leakage current, increase the breakdown voltage, and increase the output current, while simultaneously meeting the requirements of N1 transistors being high-voltage devices and N2 transistors being low-voltage devices in gallium integrated circuits.

[0060] Next, selective etching is performed to form the dual-gate structure unique to the main control device N1. The surfaces of the first cylindrical P-GaN region 63, the second cylindrical P-GaN region 64, the third cylindrical P-GaN region 65, and the fourth cylindrical P-GaN region 66 are defined as etching areas. Using etching equipment (ICP or RIE equipment), the first filler sublayer 81 and the first dielectric sublayer 71 on the surfaces of the first cylindrical P-GaN region 63, the second cylindrical P-GaN region 64, the third cylindrical P-GaN region 65, and the fourth cylindrical P-GaN region 66 are etched away, exposing the tops of the cylindrical P-GaN regions for ohmic contact, such as... Figure 4e As shown. Then, the left side (near the drain direction) of the first cylindrical P-GaN region 63 is defined as the etching region. The first filling sublayer 81, the first dielectric sublayer 71 and part of the barrier layer 5 are etched using an etching device (ICP or RIE device). The thickness of the etched part of the barrier layer is 1-5nm, forming an etching groove 9 with a width of 1-2um.

[0061] After etching, a third dielectric layer 10 is deposited using atomic deposition (ALD) equipment. The material is AlN / Al2O3, and the thickness is 20-30 nm. This third dielectric layer 10 covers the etched grooves 9, the first dielectric sublayer 71, and the first filler sublayer 81 along the surface shape, and covers the exposed surfaces of the first columnar P-GaN region 63, the second columnar P-GaN region 64, the third columnar P-GaN region 65, and the fourth columnar P-GaN region 66, as shown below. Figure 4f As shown.

[0062] Next, source-drain ohmic contacts are fabricated. The source and drain locations are defined as etching regions, such as the two ends of the main transistor N1 and the secondary transistor N2. Using etching equipment (ICP or RIE), the third dielectric layer 10, the second dielectric layer 8, and the first dielectric layer 7 are etched until the barrier layer 5 is exposed, forming source and drain contact holes. Then, using metal evaporation equipment (PVD or magnetron sputtering), source and drain metal stacks are deposited with Ti / Al / Ni / TiN materials and thicknesses of 5 / 100 / 50 / 100 nm. These are then rapidly thermally annealed to form low-resistance ohmic contacts, resulting in the main transistor drain electrode 11, the main transistor source electrode 12, the secondary transistor source electrode 13, and the secondary transistor drain electrode 14. Figure 4g As shown.

[0063] Next, the gate electrode and field plate are formed. A gate metal stack of Ti / TiN material with a thickness of 50 / 100 nm is deposited using metal evaporation equipment (PVD or magnetron sputtering equipment). This forms the main gate second gate electrode 151, the main gate first gate electrode 152, and the secondary gate first gate electrode 153. A first field plate metal 161 is formed to the right of the second cylindrical P-GaN region 64, and a second field plate metal 163 is formed to the right of the fourth cylindrical P-GaN region 66. The main gate second gate electrode 151 is located between the first cylindrical P-GaN region 63 and the second cylindrical P-GaN region 64. The main gate first gate electrode 152 is located within and above the etched groove 9. The secondary gate first gate electrode 153 is located between the third cylindrical P-GaN region 65 and the fourth cylindrical P-GaN region 66. The second gate electrode 151 and the first gate electrode 152 form a dual-gate structure, which can improve the breakdown voltage, reduce threshold voltage drift, and improve the stability of the gallium integrated circuit chip; the first field plate metal 161 and the second field plate metal 163 further improve the voltage withstand capability of the gallium integrated circuit chip.

[0064] Then, passivation and interconnection are performed. A relatively thick fourth dielectric layer 17 of SiN material is deposited using plasma-enhanced chemical vapor deposition (PECVD) as a passivation layer, which covers the main transistor's second gate electrode 151, the main transistor's first gate electrode 152, the secondary transistor's first gate electrode 153, the main transistor's drain electrode 11, the main transistor's source electrode 12, the secondary transistor's source electrode 13, the secondary transistor's drain electrode 14, the first field plate metal 161, and the second field plate metal 163, as follows. Figure 4hAs shown. Then, the locations of the main second gate electrode 151, the main first gate electrode 152, the secondary first gate electrode 153, the first field plate metal 161, and the second field plate metal 163 are defined as etching areas. The fourth dielectric layer 17 is etched using etching equipment (ICP or RIE equipment) to form corresponding etch grooves, exposing the electrodes and field plate metals to be interconnected. Then, the first interconnect metal layer, made of Al / Cu, is deposited using metal evaporation equipment (PVD or magnetron sputtering equipment), forming the first interconnect metal layer 154, the second interconnect metal layer 155, the third interconnect metal layer 162, and the fourth interconnect metal layer 164. The first interconnect metal layer 154 connects the main second gate electrode 151 and the main first gate electrode 152; the second interconnect metal layer 155 connects the secondary first gate electrode 153; the third interconnect metal layer 162 connects the first field plate metal 161; and the fourth interconnect metal layer 164 connects the second field plate metal 163. The main gate electrode 151, the main gate electrode 152, the secondary gate electrode 153, the first interconnect metal layer 154 and the second interconnect metal layer 155 are collectively referred to as gate structure 15, and the first field plate metal 161, the second field plate metal 163, the third interconnect metal layer 162 and the fourth interconnect metal layer 164 are collectively referred to as field plate structure 16.

[0065] Next, a fifth dielectric layer 25 is deposited using plasma-enhanced chemical vapor deposition (PECVD) as the interlayer dielectric. The material is SiO2 or SiN, which covers the first interconnect metal layer, such as... Figure 4iAs shown. The area corresponding to the first interconnect metal layer is defined as the etching area. The fifth dielectric layer 25 is etched using etching equipment (ICP or RIE equipment) to form corresponding etched grooves. Then, a second interconnect metal layer with a thickened top layer is deposited using metal evaporation equipment (PVD or magnetron sputtering equipment). The material is Al / Cu, forming the fifth interconnect metal layer 19, the sixth interconnect metal layer 22, the seventh interconnect metal layer 231, and the eighth interconnect metal layer 232. The fifth interconnect metal layer 19 is connected to the first interconnect metal layer 154, the sixth interconnect metal layer 22 is connected to the second interconnect metal layer 155, the seventh interconnect metal layer 231 is connected to the third interconnect metal layer 162, and the eighth interconnect metal layer 232 is connected to the fourth interconnect metal layer 164. The regions corresponding to the main drain electrode 11, main source electrode 12, secondary source electrode 13, and secondary drain electrode 14 are defined as etching regions. The fifth dielectric layer 25 and the fourth dielectric layer 17 are etched using etching equipment (ICP or RIE equipment) to form corresponding etching grooves. A third interconnect metal layer with Al / Cu material is deposited using metal evaporation equipment (PVD or magnetron sputtering equipment) to form the ninth interconnect metal layer 18, tenth interconnect metal layer 20, eleventh interconnect metal layer 21, and twelfth interconnect metal layer 24. The ninth interconnect metal layer 18 is connected to the main drain electrode 11, the tenth interconnect metal layer 20 is connected to the main source electrode 12, the eleventh interconnect metal layer 21 is connected to the secondary source electrode 13, and the twelfth interconnect metal layer 24 is connected to the secondary drain electrode 14.

[0066] After the twelfth interconnect metal layer 24 is connected to the fifth interconnect metal layer 19, it is connected to the input signal Vin1; the tenth interconnect metal layer 20, the eleventh interconnect metal layer 21, the seventh interconnect metal layer 231, and the eighth interconnect metal layer 232 are connected to the S terminal; the sixth interconnect metal layer 22 is connected to the input signal Vin2; the ninth interconnect metal layer 18 is connected to the D terminal; thus forming the basic circuit module device of this gallium integrated circuit chip, such as... Figure 4j As shown.

[0067] Using the above process, a basic circuit module chip integrating ringing suppression function was fabricated. Among them, the breakdown voltage of N1 transistor is significantly improved due to its dual-gate and field plate structure; while the structure of N2 transistor is relatively simple, only needing to meet the low withstand voltage requirement. The two are connected in a compact manner with low parasitic inductance through internal metal lines of the chip.

[0068] Example 2

[0069] This embodiment provides an application example of the basic circuit module in Embodiment 1 in a typical half-bridge topology, such as... Figure 3As shown, a half-bridge arm consists of two basic circuit modules, upper and lower. Transistors N3 and N4, and N5 and N6 respectively constitute the basic circuit modules in Embodiment 1. Transistors N3 and N5 are the main control devices, and N4 and N6 are the secondary control devices. After the gate of transistor N5 is connected to the drain of transistor N6, an external input signal Vin5 is connected. The drain of transistor N5 is connected to VCC. The source of transistor N5 is connected to the source and gate of transistor N6, and then connected to the drive electrode U / V / W terminal. When transistor N6 is connected to transistor N5, it can be disabled by connecting its gate and source, thus directly turning it off. The drain of transistor N3 is connected to the drive electrode U / V / W terminal. After the gate of transistor N3 is connected to the drain of transistor N4, an external input signal Vin3 is connected. The gate of transistor N4 is connected to the external input signal Vin4. The source of transistor N4 is connected to the source of transistor N3 and then connected to GND.

[0070] Input signals Vin3, Vin4, and Vin5 are configured according to the control logic. Vin3 and Vin5 are typically inverted signals to achieve complementary outputs from the half-bridge circuit. Input signal Vin4 is used to control the N4 transistor and is preferably set to be inverted compared to Vin3.

[0071] When input signal Vin5 is high and input signal Vin3 is low, the lower transistor N3 is off and the upper transistor N5 is on. Due to ringing, the gate voltage of N3 will be pulled high, posing a risk of N3 being turned on unnecessarily. Figure 5 As shown. At this time, a high input signal Vin4 will turn on transistor N4, thereby pulling down the gate voltage of transistor N3, preventing N3 from accidentally turning on and burning out the entire half-bridge circuit. That is, transistors N3 and N4 are close together, with small parasitic inductance between them, effectively driving the gate level of N3 to be equal to its source level. When input signals Vin5 and Vin4 are high, the gate voltage of N3 is maintained below the turn-on threshold voltage, avoiding a false turn-on situation caused by transistor N5 turning on and pulling up the gate voltage of N3. Figure 6 As stated above.

[0072] The advantage of this structure is that it avoids the problem of the lower transistor being pulled up when the upper transistor is connected to a high level, which could lead to the lower transistor being turned on accidentally and causing the half-bridge circuit to burn out. In other words, it reduces the ringing amplitude between the upper and lower transistors in the half-bridge circuit and improves the stability of the half-bridge circuit.

[0073] Example 3

[0074] This embodiment provides an optimized structure based on the basic circuit module of Embodiment 1, such as... Figure 7 As shown, the circuit of the gallium integrated circuit chip includes three enhancement-mode gallium nitride devices N1, N7 and N9, and one depletion-mode gallium nitride device N8, wherein N1 is the main device, N7 is the first auxiliary device, N8 is the second auxiliary device, and N9 is the third auxiliary device.

[0075] The circuit composed of transistors N1 and N7 corresponds to that in Example 1. The drain of transistor N1 is connected to the D terminal, and the gate of transistor N1 is connected to the drain of transistor N7, which is then connected to the input signal Vin1. The source of transistor N1 is connected to the source of transistor N7, which is then connected to the S terminal. Transistors N8 and N9 form an inverter structure. The gate of transistor N8 is externally connected to the input signal Vin8, and the drain of transistor N8 is externally connected to VDD. The source of transistor N8 is connected to the drain of transistor N9, which serves as the input signal to the gate of transistor N7. The gate of transistor N9 is externally connected to the input signal Vin9, and the source of transistor N9 is connected to the sources of transistors N1 and N7, which is then connected to the S terminal. The input signals Vin1, Vin8, and Vin9 can be the same signal or different signals, and can be adjusted according to the actual situation.

[0076] Its working process is analyzed as follows:

[0077] When the input signals Vin1, Vin8, and Vin9 are high, the gate of transistor N1 is high and it is turned on. When the inverter composed of transistors N8 and N9 is high, its output terminal (i.e., the gate of transistor N7) is pulled low, so that transistor N7 remains off. At this time, the circuit is in normal conduction operation.

[0078] When input signals Vin1, Vin8, and Vin9 are low, transistor N1 is off. With the inverter input low, transistor N9 is also off. The depletion-mode transistor N8 pulls the inverter output high, thus turning on transistor N7. At this time, transistor N7 provides a low-impedance discharge path from the gate of transistor N1 to its source (S), ensuring that Vgs is below the threshold voltage when N1 is off. This clamps the gate-source voltage of N1 at a low level, preventing N1 from accidentally turning on due to ringing and causing the entire circuit to burn out.

[0079] Compared to Example 1, the advantage of this example is that the external control is simpler. Example 1 requires an inverting signal as input, and the control structure is relatively complex, which is not conducive to the integration of the overall gallium integrated circuit chip. In this example, due to the addition of an inverter structure, the input signals Vin1, Vin8 and Vin9 can be controlled by the same signal, which can realize the ringing suppression function. The control is simple, the driving design difficulty is reduced, and the influence of ringing on connected devices in the gallium integrated circuit chip can be quickly eliminated, thereby improving the performance of the gallium integrated circuit chip.

[0080] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any changes made based on the design principles of the present invention, or any non-creative modifications made thereon, shall fall within the scope of protection of the present invention.

Claims

1. A gallium integrated circuit chip, characterized by, The system includes a basic circuit module consisting of a main transistor and a secondary transistor connected together. The main transistor is an enhancement-mode gallium nitride (GaN) device, and the secondary transistor is a field-effect semiconductor switching device whose function is adapted to the main transistor. The drain of the secondary transistor is connected to the gate of the main transistor and externally connected to a first input signal. The gate of the secondary transistor is externally connected to a second input signal. The first and second input signals are out of phase. The drain of the main transistor is configured as the drain terminal of the basic circuit module, and the source of the main transistor is connected to the source of the secondary transistor and configured as the source terminal of the basic circuit module. The secondary transistor is configured to turn on in response to the second input signal when the gate potential of the primary transistor rises due to voltage ringing caused by external circuit coupling, so as to discharge the gate charge of the primary transistor and make its gate-source voltage lower than the threshold voltage, thereby suppressing the mis-turn-on of the primary transistor.

2. The gallium integrated circuit chip of claim 1, wherein, The secondary device is an enhancement-mode gallium nitride device and is integrated with the primary device on the same epitaxial structure of the wafer.

3. The gallium integrated circuit chip of claim 2, wherein, The main tube device and / or the secondary tube device include: Substrate; A nitride semiconductor stack formed on the substrate, the nitride semiconductor stack comprising at least a channel layer and a barrier layer; Two separate columnar P-GaN regions are formed in the gate region above the barrier layer; A gate dielectric stack covering the cylindrical P-GaN region and the region between it; A first gate electrode is formed on the gate dielectric stack and located between the two cylindrical P-GaN regions.

4. The gallium integrated circuit chip of claim 3, wherein, The main control device also includes: Etching grooves formed in the barrier layer near the drain side of the gate region; A second gate electrode is formed within the etched groove, and the second gate electrode is electrically connected to the first gate electrode.

5. The gallium integrated circuit chip of claim 4, wherein, The primary transistor device further includes a first field plate structure located between its gate and source, and the secondary transistor device further includes a second field plate structure located between its gate and drain.

6. The gallium integrated circuit chip according to any one of claims 3 to 5, wherein The spacing between the cylindrical P-GaN regions is greater than the width of a single cylindrical P-GaN region.

7. The gallium integrated circuit chip of claim 1, wherein, The basic circuit module also includes a control unit, which is connected to the gate of the secondary transistor device and is used to provide the second input signal; The control unit includes an inverter circuit, the output of which is connected to the gate of the secondary transistor device; The inverter circuit is configured to receive a third input signal and output a logic signal that is inverted from the first input signal as the second input signal.

8. The gallium integrated circuit chip of claim 7, wherein, The inverter circuit includes a depletion-type gallium nitride transistor and an enhancement-type gallium nitride transistor connected in series.

9. The method of claim 2-5, wherein the gallium integrated circuit chip is prepared by the steps of: Includes the following steps: ​ S1. Provide a substrate, and sequentially epitaxially grow a buffer layer, a channel layer, an insertion layer, a barrier layer and a P-GaN layer on the substrate; S2. Pattern the P-GaN layer to form at least two sets of separate cylindrical P-GaN regions, corresponding to the gate regions of the main transistor and the secondary transistor, respectively. S3. Deposit a first dielectric layer on the barrier layer and the cylindrical P-GaN region; S4. Deposit a second dielectric layer on the first dielectric layer; S5. In the gate region corresponding to the main device, the first dielectric layer, the second dielectric layer and a portion of the barrier layer are selectively etched to form an etched groove; S6. Deposit a third dielectric layer covering the second dielectric layer and the etched grooves; S7. Form source contact holes and drain contact holes that penetrate the dielectric layer to the barrier layer, and form source electrodes and drain electrodes; S8. A first gate electrode is formed in the region corresponding to the cylindrical P-GaN region, and a second gate electrode is formed in the etched groove, and the first gate electrode and the second gate electrode are electrically connected; and a first gate electrode is formed in the gate region of the sub-device; S9. A passivation layer covering the electrode and a top interconnect metal are formed to achieve electrical connection between the main tube device and the secondary tube device, thus forming the basic circuit module.

10. The method of claim 9, wherein the gallium integrated circuit chip is prepared by a method comprising: In step S8, a first field plate structure connected to the source of the main transistor and a second field plate structure connected to the drain of the secondary transistor are formed simultaneously. ​

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