Semiconductor packaging structure and its fabrication method

Abstract

This application provides a semiconductor packaging structure and its fabrication method. The semiconductor packaging structure includes: a first rigid insulating substrate, including a first conductive structure extending through the substrate along its thickness direction; an embedded chip disposed on one side of the first rigid insulating substrate, the embedded chip being electrically connected to the first conductive structure; and a second rigid insulating substrate disposed on the side of the embedded chip away from the first rigid insulating substrate, the second rigid insulating substrate including a second conductive structure extending through the substrate along its thickness direction, the embedded chip being electrically connected to the second conductive structure. This application uses rigid substrates located on both sides of the embedded chip to balance thermal stress, reducing warpage deformation of large-size interposers during thermal processing, and solving the problem of excessive warpage caused by insufficient rigidity of organic substrates and the problem of residual warpage caused by material mismatch between single-layer glass substrates and organic redistribution layers.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and its fabrication method. Background Technology

[0002] With the advancement of technologies such as artificial intelligence and high-performance computing, the requirements for chip performance and integration are constantly increasing. As chip manufacturing processes gradually approach their physical limits, their development speed is slowing down, making packaging structures and their fabrication methods crucial for improving chip integration and performance. Currently, a common industry practice is to place an intermediary layer between the chip and the substrate to increase integration density. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a semiconductor packaging structure and its fabrication method to reduce the risk of substrate warping.

[0004] In view of the above objectives, in a first aspect, this application provides a semiconductor packaging structure, comprising: A first rigid insulating substrate includes a first conductive structure disposed through the thickness direction; An embedded chip is disposed on one side of the first rigid insulating substrate, and the embedded chip is electrically connected to the first conductive structure; A second rigid insulating substrate is disposed on the side of the embedded chip away from the first rigid insulating substrate. The second rigid insulating substrate includes a second conductive structure that extends through the chip along its thickness direction. The embedded chip is electrically connected to the second conductive structure.

[0005] Optionally, at least one of the first rigid insulating substrate and the second rigid insulating substrate may be made of glass.

[0006] Optionally, the second rigid insulating substrate includes a layer of glass fiber cloth.

[0007] Optionally, it also includes: A functional chip is disposed on the side of the second rigid insulating substrate away from the built-in chip, and the functional chip is electrically connected to the built-in chip through the second conductive structure; The built-in chip includes a silicon bridge chip, and the number of functional chips is at least two, with the at least two functional chips being electrically connected through the silicon bridge chip.

[0008] Optionally, it also includes: An insulating filler layer is disposed between the first rigid insulating substrate and the second rigid insulating substrate, and at least covers the sidewalls of the built-in chip; A third conductive structure is disposed within the insulating filler layer, and the first conductive structure is electrically connected to the second conductive structure through the third conductive structure.

[0009] Optionally, it also includes: A first wiring layer is disposed on the side of the first rigid insulating substrate close to the embedded chip. The first wiring layer includes alternating stacked first dielectric layers and first circuit layers. One side of the first circuit layer is electrically connected to the first conductive structure, and the other side is electrically connected to the embedded chip and / or the third conductive structure. The second wiring layer is disposed on the side of the built-in chip near the second rigid insulating substrate. The second wiring layer includes alternately stacked second dielectric layers and second circuit layers. One side of the second circuit layer is electrically connected to the second conductive structure, and the other side is electrically connected to the built-in chip and / or the third conductive structure.

[0010] Optionally, it also includes: A first conductor is disposed between the second wiring layer and the functional chip to electrically connect the second wiring layer and the functional chip; The second conductor is disposed on the side of the first rigid insulating substrate away from the functional chip; An insulating encapsulation layer is disposed on the side of the second wiring layer away from the built-in chip and surrounds the functional chip.

[0011] Optionally, it also includes: A circuit board is disposed on the side of the first rigid insulating substrate away from the built-in chip, and the built-in chip is electrically connected to the circuit board through the first conductive structure.

[0012] Secondly, this application also provides a method for fabricating a semiconductor packaging structure, comprising: A first rigid insulating substrate is provided, the first rigid insulating substrate including a first conductive structure disposed through the thickness direction; An embedded chip is disposed on one side of the first rigid insulating substrate; A second rigid insulating substrate is disposed on the side of the built-in chip away from the first rigid insulating substrate. The second rigid insulating substrate includes a second conductive structure disposed through the chip in the thickness direction.

[0013] Optionally, the step of setting a built-in chip on one side of the first rigid insulating substrate includes: A first redistribution layer is formed on one side of the first rigid insulating substrate, and the first redistribution layer is electrically connected to the first conductive structure. The built-in chip is bonded to the first rewiring layer, so that the built-in chip is electrically connected to the first rewiring layer; Multiple spaced third conductive structures are formed around the built-in chip; An insulating filler material is filled around the built-in chip and the third conductive structure to form an insulating filler layer; Before the second rigid insulating substrate is disposed on the side of the built-in chip away from the first rigid insulating substrate, the method further includes: A second redistribution layer is formed on the side of the built-in chip and the insulating fill layer away from the first rigid insulating substrate, and the second redistribution layer is electrically connected to the built-in chip and / or to the third conductive structure; The second rigid insulating substrate is disposed on the side of the second redistribution layer away from the built-in chip, and the second conductive structure is electrically connected to the second redistribution layer.

[0014] The semiconductor packaging structure provided in this application forms a rigid sandwich structure by placing the embedded chip between a first rigid insulating substrate and a second rigid insulating substrate. On the one hand, the rigid substrates on both sides balance the thermal stress, reducing the warpage deformation of the large-size interposer during the thermal process. This solves the problem of excessive warpage caused by insufficient rigidity of the organic substrate and the problem of residual warpage caused by the mismatch between the single-layer glass substrate and the organic redistribution layer material. On the other hand, the embedded chip forms a vertical heat conduction path through the conductive structure, alleviating the heat dissipation difficulties caused by the low thermal conductivity of the glass substrate. At the same time, the chip is embedded between the substrates and does not occupy surface space, improving the integration density and providing a basis for multi-chip stacking and functional chip integration. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a cross-sectional schematic diagram of a partial structure of a semiconductor packaging structure provided in an embodiment of this application; Figure 2 This is a partial cross-sectional schematic diagram of another semiconductor packaging structure provided in this application embodiment; Figure 3 This is a cross-sectional schematic diagram of a semiconductor packaging structure provided in an embodiment of this application; Figure 4 This is a cross-sectional schematic diagram of another semiconductor packaging structure provided in the embodiments of this application; Figure 5 This is a schematic flowchart of a method for fabricating a semiconductor packaging structure according to an embodiment of this application; Figure 6This is a schematic diagram illustrating the structural changes of the semiconductor packaging structure provided in the embodiments of this application during the fabrication process; Figure 7 This is a schematic diagram of the structural changes of the semiconductor packaging structure provided in the embodiments of this application during the fabrication process.

[0017] Marker explanation: 100. Semiconductor packaging structure; 10. First rigid insulating substrate; 11. First conductive structure; 20. Insulating filler layer; 21. Built-in chip; 22. Third conductive structure; 30. Second rigid insulating substrate; 31. Second conductive structure; 40. Functional chips; 51. First routing layer; 52. Second routing layer; 61. First conductor; 62. Second conductor; 70. Insulating encapsulation layer; 80. Circuit board. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0019] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0020] With the development of technologies such as artificial intelligence and high-performance computing, the performance requirements and integration levels of chips are constantly increasing. As chip manufacturing processes gradually approach their physical limits, the path of improving performance solely through process miniaturization is becoming increasingly limited. Packaging technology has become a key breakthrough for improving chip integration and performance. Currently, the industry commonly uses an intermediary layer between the chip and the substrate to achieve high-density interconnection between chips and electrical connection with the substrate.

[0021] In 2.5D / 3D integrated packaging, the interposer layer needs to support multiple side-by-side or stacked chips, and its planar dimensions have expanded from the traditional 20-30mm to 50mm or even over 100mm. As the computing power requirements of chips increase, the number of integrated chips continues to increase, the area of ​​the interposer layer continues to grow, and the warpage problem becomes increasingly prominent, becoming a key factor affecting packaging reliability and yield.

[0022] In related technologies, semiconductor packaging structures or interlayers mainly use organic substrate materials, such as bismaleimide triazine resin and Ajinomoto deposition film. Organic materials have low mechanical strength and insufficient rigidity, and a high coefficient of thermal expansion, which differs significantly from that of silicon chips. During thermal processing such as reflow soldering and curing, they are prone to warping deformation due to mismatch in coefficients of thermal expansion or curing shrinkage. When the substrate size exceeds 50mm, the warping of organic substrates typically exceeds 80-100μm, exceeding the tolerance limit of ≤50μm for warping in chip mounting processes, leading to decreased chip mounting accuracy, solder layer cracking, or connection failure.

[0023] To address warpage issues, related technologies have explored the use of silicon or glass substrates. Silicon substrates offer a thermal expansion coefficient matching the chip's performance and high rigidity. However, silicon, being a semiconductor material, has low resistivity, requiring an additional insulating layer to prevent signal crosstalk, increasing process complexity. Furthermore, silicon wafers are expensive and size-limited, making it difficult to meet the low-cost requirements of large-area interposers. Glass substrates offer advantages such as a low thermal expansion coefficient, high rigidity, high resistivity, and the ability to be fabricated in large sizes, theoretically making them suitable for large-area interposers. However, glass materials themselves have inherent drawbacks: low thermal conductivity, making it difficult for high-power chips to dissipate heat; high brittleness, easily developing microcracks under thermal stress; and softening at high temperatures, making them sensitive to process thermal budgets. These drawbacks are more pronounced in large-area, multi-chip integration scenarios, such as the heat dissipation requirements of high-power AI chips and the signal transmission requirements of high-frequency 6G applications.

[0024] Furthermore, chip integration in related technologies is mostly surface-mount, occupying the surface space of the interposer layer, limiting the improvement of integration density, and the heat dissipation path is singular. Although the single-layer glass substrate has sufficient rigidity, the difference in thermal expansion coefficients between it and the organic redistribution layer, as well as the mismatch in the material properties of the upper and lower structures, still results in warping problems.

[0025] In view of this, how to take advantage of the advantages of glass substrates while overcoming their inherent defects, improve the warping problem in large sizes through structural design, and increase the integration density to meet the high integration requirements of multi-chips are urgent problems to be solved in this field.

[0026] This application provides a semiconductor packaging structure 100, such as... Figure 1 , Figure 2As shown, the semiconductor package structure 100 includes a first rigid insulating substrate 10, an embedded chip 21, and a second rigid insulating substrate 30. The first rigid insulating substrate 10 includes a first conductive structure 11 that extends through the substrate along its thickness direction. The embedded chip 21 is disposed on one side of the first rigid insulating substrate 10 and is electrically connected to the first conductive structure 11. The second rigid insulating substrate 30 is disposed on the side of the embedded chip 21 away from the first rigid insulating substrate 10. The second rigid insulating substrate 30 includes a second conductive structure 31 that extends through the substrate along its thickness direction, and the embedded chip 21 is electrically connected to the second conductive structure 31.

[0027] Specifically, the first rigid insulating substrate 10 has opposing first and second surfaces, for example, the first surface is the upper surface and the second surface is the lower surface. The first rigid insulating substrate 10 includes a first conductive structure 11 disposed through the first rigid insulating substrate 10 along its thickness direction. The first conductive structure 11 is used to realize the electrical connection between the upper and lower surfaces of the first rigid insulating substrate 10.

[0028] The number of built-in chips 21 can be one or more. When there are multiple built-in chips 21, they can be arranged in an array on one side of the first rigid insulating substrate 10. The second rigid insulating substrate 30 at least covers the distribution area of ​​all built-in chips 21, and also provides wiring space.

[0029] The built-in chip 21 can be a single chip or a combination of multiple chips, such as a bridge chip, a logic chip, or a memory chip. The lower surface of the built-in chip 21 has multiple chip pads, which are electrically connected to the first conductive structure 11 through a subsequently formed wiring structure.

[0030] The second rigid insulating substrate 30 is disposed on the side of the built-in chip 21 away from the first rigid insulating substrate 10, i.e., covering the built-in chip 21. The second rigid insulating substrate 30 also includes a second conductive structure 31 that extends through the substrate along its thickness direction. The second conductive structure 31 is filled with a conductive material to achieve electrical connection between the upper and lower surfaces of the second rigid insulating substrate 30.

[0031] In some embodiments, the material of the first rigid insulating substrate 10 and / or the second rigid insulating substrate 30 includes glass.

[0032] The rigidity of the second rigid insulating substrate 30 is the same as that of the first rigid insulating substrate 10. For example, when the first rigid insulating substrate 10 is a glass substrate, the second rigid insulating substrate 30 can be a glass substrate of the same material. In this case, the thickness of the second rigid insulating substrate 30 and the first rigid insulating substrate 10 can be set to be the same, for example, 100μm, 200μm or 400μm, thereby forming a symmetrical rigid structure on both sides of the built-in chip 21, so that the thermal stress cancels each other out and reduces the warpage.

[0033] In some embodiments, the second rigid insulating substrate 30 is made of glass fiber cloth. To match the overall stiffness of the second rigid insulating substrate 30 with that of the first rigid insulating substrate 10, which uses a glass substrate, the thickness of the second rigid insulating substrate 30 can be appropriately increased. For example, when the thickness of the first rigid insulating substrate 10 is 200 μm, the thickness of the second rigid insulating substrate 30 can be designed to be 400-600 μm, so that the bending stiffness of the two tends to be consistent, thereby maintaining a symmetrical stress distribution when the temperature changes, effectively suppressing warping. The Young's modulus of the glass substrate is 70-80 GPa, and the Young's modulus of the glass fiber cloth layer is 20-30 GPa; the stiffness is proportional to the cube of the Young's modulus and the thickness. Furthermore, the stiffness of the second rigid insulating substrate 30 can also be improved by adjusting the number of glass fiber cloth layers, the fiber content, or by selecting a high-modulus resin, to achieve stiffness matching with the glass substrate.

[0034] In some embodiments, the projected area of ​​the second rigid insulating substrate 30 along the thickness direction is greater than or equal to the projected area of ​​the first rigid insulating substrate 10 along the thickness direction.

[0035] In one specific example, the projected area of ​​the second rigid insulating substrate 30 along the thickness direction is larger than that of the first rigid insulating substrate 10 along the thickness direction. For example, the second rigid insulating substrate 30 extends outward by 0.5-2 mm on each side relative to the first rigid insulating substrate 10 to provide sufficient layout space for the subsequently formed second redistribution layer 52, first conductor 61 and functional chip 40, while avoiding edge stress concentration.

[0036] In another specific example, the projected area of ​​the second rigid insulating substrate 30 along the thickness direction is equal to the projected area of ​​the first rigid insulating substrate 10 along the thickness direction. Precisely aligning the second rigid insulating substrate 30 with the first rigid insulating substrate 10 during manufacturing to achieve edge flushing simplifies the process.

[0037] The thickness relationship between the second rigid insulating substrate 30 and the first rigid insulating substrate 10 can be selected based on material properties and application requirements. In one embodiment, the first rigid insulating substrate 10 and the second rigid insulating substrate 30 have the same thickness, both 200 μm, suitable for high-performance computing scenarios with extremely high warpage requirements. In another embodiment, the first rigid insulating substrate 10 has a thickness of 150 μm, and the second rigid insulating substrate 30 has a thickness of 300 μm, suitable for cost-sensitive applications where the second rigid insulating substrate 30 uses a glass fiber cloth layer. The thickness difference can be verified through simulation or experiments to ensure that the warpage within the expected temperature range meets process requirements, such as ≤70 μm.

[0038] The embedded chip 21 is located between the first rigid insulating substrate 10 and the second rigid insulating substrate 30, with its upper and lower sides forming electrical pathways with the first conductive structure 11 and the second conductive structure 31, respectively. This structure allows the embedded chip 21 to connect downwards to external circuits and upwards to subsequently installed functional chips, enabling bidirectional signal transmission. The first rigid insulating substrate 10 and the second rigid insulating substrate 30 are made of the same or similar materials, forming a symmetrical rigid sandwich structure.

[0039] In the semiconductor packaging structure 100 provided in this application embodiment, the built-in chip 21 is encapsulated between two rigid insulating substrates. On the one hand, because the thermal expansion coefficients of the upper and lower substrate materials are matched, the thermal stresses generated during temperature changes are symmetrical, preventing the structure from bending to one side and thus reducing warping deformation. On the other hand, the rigid insulating substrate itself provides stable mechanical support for the built-in chip 21, and compared with traditional organic interposers, it has better dimensional stability and can maintain good flatness even when the area increases.

[0040] As one specific implementation method, such as Figure 1 As shown, the first rigid insulating substrate 10 is a first glass substrate and has a first glass through-hole that extends through the thickness direction. The first conductive structure 11 is a conductive structure formed by filling the first glass through-hole with metal (e.g., copper). The first glass through-hole can be formed by laser drilling or photosensitive glass etching, and then filled with metal by electroplating and planarized.

[0041] The second rigid insulating substrate 30 may be a second glass substrate and has a second glass through hole that extends through the thickness direction. The second conductive structure 31 is a conductive structure formed by filling the second glass through hole with metal.

[0042] As another specific implementation method, such as Figure 2 As shown, the second rigid insulating substrate 30 includes a glass fiber cloth layer, such as an epoxy glass fiber composite material. The glass fiber cloth layer can be formed by a lamination process. When glass fiber cloth is used as the second rigid insulating substrate 30, its coefficient of thermal expansion may differ from that of the first rigid insulating substrate 10 (e.g., glass), but warpage can still be effectively controlled due to the design of the sandwich structure and the buffering effect of the subsequent insulating filler layer.

[0043] The glass substrate has different material properties compared to traditional organic substrates. For example, glass has a low thermal conductivity of approximately 1.1 W / (m·K), is a brittle material, exhibits high-temperature softening characteristics, and has extremely high resistivity. This application addresses these issues through a symmetrical rigid sandwich structure. For instance, the embedded chip 21 is in direct contact with the upper and lower redistribution layers via a subsequently formed conductive structure. This conductive structure forms a vertical heat conduction path, which helps to conduct heat from the chip to the outside, mitigating the heat concentration problem that may be caused by the low thermal conductivity of the glass. Furthermore, the insulating filler layer between the upper and lower glass substrates uses a low-modulus organic material to encapsulate the embedded chip 21, forming a stress buffer for the glass substrate and helping to absorb CTE mismatch stress, preventing glass cracking.

[0044] The semiconductor packaging structure of this application can be applied to various scenarios. For example, in the fields of AI chips and high-performance computing, the built-in chip 21 can be directly interconnected with functional chips through a silicon bridge chip, which helps to shorten the signal transmission path. In the field of 6G communication, the glass substrate structure can be applied to the integration of high-frequency front-end chips with low-loss interconnects. In the field of radio frequency front-end, the low dielectric constant and low loss factor of the glass substrate are beneficial for integrating passive devices to achieve radio frequency characteristics. In the field of optoelectronic co-packaging, the optical transparency of glass makes it possible to construct optical waveguide channels inside the substrate. In the field of microelectromechanical systems (MEMS), the electrical insulation and thermal stability of the glass substrate can provide mechanical support and electrical isolation for MEMS devices. For example, in a miniature mass spectrometer, the high resistivity of the glass substrate can reduce the parasitic capacitance of the ion detection unit and improve the detection sensitivity; in an inertial sensor, the thermal stability of the glass substrate can ensure the zero-bias stability of the sensor when operating over a wide temperature range.

[0045] Besides glass and fiberglass cloth, the first rigid insulating substrate 10 and the second rigid insulating substrate 30 can also be made of other rigid insulating materials, such as ceramics, silicon, and metal-based composite materials (such as aluminum silicon carbide). For example, the first rigid insulating substrate 10 can be made of aluminum nitride ceramic with a thickness of 150 μm, while the second rigid insulating substrate 30 can be made of fiberglass cloth with a thickness that can be increased to more than 600 μm to match the rigidity of the first rigid insulating substrate 10, thus achieving a symmetrical effect.

[0046] In some embodiments, the semiconductor package structure 100 further includes an insulating filler layer 20 and a third conductive structure 22. The insulating filler layer 20 is disposed between the first rigid insulating substrate 10 and the second rigid insulating substrate 30, and at least covers the sidewalls of the embedded chip 21. The third conductive structure 22 is disposed within the insulating filler layer 20, and the first conductive structure 11 is electrically connected to the second conductive structure 31 through the third conductive structure 22.

[0047] Specifically, the insulating filler layer 20 can be made of insulating materials such as epoxy resin and polyimide, and formed through a potting process. After curing, the upper surface of the insulating filler layer 20 can be planarized to provide a good interface for subsequent bonding.

[0048] The third conductive structure 22 can be a conductive structure such as a copper pillar, formed by electroplating. In this embodiment, the process sequence of fabricating the third conductive structure 22 first and then potting is adopted: after the built-in chip 21 is placed on the first rigid insulating substrate 10, multiple spaced third conductive structures 22 are first fabricated around it, and then insulating filler material is filled to form an insulating filler layer 20. This process sequence is beneficial for the precise positioning and height control of the third conductive structure 22, and avoids damage to it in subsequent processes.

[0049] The first conductive structure 11 is electrically connected to the second conductive structure 31 through the third conductive structure 22, forming a complete signal path.

[0050] In some embodiments, such as Figure 3 As shown, the semiconductor package structure 100 also includes a functional chip 40, which is disposed on the side of the second rigid insulating substrate 30 away from the built-in chip 21, i.e., on the upper side of the second rigid insulating substrate 30. The functional chip 40 is electrically connected to the built-in chip 21 through the second conductive structure 31, and both the functional chip 40 and the built-in chip 21 are electrically connected to the first conductive structure 11.

[0051] In one specific implementation, the built-in chip 21 may include a silicon bridge chip, and the number of functional chips 40 is at least two. The at least two functional chips 40 are electrically interconnected with each other through the silicon bridge chip.

[0052] For example, the functional chip 40 can be various types of semiconductor chips such as logic chips, memory chips, radio frequency chips, and power management chips. Multiple functional chips 40 can be interconnected with high bandwidth and low latency through silicon bridge chips to meet the requirements of high-performance computing, artificial intelligence and other applications for inter-chip communication.

[0053] By embedding the silicon bridge chip within a symmetrical rigid structure, high-density interconnection between chips is achieved, while the rigid substrates on both sides suppress warping, solving the warping problem encountered when integrating multiple chips in a large-size interposer. Simultaneously, the internal embedding of the silicon bridge chip avoids surface wiring occupying space, facilitating further reduction in package size. The functional chip 40 is disposed on the upper surface of the second rigid insulating substrate 30, facilitating heat dissipation and testing, and also enabling the subsequent stacking of more chips.

[0054] In some embodiments, the semiconductor package structure 100 further includes a first redistribution layer 51. The first redistribution layer 51 is disposed on the side of the first rigid insulating substrate 10 near the embedded chip 21, i.e., on the upper surface of the first rigid insulating substrate 10. The first redistribution layer 51 includes alternating stacked first dielectric layers and first circuit layers. The first dielectric layer may be made of organic insulating materials such as polyimide, benzocyclobutene, or photosensitive epoxy resin, and is formed by spin coating, spraying, or lamination processes, and the desired opening pattern is formed through photolithography, development, and other steps. The first circuit layer may be made of conductive materials such as copper, aluminum, titanium, or gold, and the desired circuit pattern is formed through sputtering seed layers, electroplating, etching, and other processes.

[0055] One side of the first circuit layer is electrically connected to the first conductive structure 11, and the other side is electrically connected to the built-in chip 21 and / or the third conductive structure 22. Specifically, the lower surface of the first circuit layer is electrically connected to the upper end of the first conductive structure 11 through an opening in the first dielectric layer, and the upper surface of the first circuit layer is electrically connected to the chip pads on the lower surface of the built-in chip 21 and / or the lower end of the third conductive structure 22 through an opening in the first dielectric layer. The first redistribution layer 51 is used to redistribute the signals of the first conductive structure 11 to the built-in chip 21 and the third conductive structure 22, realizing fan-in and fan-out functionality.

[0056] In some embodiments, the semiconductor package structure 100 further includes a second redistribution layer 52, which is disposed on the side of the embedded chip 21 near the second rigid insulating substrate 30, i.e., on the upper surface of the embedded chip 21 and the insulating fill layer 20. The second redistribution layer 52 includes alternately stacked second dielectric layers and second circuit layers. The materials and formation processes of the second dielectric layers and the second circuit layers are similar to those of the first redistribution layer 51.

[0057] One side of the second circuit layer is electrically connected to the second conductive structure 31, and the other side is electrically connected to the built-in chip 21 and / or the third conductive structure 22. Specifically, the upper surface of the second circuit layer is electrically connected to the lower end of the second conductive structure 31 through an opening in the second dielectric layer, and the lower surface of the second circuit layer is electrically connected to the chip pads on the upper surface of the built-in chip 21 and / or the upper end of the third conductive structure 22 through an opening in the second dielectric layer. The second redistribution layer 52 is used to redistribute the signals from the built-in chip 21 and the third conductive structure 22 back to the second conductive structure 31.

[0058] The first redistribution layer 51 and the second redistribution layer 52 are located below and above the built-in chip 21, respectively, forming a double-sided wiring structure. The built-in chip 21 is fanned out through the first redistribution layer 51 and then connected to the upper second redistribution layer 52 through the third conductive structure 22, and further connected to the upper functional chip 40, forming a complete signal path. The double-sided redistribution layer design helps to improve wiring density and design flexibility.

[0059] In some embodiments, the semiconductor package structure 100 further includes a first conductor 61 disposed between the second wiring layer 52 and the functional chip 40 for electrically connecting the second wiring layer 52 and the functional chip 40. The first conductor 61 may be a microbump, copper pillar, solder ball, or other conductive connection structure.

[0060] The semiconductor package structure 100 also includes a second conductor 62, which is disposed on the side of the first rigid insulating substrate 10 away from the functional chip 40, i.e., on the lower surface of the first rigid insulating substrate 10. The second conductor 62 may be a solder ball, a solder pad, a bonding pillar, or other conductive connection structure, used to connect the entire semiconductor package structure 100 to an external circuit board or package substrate.

[0061] The semiconductor package structure 100 also includes an insulating encapsulation layer 70, which is disposed on the side of the second wiring layer 52 away from the built-in chip 21, i.e., on the upper surface of the second wiring layer 52, and surrounds the functional chip 40. The insulating encapsulation layer 70 may be made of epoxy molding compound, underfill adhesive, or other insulating encapsulation materials, and is formed through a secondary potting process.

[0062] In one preferred embodiment, the upper surface of the insulating encapsulation layer 70 can be substantially flush with the upper surface of the functional chip 40, or can completely cover the functional chip 40, depending on the heat dissipation requirements and application scenario. If better heat dissipation performance is required, the upper surface of the functional chip 40 can be exposed to allow for the installation of a heat sink; if better mechanical protection is required, the functional chip 40 can be completely covered.

[0063] The first conductor 61 and the second conductor 62 respectively connect the chip to the carrier board and the carrier board to external circuits, forming a complete packaged interconnect system. The insulating encapsulation layer 70 provides mechanical protection and environmental isolation for the functional chip 40, improving package reliability. The secondary potting process is compatible with the first potting process and is simple and easy to implement. The entire structure forms a complete electrical path from the functional chip 40 to the second conductor 62, with the functional chip 40, the first conductor 61, the second rewiring layer 52, the third conductive structure 22, the first rewiring layer 51, the first conductive structure 11, and the second conductor 62 sequentially electrically connected, achieving a reliable connection between the chip and the external circuit board.

[0064] In some embodiments, such as Figure 4As shown, the semiconductor package structure 100 also includes a circuit board 80, which is disposed on the side of the first rigid insulating substrate 10 away from the built-in chip 21. The built-in chip 21 is electrically connected to the circuit board 80 through the first conductive structure 11, thereby enabling the functional chip 40 to be electrically connected to the circuit board 80. The circuit board 80 can be a printed circuit board or other types of packaging substrate.

[0065] In some embodiments, the embedded chip 21 can be a three-dimensional integrated structure formed by stacking multiple chips. For example, a first layer of embedded chips can be first disposed on a first rigid insulating substrate 10, fanned out through a first redistribution layer 51, and then a second layer of embedded chips can be stacked on top of it. The layers are connected by microbumps or copper pillars, and then uniformly filled with an insulating filler layer 20 to form an overall embedded structure. This multi-layer chip embedding scheme can further improve the integration density and is suitable for AI chip applications that require high computing power density.

[0066] Some embodiments of this application also provide a method for preparing a semiconductor packaging structure, used to prepare the semiconductor packaging structure 100 described in any of the above embodiments.

[0067] like Figure 5 As shown, the method for fabricating the semiconductor package structure 100 specifically includes the following steps: Step S110: Provide a first rigid insulating substrate 10, the first rigid insulating substrate 10 including a first conductive structure 11 disposed through the thickness direction.

[0068] Specifically, a glass substrate is provided as the first rigid insulating substrate 10, a first glass through hole is formed by laser drilling, a first conductive structure 11 is formed by electroplating a filler metal (such as copper), and finally a planarization process is performed.

[0069] Step S120: An embedded chip 21 is disposed on one side of the first rigid insulating substrate 10.

[0070] Furthermore, such as Figure 6 As shown, step S120 includes the following sub-steps: Step S121: A first redistribution layer 51 is formed on one side of the first rigid insulating substrate 10, and the first redistribution layer 51 is electrically connected to the first conductive structure 11. Step S122: Bond the built-in chip 21 to the first rewiring layer 51 to make the built-in chip 21 electrically connected to the first rewiring layer 51. Step S123: Form a plurality of spaced third conductive structures 22 around the built-in chip 21; Step S124: Fill the area around the built-in chip 21 and the third conductive structure 22 with insulating filler material to form an insulating filler layer 20. Specifically, after the first potting to form the insulating filler layer 20, a planarization process is performed using chemical mechanical polishing or grinding to expose the upper surface of the conductive structure on the built-in chip 21 and the upper surface of the third conductive structure 22, forming a flat surface to provide a smooth interface for the subsequent fabrication of the second redistribution layer 52.

[0071] When the built-in chip 21 includes a silicon bridge chip, in step S122 the silicon bridge chip is bonded to the first redistribution layer 51 through a hybrid bonding process to achieve high-density interconnection.

[0072] Step S130: A second rigid insulating substrate 30 is disposed on the side of the built-in chip 21 away from the first rigid insulating substrate 10. The second rigid insulating substrate 30 includes a second conductive structure 31 disposed through the thickness direction.

[0073] Specifically, such as Figure 7 As shown, before setting the second rigid insulating substrate 30, a second redistribution layer 52 can be formed on the built-in chip 21 and the insulating fill layer 20, making it electrically connected to the built-in chip 21 and / or the third conductive structure 22. Then, the second rigid insulating substrate 30 is bonded to the second redistribution layer 52, so that the second conductive structure 31 is electrically connected to the second redistribution layer 52. The bonding of the second rigid insulating substrate 30 and the second redistribution layer 52 can adopt a hybrid bonding process: first, the bonding surface is subjected to plasma activation treatment, then pre-bonding is performed at room temperature, and finally annealing is performed at a temperature of 200-400℃, so that the dielectric layer to dielectric layer and the metal to metal form covalent bonding and metal diffusion bonding, respectively. The fabrication of the third conductive structure 22 can adopt a photolithography and electroplating process: first, photoresist is coated, exposure and development are performed to form an opening, and then copper is electroplated to form a copper pillar.

[0074] When the second rigid insulating substrate 30 uses a glass fiber cloth layer, it can be formed through a vacuum lamination process, eliminating the need for glass through-holes and ensuring compatibility with existing organic substrate production lines. Although its rigidity is slightly weaker than an all-glass structure, the stress buffering and symmetrical structural design of the insulating filler layer 20 still allows the warpage of packages larger than 50mm to be controlled within 70μm, meeting the needs of most applications. The glass fiber cloth layer solution is suitable for cost-sensitive products with moderate warpage requirements.

[0075] In some embodiments, the method for fabricating the semiconductor package structure 100 may further include: In step S140, a functional chip 40 is disposed on the side of the second rigid insulating substrate 30 away from the built-in chip 21.

[0076] Specifically, such as Figure 7As shown, before setting the functional chip 40, a first conductor 61 can be formed on the second wiring layer 52. Then, the functional chip 40 is bonded to the second wiring layer 52 through the first conductor 61. Afterward, an insulating encapsulation material can be filled around the functional chip 40 to form an insulating encapsulation layer 70.

[0077] In addition, the method for fabricating the semiconductor package structure 100 may also include forming a second conductor 62 on the side of the first rigid insulating substrate 10 away from the functional chip 40 for connection with an external circuit board 80.

[0078] Specifically, after the functional chip 40 is bonded to the first conductor 61, underfilling can be performed first: using an underfilling process, underfill adhesive is injected into the gap between the functional chip 40 and the second redistribution layer 52, and then cured at a temperature of 150-180℃ to form an underfill layer. A second potting process is then performed to form the insulating encapsulation layer 70, achieving double-layer encapsulation protection. The second conductor 62 can be a copper pillar or a solder ball. When using a copper pillar, it can be formed on the lower surface of the first rigid insulating substrate 10 through an electroplating process, with the pillar height controlled between 50-200 μm; when using a solder ball, it can be implanted into the lower end of the first conductive structure 11 through a ball-planting process, and then reflow soldering is performed.

[0079] It should be noted that, in specific process implementations, to further improve the interface bonding strength and reliability, seed layer and buffer layer structures can be set at critical interfaces. For example, when forming a redistribution layer, a metal seed layer such as titanium / copper can be set between the circuit layer and the dielectric layer to improve adhesion. When filling glass vias, a buffer layer such as silicon oxide can be set between the via wall and the metal to provide electrical isolation and stress relief.

[0080] For example, before forming the first and second circuit layers, a titanium / copper seed layer can be sputtered onto the surface of the dielectric layer. The titanium layer acts as an adhesion layer and a diffusion barrier layer, forming a chemical bond with the polyimide dielectric layer to prevent copper diffusion. The copper layer acts as an electroplated conductive layer to ensure uniform circuit growth.

[0081] Before filling the first and second glass vias, an atomic layer deposition process can be used to deposit a silicon oxide buffer layer on the via walls. The silicon oxide layer provides electrical isolation to prevent leakage caused by direct contact between the metal and the glass, while filling microscopic defects in the glass via walls and improving the metal filling quality.

[0082] The semiconductor packaging structure and its fabrication method provided in this application effectively balance thermal stress and reduce warpage issues in large-sized packages through a symmetrical rigid insulating substrate sandwich structure. Chips are embedded between the substrates, and multi-chip interconnection can be achieved through silicon bridge chips. Simultaneously, the dual-sided redistribution layers increase wiring density. The process of fabricating conductive structures first and then potting, along with a successive layer-addition technique for fabricating the redistribution layers, ensures good compatibility with existing production lines. The insulating filler layer provides encapsulation and protection for the chip and conductive structures, while the dual-sided redistribution layers enhance wiring flexibility, resulting in high overall structural mechanical stability. Various rigid insulating materials, such as glass and fiberglass cloth, can be flexibly selected according to performance and cost requirements.

[0083] The semiconductor packaging structure provided in this application can be applied to multiple fields such as AI chips, high-performance computing, 6G communication, RF front-end, optoelectronic co-packaging, and microelectromechanical systems. Through a symmetrical rigid sandwich structure and built-in chip design, utilizing the low thermal expansion coefficient, high rigidity, and low dielectric loss of the glass substrate, combined with the vertical heat conduction path formed by the conductive structure, high-density interconnection is achieved while effectively controlling warpage. Furthermore, adaptive structural optimizations have been implemented to address the inherent defects of glass, such as low thermal conductivity and high brittleness, meeting the differentiated needs of various application scenarios, including high-frequency and high-speed signal transmission, high-power heat dissipation, and optoelectronic co-integration.

[0084] The semiconductor packaging structure described in this application is suitable for large-size multi-chip integration scenarios. Through the symmetrical design of the upper and lower rigid substrates and the stress buffering of the insulating filler layer, the warpage of packages larger than 50mm can be controlled within 50μm by using an all-glass solution for the rigid substrates on both sides. By using a hybrid solution of glass and glass fiber cloth, the warpage can be controlled within 70μm, meeting the warpage requirements of different application scenarios. At the same time, the flexible selection of all-glass substrates and glass-glass fiber cloth hybrid material solutions can balance the requirements of high performance and low cost, adapting to industrial applications of different levels of products such as consumer electronics, communication infrastructure, and data centers while ensuring structural rigidity and reliability.

[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor packaging structure, characterized in that, include: A first rigid insulating substrate includes a first conductive structure disposed through the thickness direction; An embedded chip is disposed on one side of the first rigid insulating substrate, and the embedded chip is electrically connected to the first conductive structure; A second rigid insulating substrate is disposed on the side of the built-in chip away from the first rigid insulating substrate. The second rigid insulating substrate includes a second conductive structure that extends through the chip along the thickness direction. The built-in chip is electrically connected to the second conductive structure. A functional chip is disposed on the side of the second rigid insulating substrate away from the built-in chip, and the functional chip is electrically connected to the built-in chip through the second conductive structure; The built-in chip includes a silicon bridge chip, and the number of functional chips is at least two, with the at least two functional chips being electrically connected through the silicon bridge chip.

2. The semiconductor packaging structure according to claim 1, characterized in that, The material of at least one of the first rigid insulating substrate and the second rigid insulating substrate includes glass.

3. The semiconductor packaging structure according to claim 1, characterized in that, The second rigid insulating substrate includes a glass fiber cloth layer.

4. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: An insulating filler layer is disposed between the first rigid insulating substrate and the second rigid insulating substrate, and at least covers the sidewalls of the built-in chip; A third conductive structure is disposed within the insulating filler layer, and the first conductive structure is electrically connected to the second conductive structure through the third conductive structure.

5. The semiconductor packaging structure according to claim 4, characterized in that, Also includes: A first wiring layer is disposed on the side of the first rigid insulating substrate close to the embedded chip. The first wiring layer includes alternating stacked first dielectric layers and first circuit layers. One side of the first circuit layer is electrically connected to the first conductive structure, and the other side is electrically connected to the embedded chip and / or the third conductive structure. The second wiring layer is disposed on the side of the built-in chip near the second rigid insulating substrate. The second wiring layer includes alternately stacked second dielectric layers and second circuit layers. One side of the second circuit layer is electrically connected to the second conductive structure, and the other side is electrically connected to the built-in chip and / or the third conductive structure.

6. The semiconductor packaging structure according to claim 5, characterized in that, Also includes: A first conductor is disposed between the second wiring layer and the functional chip to electrically connect the second wiring layer and the functional chip; The second conductor is disposed on the side of the first rigid insulating substrate away from the functional chip; An insulating encapsulation layer is disposed on the side of the second wiring layer away from the built-in chip and surrounds the functional chip.

7. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: A circuit board is disposed on the side of the first rigid insulating substrate away from the built-in chip, and the built-in chip is electrically connected to the circuit board through the first conductive structure.

8. A method for fabricating a semiconductor packaging structure, characterized in that, The method includes: A first rigid insulating substrate is provided, the first rigid insulating substrate including a first conductive structure disposed through the thickness direction; An embedded chip is disposed on one side of the first rigid insulating substrate; A second rigid insulating substrate is disposed on the side of the built-in chip away from the first rigid insulating substrate, and the second rigid insulating substrate includes a second conductive structure disposed through the thickness direction; A functional chip is disposed on the side of the second rigid insulating substrate away from the built-in chip, and the functional chip is electrically connected to the built-in chip through the second conductive structure; wherein, the built-in chip includes a silicon bridge chip, and the number of the functional chips is at least two, and the at least two functional chips are electrically connected through the silicon bridge chip.

9. The method for preparing a semiconductor packaging structure according to claim 8, characterized in that, The provision of a built-in chip on one side of the first rigid insulating substrate includes: A first redistribution layer is formed on one side of the first rigid insulating substrate, and the first redistribution layer is electrically connected to the first conductive structure. The built-in chip is bonded to the first rewiring layer, so that the built-in chip is electrically connected to the first rewiring layer; Multiple spaced third conductive structures are formed around the built-in chip; An insulating filler material is filled around the built-in chip and the third conductive structure to form an insulating filler layer; Before the second rigid insulating substrate is disposed on the side of the built-in chip away from the first rigid insulating substrate, the method further includes: A second redistribution layer is formed on the side of the built-in chip and the insulating fill layer away from the first rigid insulating substrate, and the second redistribution layer is electrically connected to the built-in chip and / or to the third conductive structure; The second rigid insulating substrate is disposed on the side of the second redistribution layer away from the built-in chip, and the second conductive structure is electrically connected to the second redistribution layer.

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