Package structure and testing method

Abstract

The application relates to the technical field of semiconductors, and discloses a packaging structure and a testing method. The packaging structure comprises a first through hole arranged on a cathode molybdenum sheet and overlapping a part of the gate of a target cell, a second through hole arranged on a cathode tube shell, the first through hole and the second through hole being in series, a first lead unit comprising a first lead end in contact with the gate of the target cell and a first lead with a first end connected to the first lead end and a second end led out through the first through hole and the second through hole, and a second lead unit comprising a second lead end in contact with the cathode molybdenum sheet and a second lead with a first end connected to the second lead end and a second end led out through the second through hole. The application can directly measure the commutation parameters of the cell level in the turn-off process of the power device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a packaging structure and testing method. Background Technology

[0002] An IGCT (Integrated Gate Commutated Thyristor) is a novel power semiconductor device that integrates a packaged GCT chip with a gate drive unit. IGCTs offer advantages such as low loss, high switching frequency, fast commutation speed, low heat dissipation, and high reliability, making them invaluable in high-voltage, high-current applications. Based on their structure, IGCT devices can be classified into asymmetric, reverse-conducting, reverse-resistive, and wavy-base types. Taking an asymmetric IGCT device as an example, its typical GCT cell structure is as follows... Figure 1 As shown, the chip has a PNPN four-layer triple-junction structure in the vertical direction, specifically including a cathode, gate, gate ring (not shown), n+ emitter, p-base region, n-base region, n+ buffer layer, p+ emitter, and anode. In the horizontal structure, the GCT chip has concentric ring-shaped strip cells. The gates of the cells are distributed around the strip cathodes, and the metal regions of the gates at different locations are connected and jointly led out by the gate ring (e.g., ...). Figure 3a (As shown).

[0003] The turn-on and turn-off principles of IGCT devices are as follows: Figure 2a , Figure 2b As shown, during the turn-off process, by applying a negative pulse voltage (or current, i.e., reverse voltage or current) with high amplitude and high rise rate between the gate and cathode, the PN junction (J3 junction) between the gate and cathode of the IGCT device is rapidly restored to blocking state, causing the anode current to transfer from the cathode to the gate, thereby completing the commutation process. At this time, because the positive feedback between the NPN transistor on the cathode side and the PNP transistor on the anode side is broken, turn-off is gradually achieved.

[0004] During the turn-off period of an IGCT device, due to its large lateral dimensions, cells farther from the gate ring (i.e., far-gate ring cells) have longer commutation paths and higher impedance and inductive reactance. Therefore, the time required for the cathode current to transition to the gate ring in these cells is longer, resulting in a slower turn-off speed. In contrast, cells closer to the gate ring (i.e., near-gate ring cells) can complete current transition and form a depletion layer more quickly. This difference in turn-off speed between cells at different locations can cause the following problems: cells closer to the gate ring may enter the turn-off state earlier, while cells farther from the gate ring may remain conducting due to incomplete charge removal, leading to localized current concentration. This can cause overheating and excessively high electric field strength in localized areas of the chip, ultimately resulting in chip damage or decreased reliability. This phenomenon is also known as the delay effect, which has a serious negative impact on the lifespan of IGCT devices in practical applications. To analyze and address the hazards caused by the back-delay effect, it is necessary to measure the commutation process of the far-gate and near-gate polarity ring cells. This will allow for comparison and analysis of the turn-off voltage differences between the far and near-gate polarity ring cells, thereby guiding the optimization of chip cell layout and improvement of driver circuit design.

[0005] However, existing turn-off testing methods require the GCT chip to be pressed into a casing or packaged before it can be connected to an external circuit for testing. This involves collecting data between the gate ring and the cathode. Figure 4 The voltage difference across the test circuit shown (i.e., the voltage V between the housing and the cathode interface of the drive board) GK To further derive the voltage V of the J3 junction inside the IGCT device. J3 Since the gate metal regions at different locations are connected and all led out by the gate ring, the measured V... J3 It is the total voltage and current characteristics of all cells in the GCT connected in parallel. It is not possible to obtain the commutation process and electrical parameters of a single cell in the IGCT device, so it is impossible to analyze the commutation difference between far and near gate ring cells. Summary of the Invention

[0006] The purpose of this invention is to provide a packaging structure and testing method that reduces the influence of stray parameters of the package on the test results without changing the current path during the commutation process. This allows for direct measurement of commutation parameters at the cell level during the turn-off process of power devices, resulting in measurement results that are closer to the actual situation. The testing method is simple and easy to implement, and the test results are stable and reliable.

[0007] To achieve the above objectives, a first aspect of the present invention provides a packaging structure comprising a power device, the power device including a power chip; a molybdenum cathode; a cathode housing; and a gate drive unit for applying a reverse voltage between the gate ring and the cathode of the power chip during a turn-off test. The packaging structure includes: a first via disposed on the molybdenum cathode, the first via overlapping at least a portion of the gate region of a first target cell of the power chip; a second via disposed on the cathode housing, wherein the second via and the first via are interconnected; a first lead unit comprising: a first lead end contacting the gate of the first target cell; and a first lead, a first end of which is connected to the first lead end, and a second end of which is led out through the first via and the second via; and a second lead unit comprising: a second lead end contacting the molybdenum cathode; and a second lead, a first end of which is connected to the second lead end, and a second end of which is led out through the second via.

[0008] Preferably, the packaging structure further includes: a first lead groove, the first lead groove being connected to the second through hole, the second end of the first lead being led out through the first through hole, the second through hole and the first lead groove, and the second end of the second lead being led out through the second through hole and the first lead groove.

[0009] Preferably, the packaging structure further includes: a third through-hole disposed on the cathode molybdenum sheet, wherein the third through-hole overlaps at least a portion of the gate region of the second target cell of the power chip, and the distance of the first target cell from the gate ring is different from the distance of the second target cell from the gate ring; a fourth through-hole disposed on the cathode housing, wherein the fourth through-hole and the third through-hole are interconnected; a third lead unit comprising: a third lead end contacting the gate of the second target cell, and a third lead, wherein a first end of the third lead is connected to the third lead end, and a second end of the third lead is led out through the third through-hole and the fourth through-hole; and a fourth lead unit comprising: a fourth lead end contacting the cathode molybdenum sheet, and a fourth lead, wherein a first end of the fourth lead is connected to the fourth lead end, and a second end of the fourth lead is led out through the fourth through-hole.

[0010] Preferably, the packaging structure further includes: a second lead groove, the second lead groove being connected to the fourth through hole, the second end of the third lead being led out through the third through hole, the fourth through hole and the second lead groove, and the second end of the fourth lead being led out through the fourth through hole and the second lead groove.

[0011] Preferably, the gate in the first target cell and the gate in the second target cell are located on the same radial direction of the power chip, and the first lead slot and the second lead slot are the same slot.

[0012] Preferably, the cathode of one of the first target cells and the second target cells is located on the cathode ring furthest from the gate ring, and the cathode of the other cell is located on the cathode ring closest to the gate ring.

[0013] Preferably, the radius of the first through hole is less than or equal to the radius of the second through hole, and the radius of the third through hole is less than or equal to the radius of the fourth through hole.

[0014] Preferably, the radius of the first through hole and the third through hole is 1-4 mm, and the radius of the second through hole and the fourth through hole is 2-6 mm.

[0015] Preferably, the centers of the first through hole and the second through hole are aligned, and the centers of the third through hole and the fourth through hole are aligned.

[0016] Preferably, the first lead end, the second lead end, the third lead end, and the fourth lead end are thin probes or spring probes.

[0017] Preferably, the first lead, the second lead, the third lead, and the fourth lead are twisted-pair shielded cables.

[0018] Preferably, the power device is an IGCT device or an IGTO device.

[0019] A second aspect of the present invention provides a testing method applied to the packaging structure of any of the foregoing embodiments of the first aspect of the present invention. The packaging structure further includes a third via, a third lead unit including a third lead end and a third lead, and a fourth lead unit including a fourth lead end and a fourth lead. The third via at least overlaps with a portion of the gate region of the second target cell of the power chip. The testing method includes: using a voltage detection device to detect the voltage between the first lead and the second lead to obtain the voltage of the PN junction between the gate and the cathode of the first target cell.

[0020] Preferably, the testing method further includes: using a voltage detection device to detect the voltage between the third lead and the fourth lead to obtain the voltage of the PN junction between the gate and the cathode of the second target cell; calculating the difference between the voltage of the PN junction between the gate and the cathode of the first target cell and the voltage of the PN junction between the gate and the cathode of the second target cell to obtain the voltage difference.

[0021] Through the above technical solution, the present invention creatively sets any cell in the power device (e.g., IGCT device) as the first target cell, and uses through holes for lead-in so that the test circuit does not pass through the cathode case. Therefore, without changing the current path during the commutation process, the influence of the case stray parameters on the test results is reduced. Thus, the commutation parameters at the cell level can be directly measured during the turn-off process of the power device. The measurement results are closer to the actual situation. The test method is simple and easy to implement, and the test results are stable and reliable.

[0022] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0023] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0024] Figure 1 This is a schematic diagram of the cell structure of an IGCT device;

[0025] Figure 2a and Figure 2b These are schematic diagrams of the IGCT device being turned on and off, respectively.

[0026] Figure 3a and Figure 3b These are schematic diagrams of the horizontal and vertical structures of a GCT chip with a central gate ring.

[0027] Figure 4 This is a schematic diagram of the packaging shell of an existing IGCT device;

[0028] Figure 5 This is a schematic diagram of the packaging structure provided in an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of the packaging structure provided in an embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of the packaging structure provided in an embodiment of the present invention;

[0031] Figure 8 This is a test schematic diagram of an IGCT device provided in an embodiment of the present invention;

[0032] Figure 9a and Figure 9b These are schematic diagrams of the lateral and longitudinal structures of an IGCT device with an outer gate electrode ring; and

[0033] Figure 10This is a test schematic diagram of an IGCT device provided in an embodiment of the present invention. Detailed Implementation

[0034] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0035] Before describing specific embodiments of the present invention, a specific structure of a power device (e.g., an IGCT device) and the relevant process of conventional turn-off testing are first introduced. The present invention mainly uses an IGCT device as an example to illustrate the characteristics of such devices. Figure 1 The test method for the commutation process of the power device shown in the cell is described, but this does not mean that the present invention is limited to IGCT devices.

[0036] like Figure 1 , Figure 2a and Figure 2b As shown, Figure 1 , Figure 2a and Figure 2b J1, J2, and J3 in the text refer to three PN junctions in the internal PNPN four-layer structure of the GCT device, with J1 being a p + emitter and n + J2 is the PN junction between the buffer layers, J3 is the NP junction between the n-base region and the p-base region, and J4 is the NP junction between the p-base region and the n-base region. + The PN junction between the emitters is the PN junction between the gate and cathode of a GCT device.

[0037] Taking asymmetric IGCT devices as an example, Figure 3a and Figure 3b This diagram illustrates the structure of a GCT chip with a central gate ring. The diagram shows the lateral structure of the GCT chip. Figure 3a The GCT chip consists of a gate ring structure and eight cathode rings from the inside out (this is just an example; the actual number of cathode rings in the GCT chip should not be limited by this diagram). Cathode rings 1-5 are located inside the gate ring, and cathode rings 6-8 are located outside the gate ring. Therefore, structurally, the cells on the first and eighth cathode rings are farther from the gate ring, while the cells on the fifth and sixth cathode rings are closer to the gate ring. The longitudinal structure of the GCT cell is shown below. Figure 3b As shown, it includes a cathode, gate, gate ring, n+ emitter, p-base region, n-base region, n+ buffer layer, p+ emitter, and anode. The cathode is located on the silicon mesa, with a certain height difference between it and the gate at the bottom of the mesa. Typically, GCT chips need to be packaged in a die and integrated with the gate driver unit before they can be tested and used normally. Figure 4As shown, the package of the IGCT device mainly includes an anode cap 1, an anode molybdenum sheet 2, a gate pressure ring 3, a gate lead-out ring 4, a cathode molybdenum sheet 5, a cathode housing 6 (also known as a cathode socket), a cathode lead-out ring 7, and a GCT chip 8. The cathode side of the GCT chip 8 contacts the cathode molybdenum sheet, and the anode side contacts the anode molybdenum sheet. The gate drive unit includes a switching element 9 (e.g., a MOSFET) and a capacitor 10 connected in parallel with the gate cathode of the GCT chip 8. The switching element 9 and the capacitor 10 are connected in series. The switching element 9 is connected to the gate ring of the GCT chip 8 via the gate lead-out ring 4 and the gate pressure ring 3. The capacitor 10 is connected to the cathode of the GCT chip 8 via the cathode lead-out ring 7 and the cathode housing 6. The cathode of the GCT chip 8 is grounded via the cathode molybdenum sheet 5 and the cathode housing 6.

[0038] During routine shutdown testing, the packaged IGCT device needs to be placed on the test stage with the cathode facing down and the anode facing up. A bus voltage V is applied between the anode and cathode during the test. AK By controlling the switching element 9 of the gate drive unit, a reverse voltage V is applied between the gate and cathode (J3 junction) using capacitor 10. GK (i.e., the voltage at the cathode interface between the casing and the drive board gate) depletes the J3 junction, thereby ensuring that the cathode current is completely transferred to the gate and the commutation process is completed.

[0039] The commutation circuit during turn-off includes a GCT chip, a package, a gate driver board circuit, and a gate driver unit (switching element and capacitor) connected in series. One or more of the following electrical parameters exist during commutation, including: the voltage V of the J3 junction inside the IGCT device. J3 The voltage V at the cathode interface between the tube shell and the drive plate door. GK The voltage V across the capacitor CO The voltage V across the switching element M Voltage V of the driver board circuit PCB Internal voltage V of capacitor CI Gate current i G Stray resistance R of the casing P (Including cathode stray R) PK and gate stray R PG ) and inductance L P (Including cathode stray L) PK and gate stray L PG The stray resistance R of the capacitor C and inductor L C Stray resistance R of the driver board circuit PCB and inductor L PCB Among them, the voltage V of the J3 junction inside the GCT chip. J3It is the combined value exhibited by thousands of cells connected in parallel. According to Kirchhoff's laws, the voltage V J3 Other electrical parameters in the above-mentioned turn-off process can satisfy the following formula:

[0040] (1)

[0041] Among them, the voltage V at the cathode interface between the tube shell and the drive plate door. GK The waveform and gate current i G The waveform of (anode current minus cathode current) can be directly measured using conventional voltage and current probes and an oscilloscope. However, according to the above formula, to accurately obtain the voltage of the J3 junction inside the GCT cell... The following difficulties exist with parameters such as V: GK The test results will be affected by the stray resistance and inductance of the tube shell, especially due to the induced electromotive force generated by the coupling of the spatial magnetic field in the test circuit. The impact of this on the results is significant and cannot be ignored; therefore, it cannot be passed by V. GK To effectively judge V J3 The situation is twofold: firstly, even if the stray resistance and inductance parameters of the casing are known, and V can be calculated... J3 However, this result is only a comprehensive result reflected by the parallel connection of all cells of the GCT chip as a whole. It cannot obtain the commutation situation of the cell level itself, let alone analyze the commutation difference between the far and near gate ring cells at the same time.

[0042] To enable monitoring of the cell-level commutation process of power devices during turn-off, this invention proposes a packaging structure for directly measuring the cell-level commutation process.

[0043] Example 1

[0044] Figure 5 This is a schematic diagram of a packaging structure provided in an embodiment of the present invention. The packaging structure includes a power device, which is the packaged device. Figure 4 As shown, the power device includes a power chip (in the case of an IGCT, the power chip is a GCT chip 8); a molybdenum cathode 5; a cathode housing 6; and a gate drive unit (which may include a switching element 9 and a capacitor 10) for applying a reverse voltage between the gate ring and the cathode of the power chip (e.g., the GCT chip 8) during a turn-off test. Figure 5 As shown, the packaging structure includes: a first through hole 11 and a second through hole 12, a first lead unit for leading out the gate signal of the first target cell, and a second lead unit for leading out the cathode molybdenum sheet signal of the first target cell.

[0045] The gate drive unit may include a switching element 9 and a capacitor 10, such as... Figure 4 As shown. Since the power device is a packaged device, it has a package and a gate driver unit. For details on the connection method of the gate driver unit, please refer to existing technology or... Figure 4 The relevant description states that the gate drive unit is used to apply a reverse voltage (V) between the gate ring and cathode of the power device during the turn-off test. GK Specifically, the configuration of the gate drive unit and its description during the turn-off test are not the main improvements of this invention, and will not be elaborated here. Please refer to existing technologies or... Figure 4 Related descriptions.

[0046] To enable testing of the gate and cathode leads in the measured cell region, the cathode molybdenum sheet and cathode housing need to be processed and through-holes formed, respectively. In this embodiment, a first through-hole 11 is disposed on the cathode molybdenum sheet 5, and the first through-hole 11 overlaps at least with a portion of the gate region of the first target cell of the power chip; and a second through-hole 12 is disposed on the cathode housing 6. The second through-hole 12 is interconnected with the first through-hole 11. Thus, the first lead and the second lead can be smoothly led out, as detailed below.

[0047] Specifically, the first lead unit includes: a first lead end (not shown) that contacts the gate of the first target cell; and a first lead 13, the first end of which is connected to the first lead end, and the second end of which is led out through the first through hole 11 and the second through hole 12, such as... Figure 5 As shown.

[0048] The second lead unit includes: a second lead end (not shown) in contact with the cathode molybdenum sheet 5; and a second lead 14, the first end of which is connected to the second lead end, and the second end of which is led out through the second through hole 12; and

[0049] The packaging structure of this embodiment uses a testing device (e.g., an oscilloscope 16) to detect voltage. The testing device (not shown) is connected to the second end of the first lead 13 and the second end of the second lead 14 to test the voltage between the first lead 13 and the second lead 14.

[0050] Since any cell in the power device (such as the IGCT device) can be set as the first target cell, and the test circuit can be led through a via so that it does not pass through the cathode case, the influence of the case stray parameters on the test results is reduced without changing the current path during the commutation process. Thus, the commutation parameters at the cell level can be measured directly during the turn-off process of the GCT chip. The measurement results are closer to the actual situation, the test method is simple and easy to implement, and the test results are stable and reliable.

[0051] Example 2

[0052] Since pressure needs to be applied to the tube shell during the shutdown test, in order to avoid the lead wires used in the method of this invention from affecting the normal test, a lead wire groove can be set in the cathode tube shell, and then all the lead wires can be put into the lead wire groove.

[0053] Based on the above embodiments, the packaging structure further includes: a first lead groove 15, which is connected to the second through hole 12, such as... Figure 5 As shown.

[0054] Accordingly, the second end of the first lead 13 is led out through the first through hole 11, the second through hole 12 and the first lead groove 15, and the second end of the second lead 14 is led out through the second through hole 12 and the first lead groove 15.

[0055] The first lead groove 15 can be distributed radially along the first target cell. Of course, the present invention does not limit this radial direction and can be reasonably set according to actual needs.

[0056] Example 3

[0057] To reduce the impact of vias on the current flow of the IGCT device itself, based on any of the above embodiments, the centers of the first via 11 and the second via 12 are aligned to ensure that the first via 11 is within the range of the second via 12, thereby reducing the additional via area and thus reducing its impact on the current flow of the device.

[0058] Example 4

[0059] To minimize the impact of vias on the current flow of the IGCT device itself, the design principle for vias is to keep the via size as small as possible while ensuring normal gate cathode leads (for example, the radius of the via for the cathode molybdenum sheet can be set to 2-6 mm).

[0060] Based on any of the above embodiments, the radius of the first through hole 11 is less than or equal to the radius of the second through hole 12.

[0061] For example, the radius of the first through hole 11 is 1-4 mm, and the radius of the second through hole 12 is 2-6 mm. Of course, the above values ​​are based on the premise that the radius of the first through hole is less than or equal to the radius of the second through hole.

[0062] For example, when the centers of the first through hole 11 and the second through hole 12 are aligned and the radius of the first through hole 11 is less than or equal to the radius of the second through hole 12, it indicates that the size of the through hole on the cathode housing should be larger than the size of the through hole of the cathode molybdenum sheet, and the projection area of ​​the through hole on the cathode housing on the cathode surface should completely include the projection area of ​​the through hole of the cathode molybdenum sheet on the cathode surface. This design can ensure that the total through hole area of ​​both is relatively small, thereby reducing the impact on the current flow of the IGCT device.

[0063] In addition, the shape of the through hole can be set differently. For example, the shape of the through hole can be circular, square, etc., and its specific size design is related to the lead wire method.

[0064] Example 5

[0065] The contact method between the lead end and the corresponding metal can be crimping or welding. For example, the contact method between the first lead end and the gate metal can be crimping or welding. Preferably, a fine probe / spring probe can form a stable and reliable contact with the gate metal region under a certain pressure. Similarly, the contact method between the second lead end and the cathode molybdenum sheet (e.g., bottom or sidewall) can be crimping or welding. Preferably, a fine probe / spring probe can form a stable and reliable contact with the cathode molybdenum sheet under a certain pressure.

[0066] Preferably, based on any of the above embodiments, the first lead end and the second lead end are fine probes or spring probes.

[0067] In other words, the gate-side lead is in contact with the gate metal of the power device (such as an IGCT device), and the cathode-side test lead is in contact with the cathode molybdenum sheet.

[0068] like Figure 5 As shown, the first lead 13 leads out the gate signal of the first target cell via a spring probe. The first lead 13 passes through the first through hole 11 (i.e., the cathode molybdenum sheet through hole), the second through hole 12 (i.e., the cathode housing through hole), and the first lead groove 15 to connect to the oscilloscope 16. The second lead 14 contacts the cathode molybdenum sheet by pressure bonding to lead out the cathode signal. The second lead 14 passes through the second through hole 12 (i.e., the cathode housing through hole) and the first lead groove 15 to connect to the oscilloscope 16.

[0069] Example 6

[0070] The encapsulation structure further includes: a third through-hole 17 and a fourth through-hole 18 (e.g., ...). Figure 6As shown), the third lead unit is used to extract the gate signal of the second target cell, and the fourth lead unit is used to extract the cathode molybdenum sheet signal of the second target cell.

[0071] To enable testing of the gate and cathode leads in the measured cell region, the cathode molybdenum sheet and cathode housing need to be processed and through-holes formed, respectively. In this embodiment, a third through-hole 17 is disposed on the cathode molybdenum sheet 5, and the third through-hole 17 overlaps at least with a portion of the gate region of the second target cell of the power chip. The distance from the first target cell to the gate ring is different from the distance from the second target cell to the gate ring. A fourth through-hole 18 is disposed on the cathode housing 6, wherein the fourth through-hole 18 is interconnected with the third through-hole 17. Thus, the third lead and the fourth lead can be smoothly led out, as detailed below.

[0072] The third lead unit is similar to the first lead unit; the fourth lead unit is similar to the second lead unit, see [link to relevant documentation]. Figure 5 The diagram shows the first lead unit and the second lead unit.

[0073] Specifically, the third lead unit includes: a third lead end (not shown) that contacts the gate of the second target cell; and a third lead (not shown), the first end of which is connected to the third lead end, and the second end of which is led out through the third through hole 17 and the fourth through hole 18, as shown. Figure 6 As shown.

[0074] The fourth lead unit includes: a fourth lead end (not shown) that contacts the cathode molybdenum sheet 5; and a fourth lead (not shown), the first end of which is connected to the fourth lead end, and the second end of which is led out through the fourth through hole 18.

[0075] Accordingly, the testing device (not shown) is also used to connect the second end of the third lead to the second end of the fourth lead, for testing the voltage between the third lead and the fourth lead.

[0076] Example 7

[0077] Since pressure needs to be applied to the tube shell during the shutdown test, in order to avoid the lead wires used in the method of this invention from affecting the normal test, a lead wire groove can be set in the cathode tube shell, and then all the lead wires can be put into the lead wire groove.

[0078] like Figure 6 As shown, the packaging structure further includes a second lead groove 19, which is connected to the fourth through hole 18.

[0079] Accordingly, the second end of the third lead is led out through the third through hole 17, the fourth through hole 18 and the second lead groove 19, and the second end of the fourth lead is led out through the fourth through hole 18 and the second lead groove 19.

[0080] The second lead groove 19 can be distributed radially along the location of the second target cell. However, this invention does not limit this radial distribution and can be reasonably configured according to actual needs. Furthermore, the second lead groove 19 and the first lead groove 15 can be in the same direction (e.g., ...). Figures 6-7 In the same radial direction, wherein the second lead groove 19 partially overlaps with the first lead groove 15 (i.e., the second lead groove 19 includes the first lead groove 15), it may also be in different directions.

[0081] Example 8

[0082] To reduce the impact of vias on the current flow of the IGCT device itself, based on any of the above embodiments, the center of the third via 17 and the fourth via 18 are aligned to ensure that the first via 11 can be within the range of the second via 12, thereby reducing the additional via area and thus reducing its impact on the current flow of the device.

[0083] Example 9

[0084] To minimize the impact of vias on the current flow of the IGCT device itself, the design principle for vias is to keep the via size as small as possible (e.g., radius of 2-6 mm) while ensuring normal gate cathode leads.

[0085] Based on any of the above embodiments, the radius of the third through hole 17 is less than or equal to the radius of the fourth through hole 18.

[0086] For example, the radius of the third through hole 17 is 1-4 mm, and the radius of the fourth through hole 18 is 2-6 mm. Of course, the above values ​​are based on the premise that the radius of the third through hole is less than or equal to the radius of the fourth through hole.

[0087] For example, when the center of the third through hole 17 is aligned with the center of the fourth through hole 18 and the radius of the third through hole 17 is less than or equal to the radius of the fourth through hole 18, it indicates that the size of the through hole on the cathode housing should be larger than the size of the through hole of the cathode molybdenum sheet, and the projection area of ​​the through hole on the cathode housing on the cathode surface should completely include the projection area of ​​the through hole of the cathode molybdenum sheet on the cathode surface. This setting can reduce the influence of the through hole setting on the current flow of the IGCT device.

[0088] In addition, the shape of the through hole can be set differently. For example, the shape of the through hole can be circular, square, etc., and its specific size is related to the lead wire method.

[0089] Example 10

[0090] The contact method between the lead end and the corresponding metal can be crimping or welding. For example, the contact method between the third lead end and the gate metal can be crimping or welding. Preferably, a fine probe / spring probe can form a stable and reliable contact with the gate metal region under a certain pressure. Similarly, the contact method between the fourth lead end and the cathode molybdenum sheet can be crimping or welding. Preferably, a fine probe / spring probe can form a stable and reliable contact with the cathode molybdenum sheet under a certain pressure.

[0091] Based on any of the above embodiments, the third lead end and the fourth lead end are fine probes or spring probes.

[0092] In other words, the gate-side lead is in contact with the gate metal of the power device (such as an IGCT device), and the cathode-side test lead is in contact with the cathode molybdenum sheet.

[0093] Similar to the lead configuration of the first target cell, the third lead, via a spring probe, leads out the gate signal of the second target cell. This third lead passes through the third through-hole 17 (i.e., the cathode molybdenum sheet through-hole), the fourth through-hole 18 (i.e., the cathode housing through-hole), and the second lead slot 19 to connect to the oscilloscope 16. The fourth lead contacts the cathode molybdenum sheet via pressure bonding to lead out the cathode signal. This fourth lead passes through the fourth through-hole 18 (i.e., the cathode housing through-hole) and the second lead slot 19 to connect to the oscilloscope, as shown below. Figure 6 As shown.

[0094] Example 11

[0095] The gate in the first target cell and the gate in the second target cell are located on the same radial direction of the power chip, and the second lead slot 19 and the first lead slot 15 are on the same radial direction, as shown below. Figure 6 As shown, this configuration structure is simple and can effectively reduce the difficulty of processing this packaging structure.

[0096] For example, the gate in the first target cell and the gate in the second target cell are located on the same radial direction of the power chip. A third lead, via a spring probe, leads out the gate signal of the second target cell. This third lead passes through the third through-hole 17 (i.e., the cathode molybdenum sheet through-hole), the fourth through-hole 18 (i.e., the cathode housing through-hole), and the first lead slot 15 to connect to the oscilloscope 16. A fourth lead, by bonding, contacts the cathode molybdenum sheet to lead out the cathode signal. This fourth lead passes through the fourth through-hole 18 (i.e., the cathode housing through-hole) and the second lead slot 19 to connect to the oscilloscope 16, wherein the second lead slot 19 includes the first lead slot 15 (or the second lead slot 19 and the first lead slot 15 are on the same radial direction).

[0097] Specifically, the cathode of one of the first target cells and the second target cells is located on the cathode ring furthest from the gate ring, while the cathode of the other cell is located on the cathode ring closest to the gate ring.

[0098] For example, the cathode in the first target cell can also be located in the cathode ring closest to the gate ring (e.g. Figure 3a The cathode in the second target cell is located on the 5th or 6th cathode ring (e.g., the 5th or 6th cathode ring in the gate ring), and the cathode in the second target cell is located on the cathode ring furthest from the gate ring (e.g., the 5th or 6th cathode ring in the gate ring). Figure 3a On the first cathode ring in the middle.

[0099] Example 12

[0100] Based on any of the above embodiments, the first lead 13, the second lead 14, the third lead (not shown) and the fourth lead (not shown) can be enameled wire, twisted pair shielded wire, PCB flying wire, etc.

[0101] Preferably, the lead wires of the gate and cathode test can be twisted-pair shielded wires, which can filter the signal during the test process, reduce the influence of spatial magnetic field coupling, and thus make the test results more accurate.

[0102] Example 13

[0103] To monitor the cell-level commutation process of power devices (such as IGCT devices) during turn-off, this embodiment proposes a test method for directly measuring the cell commutation process. Specifically, the corresponding test principle can be found in [link to relevant documentation]. Figure 8 The enlarged view inside the dashed box in the lower right corner and on the right side shows that, while keeping the original normal turn-off test circuit unchanged, the gate and cathode regions of the cell to be observed are connected to an oscilloscope for measurement. The gate of the cell is led out using a fine probe crimping or soldering method, and the cell cathode is led out using a fine probe crimping or soldering method through the molybdenum cathode sheet it contacts below, thus forming the test circuit. Note that, for ease of description of the commutation process, the gate current... The dashed line in the diagram represents the gate current, but it does not represent the actual flow of the gate current. The gate current does not converge in the p-base region, but rather in the gate interconnect metal layer region. Figure 8 I in a I is the anode current. k This represents the current flowing from the cathode.

[0104] The test device in the above test circuit can be a voltage detection device (e.g., oscilloscope 16) that measures a voltage value of V. gk The stray parameter of the cathode tube shell is R pk (Resistance) and L pk(Inductance), the stray parameter of the gate interconnect layer is R pg (Resistance) and L pg (Inductance), then the following electrical parameters should be included in the test circuit: the voltage of the J3 junction inside the cell. Stray resistance of the test circuit Stray inductance of the test circuit and the gate current at that cell Therefore, according to Kirchhoff's laws, we can obtain the following formula (2):

[0105] (2)

[0106] The voltage drop term related to stray inductance in the above formula The voltage drop term in formula (2) is composed of the induced electromotive force in the cell test circuit caused by the changing magnetic field generated during the turn-off process of the main current loop of the IGCT device. Its magnitude is mainly affected by the closed loop path of the cell test circuit, and the test circuit with a shorter path is less affected. In the test method of the present invention, since the test positions at the gate and cathode are very close and the test circuit is very short, the spatial magnetic field coupling effect generated by the main current loop during the turn-off process has little effect on the cell test circuit. Therefore, the voltage drop term caused by this term in formula (2) can be ignored. In addition, since the test circuit of the present invention passes through the through hole and does not pass through the shell, most of the shell stray parameters of the gate-cathode main circuit (such as the stray parameter R of the cathode shell) are not affected. pk and L pk The stray resistance in the test circuit of this invention is not included in the scope of the test circuit of this invention. The value is much smaller than the total stray resistance R of the casing. P , The value of represents a small proportion of the entire test circuit and can be ignored. Therefore, formula (2) can be simplified to formula (3):

[0107] (3)

[0108] Therefore, the voltage drop value obtained by this method can be considered as the J3 junction voltage of the cell at that location, and the obtained voltage waveform can effectively reflect the commutation process of the cell at that location during turn-off.

[0109] Specifically, the packaging structure may further include a voltage detection device, and the testing method in this embodiment includes:

[0110] The voltage of the PN junction between the gate and cathode of the first target cell is obtained by detecting the voltage between the first lead 13 and the second lead 14 using a voltage detection device.

[0111] The packaging structure of this embodiment enables testing and facilitates the analysis of cell commutation processes at different locations of power devices (such as IGCT devices).

[0112] Example 14

[0113] Based on Example 13, it is also possible to compare the commutation parameters of different cells of a power device (e.g., an IGCT device) at the same time. For example, in the IGCT device shown in Figure 3, the measurement voltage of the far gate electrode ring cell can be simultaneously measured using the method described above. (exist Figure 8 The measured voltage of the near-gate polarity ring cell (represented by V1). (exist Figure 8 V in Chinese n (This indicates that) because the cathode molybdenum sheets at both test locations share a common ground, the difference in J3 junction voltage between the far / near gate ring cells during turn-off can be analyzed. And the voltage drop values ​​applied to the far / near regions of the gate interconnect metal during the turn-off process are calculated:

[0114] (4)

[0115] Therefore, obtaining the above results can help analyze the commutation differences between different cells, providing an important reference for subsequent optimization of cell layout design and improvement of drive current strategy, thereby improving the overall performance and reliability of the device.

[0116] The testing method in this embodiment also includes:

[0117] The voltage between the third lead (not shown) and the fourth lead (not shown) is detected using a voltage detection device to obtain the voltage of the PN junction between the gate and cathode of the second target cell.

[0118] The voltage difference is obtained by calculating the voltage difference between the PN junction between the gate and cathode of the first target cell and the PN junction between the gate and cathode of the second target cell.

[0119] Of course, in one embodiment, the voltage of the PN junction between the gate and cathode of the first target cell, the voltage of the PN junction between the gate and cathode of the second target cell, and the voltage difference between the PN junction between the gate and cathode of the first target cell and the PN junction between the gate and cathode of the second target cell can also be determined simultaneously.

[0120] This embodiment provides a testing method and packaging structure for power devices (such as IGCT devices), which can obtain the commutation difference between far and near gate ring cells at the same time in a single test, thereby providing data support for subsequent cell structure optimization and drive design iteration of power devices (such as IGCT devices) (i.e., it is beneficial for analyzing the back-delay effect) and improving the overall reliability of the device.

[0121] Example 15

[0122] In the above embodiments, the power device is a power semiconductor device with a cellular structure, such as an IGCT device or an IGTO (Integrated Gate Turn-off Thyristor) device. The IGCT device includes, but is not limited to, reverse-resistance IGCT devices and asymmetric IGCT devices.

[0123] Specifically, taking IGCT devices as an example, the testing method and packaging structure proposed in this invention are not only applicable to... Figure 3a The asymmetric GCT chip with the middle gate ring structure shown in Figure 9 is also applicable to the asymmetric GCT chip with the outer gate ring structure shown in Figure 9. A schematic diagram of the testing method is shown below. Figure 10 As shown, the specific details can be found in the relevant content above (especially Examples Thirteen and Fourteen), and will not be repeated here.

[0124] Furthermore, the test methods and packaging structures described in this invention are not only applicable to the asymmetric GCT devices described above, but also to the test methods and packaging structures for reverse-conducting, reverse-resistive, and wave-based GCT devices, which are also within the scope of protection of this invention.

[0125] Preferably, the number of cells tested using this packaging structure can be expanded from two to multiple, allowing the acquisition of the gate-cathode J3 junction voltage of cells on different cathode rings, and enabling the comparison of the voltage difference between the PN junction between the gate and cathode of cells in any different cathode rings.

[0126] In summary, this invention creatively sets any cell in a power device (such as an IGCT device) as the first target cell and uses through-holes for wiring so that the test circuit does not pass through the cathode case. Therefore, without changing the current path during commutation, the influence of case stray parameters on the test results is reduced. This allows for direct measurement of cell-level commutation parameters during the power device's turn-off process, resulting in measurement results that are closer to the actual situation. The test method is simple and easy to implement, and the test results are stable and reliable.

[0127] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0128] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0129] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A packaging structure, characterized in that, The packaging structure includes a power device, which includes a power chip and a molybdenum cathode. and the cathode tube shell; And a gate drive unit for applying a reverse voltage between the gate ring and the cathode of the power chip during a turn-off test, the package structure comprising: A first through hole is disposed on the cathode molybdenum sheet and the first through hole overlaps at least with a portion of the gate region of the first target cell of the power chip; A second through hole is provided on the cathode tube shell, wherein the second through hole is in series with the first through hole; The first lead unit includes: a first lead end that contacts the gate of the first target cell, and a first lead, wherein a first end of the first lead is connected to the first lead end, and a second end of the first lead is led out through the first through hole and the second through hole; The second lead unit includes: a second lead end that contacts the cathode molybdenum sheet, and a second lead, wherein a first end of the second lead is connected to the second lead end, and a second end of the second lead is led out through the second through hole; A third through-hole is disposed on the cathode molybdenum sheet and the third through-hole overlaps at least with a portion of the gate region of the second target cell of the power chip, wherein the distance of the first target cell from the gate ring is different from the distance of the second target cell from the gate ring; A fourth through hole is provided on the cathode tube shell, wherein the fourth through hole is in series with the third through hole; The third lead unit includes: a third lead end that contacts the gate of the second target cell, and a third lead, wherein a first end of the third lead is connected to the third lead end, and a second end of the third lead is led out through the third through hole and the fourth through hole; The fourth lead unit includes: a fourth lead end, which contacts the cathode molybdenum sheet, and a fourth lead, wherein a first end of the fourth lead is connected to the fourth lead end, and a second end of the fourth lead is led out through the fourth through hole; The first lead groove is connected to the second through hole. The second end of the first lead wire is led out through the first through hole, the second through hole and the first lead wire groove, and the second end of the second lead wire is led out through the second through hole and the first lead wire groove; The second lead groove is connected to the fourth through hole. The second end of the third lead wire is led out through the third through hole, the fourth through hole and the second lead wire groove, and the second end of the fourth lead wire is led out through the fourth through hole and the second lead wire groove; The gate in the first target cell and the gate in the second target cell are located on the same radial direction of the power chip, and the first lead slot and the second lead slot are the same slot.

2. The packaging structure according to claim 1, characterized in that, The cathode of one of the first target cells and the second target cells is located on the cathode ring furthest from the gate ring, while the cathode of the other cell is located on the cathode ring closest to the gate ring.

3. The packaging structure according to claim 2, characterized in that, The radius of the first through hole is less than or equal to the radius of the second through hole, and the radius of the third through hole is less than or equal to the radius of the fourth through hole.

4. The packaging structure according to claim 3, characterized in that, The radius of the first through hole and the third through hole is 1-4 mm, and the radius of the second through hole and the fourth through hole is 2-6 mm.

5. The packaging structure according to claim 3, characterized in that, The center of the first through hole is aligned with the center of the second through hole, and the center of the third through hole is aligned with the center of the fourth through hole.

6. The packaging structure according to claim 1, characterized in that, The first lead end, the second lead end, the third lead end, and the fourth lead end are fine probes or spring probes.

7. The packaging structure according to claim 1, characterized in that, The first lead, the second lead, the third lead, and the fourth lead are twisted-pair shielded cables.

8. The packaging structure according to claim 1, characterized in that, The power device is an IGCT device or an IGTO device.

9. A testing method, characterized in that, The test method is applied to the packaging structure as described in any one of claims 1-8, and the test method includes: The voltage between the first lead and the second lead is detected using a voltage detection device to obtain the voltage of the PN junction between the gate and the cathode of the first target cell.

10. The test method according to claim 9, characterized in that, The testing method also includes: The voltage between the third lead and the fourth lead is detected using a voltage detection device to obtain the voltage of the PN junction between the gate and the cathode of the second target cell; The voltage difference is obtained by calculating the voltage difference between the PN junction between the gate and cathode of the first target cell and the PN junction between the gate and cathode of the second target cell.

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