A method of forming a MEMS sensor and a MEMS sensor

Abstract

The application discloses a forming method of a MEMS sensor and the MEMS sensor. The forming method comprises the following steps: providing a first wafer; forming a first insulating layer on the first wafer; providing a device wafer and bonding the device wafer with the first insulating layer; forming a through hole extending into the first wafer through the device wafer; filling polysilicon in the through hole to form an electrical connection structure; forming a sensing structure and a signal transmission structure which are independent of each other on the device wafer, and a projection of the through hole is located in a projection range of the signal transmission structure; providing a second wafer; bonding the sensing structure and the signal transmission structure with the second wafer; removing part of the first wafer on a side where the second wafer is located to expose the electrical connection structure in the through hole on the second wafer; and forming at least one signal leading-out structure on the second wafer. The application can improve the detection precision and stability of the MEMS sensor, reduce the manufacturing cost of the MEMS sensor, and is beneficial to batch production.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a method for forming a MEMS sensor and a MEMS sensor. Background Technology

[0002] As microelectromechanical systems (MEMS) and inertial sensors (such as accelerometers and gyroscopes) develop towards smaller package sizes and higher integration, in order to further reduce the size of MEMS sensors and improve integration, the substrate of traditional MEMS chips is usually replaced with an application-specific integrated circuit (ASIC) chip, thereby forming a highly integrated MEMS sensor chip.

[0003] For highly integrated MEMS sensor chips, existing technologies typically employ through-silicon vias (TSVs) on the electrically connected wafer, followed by metal filling within the TSVs to extract signals from the ASIC chip. However, this method suffers from a mismatch in the thermal expansion coefficients between the metal and silicon, which can easily generate significant stress within the chip, leading to increased zero-bias drift. Furthermore, due to limitations in the metal filling process, the via size is usually large to ensure filling quality, making further reduction difficult. This hinders the miniaturization and integration of MEMS sensors and results in complex fabrication processes and high manufacturing costs. Moreover, creating TSVs on the ASIC chip requires thinning the ASIC chip, which can increase electrode deformation, exacerbating the zero-bias problem and affecting the detection accuracy and stability of the MEMS sensor. Summary of the Invention

[0004] This application provides a method for forming a MEMS sensor and a MEMS sensor, which can improve the detection accuracy and stability of the MEMS sensor, reduce the manufacturing cost of the MEMS sensor, and facilitate mass production.

[0005] To achieve the above objectives, according to a first aspect of this application, a method for forming a MEMS sensor is provided, comprising:

[0006] A first wafer is provided, the first wafer having a first surface and a second surface disposed opposite to each other along the thickness direction.

[0007] A first insulating layer is formed on the first surface;

[0008] A device wafer is provided, and the device wafer is bonded to the first insulating layer;

[0009] At least one through-hole is formed, the through-hole comprising a first segment and a second segment connected to each other, the first segment penetrating the device wafer, the second segment extending into the first wafer but not penetrating the first wafer, and at least the wall of the second segment being covered with a second insulating layer.

[0010] Polysilicon is filled into the through-hole to form an electrical connection structure;

[0011] The device wafer is patterned to form a sensitive structure and a signal transmission structure that are independent of each other on the device wafer. The sensitive structure includes at least one movable part, and the movable part has a first gap with the first wafer. In the thickness direction, the projection of the via is located within the projection range of the signal transmission structure.

[0012] A second wafer is provided, on which metal wiring is laid; the side of the device wafer opposite to the first surface is bonded to the second wafer, so that the sensitive structure and the signal transmission structure are electrically connected to the second wafer respectively;

[0013] Remove a portion of the first wafer on the side containing the second surface to expose the electrical connection structure located within the via.

[0014] At least one signal lead-out structure is formed on the second surface, each signal lead-out structure corresponding to one of the electrical connection structures and electrically connected to the corresponding electrical connection structure.

[0015] In some embodiments, the specific steps of forming at least one through-hole, the through-hole comprising a first segment and a second segment connected to each other, the first segment penetrating the device wafer, the second segment extending into the first wafer but not penetrating the first wafer, and at least the wall of the second segment being covered with a second insulating layer include:

[0016] Before forming the first insulating layer, at least one second hole segment is etched on the first side of the first wafer, the second hole segment extending into the interior of the first wafer along the thickness direction but not penetrating the first wafer;

[0017] When the first insulating layer is formed, the second insulating layer covering the hole wall of the second hole segment is formed simultaneously;

[0018] After the device wafer is bonded to the first insulating layer, a first hole segment is etched on the device wafer to penetrate the device wafer. The first hole segment corresponds to a second hole segment. In the thickness direction, the projection of the first hole segment and the projection of the corresponding second hole segment at least partially overlap, so that the first hole segment and the second hole segment are connected to form the through hole.

[0019] In some embodiments, the specific steps of filling the via with polysilicon to form an electrical connection structure include:

[0020] A polycrystalline silicon seed layer is deposited, the polycrystalline silicon seed layer covering the side surface of the device wafer opposite to the first wafer and the inner wall of the via;

[0021] Polycrystalline silicon is epitaxially grown on the polycrystalline silicon seed layer until the polycrystalline silicon fills the vias, forming an initial polycrystalline silicon layer.

[0022] The initial polysilicon layer is planarized until the surface of the device wafer facing away from the first wafer is exposed, and an electrical connection structure is formed within the via.

[0023] In some embodiments, the steps of forming at least one through-hole, the through-hole comprising a first segment and a second segment connected in series, the first segment penetrating the device wafer, and the second segment extending into the first wafer but not penetrating it, wherein at least the wall of the second segment is covered with a second insulating layer, include:

[0024] After the device wafer is bonded to the first insulating layer, etching is performed from the side of the device wafer facing away from the first wafer toward the first wafer to form a first hole segment penetrating the device wafer and a second hole segment communicating with the first hole segment and extending into the first wafer.

[0025] In some embodiments, the specific step of forming at least one through hole further includes:

[0026] A second insulating layer is formed on the wall of the first aperture segment, the wall of the second aperture segment, and the surface of the device wafer facing away from the first wafer.

[0027] In some embodiments, the specific steps of filling the via with polysilicon to form an electrical connection structure include:

[0028] A polycrystalline silicon seed layer is deposited, the polycrystalline silicon seed layer covering the surface of the second insulating layer;

[0029] Polycrystalline silicon is epitaxially grown on the polycrystalline silicon seed layer until the polycrystalline silicon fills the vias, forming an initial polycrystalline silicon layer.

[0030] The initial polysilicon layer is planarized to remove the second insulating layer and the initial polysilicon layer covering the surface of the device wafer facing away from the first wafer, until the surface of the device wafer facing away from the first wafer is exposed, and the polysilicon located in the via forms the electrical connection structure.

[0031] In some embodiments, a first bonding layer is deposited on the side of the second wafer facing the first wafer; the method for forming the MEMS sensor further includes:

[0032] Before patterning the device wafer, a second bonding layer is formed on the side of the device wafer opposite to the first wafer;

[0033] The specific steps of bonding the side of the device wafer away from the first surface to the second wafer include:

[0034] The first bonding layer and the second bonding layer are bonded together so that the sensitive structure and the signal transmission structure are electrically connected to the second wafer, respectively.

[0035] In some embodiments, a second bonding layer is formed on the side surface of both the sensitive structure and the signal transmission structure facing away from the first wafer, and the second bonding layer on the sensitive structure and the second bonding layer on the signal transmission structure are independent of each other.

[0036] In some embodiments, when the walls of both the first and second aperture segments are covered with the second insulating layer, the projection of the second bonding layer on the signal transmission structure at least partially overlaps with the projection of the electrical connection structure in the thickness direction.

[0037] In some embodiments, when the wall of the second hole segment is covered with the second insulating layer and the wall of the first hole segment is not covered with the second insulating layer, the projection of the second bonding layer of the signal transmission structure and the projection of the electrical connection structure do not overlap in the thickness direction.

[0038] In some embodiments, it also includes:

[0039] Before forming the first insulating layer on the first surface, at least one first groove is formed on the first wafer;

[0040] After forming a first insulating layer on the first surface, the first insulating layer also covers the inner wall of each of the first grooves;

[0041] Wherein, the first groove corresponds to at least one of the movable parts, and in the thickness direction, the projection of the movable part is located within the projection range of the corresponding first groove, and the first groove constitutes the first gap.

[0042] In some embodiments, the specific steps of forming at least one signal lead-out structure on the second surface, each signal lead-out structure corresponding to one of the electrical connection structures, and being electrically connected to the corresponding electrical connection structure, include:

[0043] A dielectric layer is formed, which covers the second surface. A second groove is formed on the dielectric layer, and each second groove corresponds to a through hole. The electrical connection structure corresponding to the through hole is exposed in the second groove.

[0044] A redistribution layer is formed, which covers the dielectric layer and the electrical connection structure exposed in the second groove;

[0045] A passivation layer is formed, which covers the redistribution layer. The passivation layer has multiple openings, and the redistribution layer is exposed in the openings.

[0046] A signal lead-out structure is formed in the opening so that the signal lead-out structure is electrically connected to the corresponding electrical connection structure through the redistribution layer.

[0047] According to a second aspect of this application, a MEMS sensor is provided, comprising:

[0048] The first wafer has a first surface and a second surface disposed opposite to each other along the thickness direction;

[0049] A first insulating layer covers the first surface;

[0050] The device wafer includes a sensing structure and a signal transmission structure that are independent of each other. Both the sensing structure and the signal transmission structure are bonded to the first insulating layer on the side facing the first wafer. The sensing structure includes at least one movable part, and the movable part has a first gap with the first wafer.

[0051] The second wafer has metal wiring laid on it, and the side of the second wafer facing the first wafer is bonded to the sensitive structure and the signal transmission structure to be electrically connected to the sensitive structure and the signal transmission structure respectively.

[0052] At least one via includes a first via segment and a second via segment connected to each other, the first via segment penetrating the signal transmission structure, the second via segment extending into and through the first wafer, and at least the wall of the second via segment is covered with a second insulating layer.

[0053] An electrical connection structure is filled within the through-hole;

[0054] At least one signal lead-out structure is located on the second surface, the signal lead-out structure corresponding to one of the through holes and connected to the electrical connection structure within the corresponding through hole.

[0055] In some embodiments, within the first aperture segment, the electrical connection structure is in direct contact with and electrically connected to the device wafer.

[0056] In some embodiments, a first bonding layer is deposited on the side of the second wafer facing the first wafer, and a second bonding layer is formed on the side of the sensitive structure and the signal transmission structure away from the first wafer. The corresponding first bonding layer and the second bonding layer are connected, and in the thickness direction, the projection of the second bonding layer on the signal transmission structure does not overlap with the projection of the electrical connection structure.

[0057] In some embodiments, the second insulating layer also covers the hole wall of the first hole segment.

[0058] In some embodiments, a first bonding layer is deposited on the side of the second wafer facing the first wafer, and a second bonding layer is formed on the side of the sensitive structure and the signal transmission structure away from the first wafer. The corresponding first bonding layer and the second bonding layer are connected. In the thickness direction, the projection of the second bonding layer on the signal transmission structure at least partially overlaps with the projection of the electrical connection structure.

[0059] This application forms vias after bonding a first wafer to a device wafer, and fills the vias with polysilicon to form an electrical connection structure. Subsequently, the device wafer is patterned to form independent sensing and signal transmission structures, which are then bonded to a second wafer. The first wafer is also thinned to form a signal lead-out structure on its second surface, thereby effectively leading internal electrical signals to external connections. Because this embodiment uses polysilicon instead of metal to form the electrical connection structure within the vias, the polysilicon material is more compatible with the silicon substrate of both the first and device wafers in terms of thermal expansion coefficients. This significantly reduces thermal stress caused by differences in material thermal expansion during device fabrication and operation, effectively reducing stress concentration around the vias and its transmission to the sensing structure. This reduces stress bias in the sensing structure, which is beneficial for minimizing zero-bias drift in MEMS sensors and improving detection accuracy and long-term stability. Meanwhile, since this application does not require a large-sized via structure specifically for metal filling, the area occupied by the via can be reduced, which is more conducive to chip area reduction and promotes the development of MEMS sensors towards miniaturization and high integration, thereby reducing manufacturing costs. In addition, this application does not require thinning of the second wafer to form an electrical connection structure, thus avoiding the problem of increased zero-bias drift caused by deformation of the metal wiring and electrode structure on the second wafer after thinning, which is further conducive to improving the stability and accuracy of MEMS sensor output.

[0060] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0062] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0063] Figure 1 This is a schematic flowchart of a method for forming a MEMS sensor disclosed in an embodiment of this application;

[0064] Figures 2 to 17 This is a schematic diagram of the process steps of a MEMS sensor disclosed in an embodiment of this application;

[0065] Figures 18 to 28 This is a schematic diagram of the process steps of another MEMS sensor disclosed in the embodiments of this application.

[0066] Explanation of reference numerals in the attached figures:

[0067] 10. First wafer; 101. First side; 102. Second side; 103. First groove; 104. First insulating layer; 105. Mask layer; 1051. Notch;

[0068] 20. Device wafer; 201. Sensitive structure; 2011. Movable part; 2012. Fixed part; 202. Signal transmission structure; 203. Bonding boss; 204. Second bonding layer; 205. Sealing structure;

[0069] 30. Through hole; 301. First hole section; 302. Second hole section; 303. Second insulating layer;

[0070] 401. Polycrystalline silicon seed layer; 402. Initial polycrystalline silicon layer; 403. Electrical connection structure;

[0071] 50. Second wafer; 501. Metal wiring; 502. First bonding layer; 503. Substrate;

[0072] 601, Dielectric layer; 6011, Second groove; 602, Rerouting layer; 603, Passivation layer; 6031, Opening; 604, Signal lead-out structure; 6041, Metal layer; 6042, Solder ball. Detailed Implementation

[0073] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0074] As microelectromechanical systems (MEMS) and inertial sensors (such as accelerometers and gyroscopes) develop towards smaller package sizes and higher integration, in order to further reduce the size of MEMS sensors and improve integration, the substrate of traditional MEMS chips is usually replaced with an application-specific integrated circuit (ASIC) chip, thereby forming a highly integrated MEMS sensor chip.

[0075] For highly integrated MEMS sensor chips, the existing technology described in the background typically employs through-silicon vias (TSVs) on the electrically connected wafer, then fills the TSVs with metal to extract the signals from the ASIC chip. However, this method, due to the mismatch in thermal expansion coefficients between the metal and silicon, easily generates significant stress within the chip, leading to increased zero-bias drift. Specifically, the thermal expansion or contraction of metal materials (such as copper and aluminum) during temperature changes is generally greater than that of silicon. When the chip undergoes temperature changes during packaging processes or in the actual operating environment, relative deformation occurs between the metal-filled structure within the via and the surrounding silicon structure, introducing thermal stress into the area around the via. This thermal stress propagates through the silicon substrate into the device and acts on the sensitive structure region. Since the sensitive structure of MEMS sensors typically includes microstructures such as cantilever beams and mass blocks, which are highly sensitive to external stresses, the stress caused by the aforementioned thermal expansion difference easily leads to minute deformations or stress biases in the sensitive structure, thereby altering its initial equilibrium state or electrical response characteristics, causing the output signal of the sensitive structure to drift and increasing zero-bias drift. Meanwhile, due to limitations in the metal filling process, the through-hole size is usually large in order to ensure the filling quality of the metal filling, and it is difficult to further reduce it. Therefore, it is not conducive to the miniaturization and integration of MEMS sensors, and the fabrication process is complex and the manufacturing cost is high.

[0076] Furthermore, since creating a TSV on an ASIC chip requires thinning the ASIC chip, it can easily lead to increased electrode deformation on the ASIC chip, making the zero bias problem more serious and further affecting the detection accuracy and stability of the MEMS sensor.

[0077] Therefore, in order to improve the detection accuracy and stability of MEMS sensors while reducing manufacturing costs and facilitating mass production, referencing Figure 1 This application discloses a method for forming a MEMS sensor, which includes:

[0078] S100: Provide a first wafer, the first wafer having a first surface and a second surface disposed opposite to each other along the thickness direction;

[0079] S200: A first insulating layer is formed on the first surface;

[0080] S300: Provides a device wafer and bonds the device wafer to the first insulating layer;

[0081] S400: Form at least one through hole, the through hole including a first hole segment and a second hole segment connected to each other, the first hole segment penetrating the device wafer, the second hole segment extending into the first wafer but not penetrating the first wafer, and at least the hole wall of the second hole segment being covered with a second insulating layer.

[0082] S500: Polysilicon is filled into the through-hole to form an electrical connection structure;

[0083] S600: The device wafer is patterned to form a sensitive structure and a signal transmission structure that are independent of each other on the device wafer. The sensitive structure includes at least one movable part, and there is a first gap between the movable part and the first wafer. In the thickness direction, the projection of the through hole is located within the projection range of the signal transmission structure.

[0084] S700: Provides a second wafer on which metal wiring is laid; the side of the device wafer facing away from the first surface is bonded to the second wafer so that the sensitive structure and the signal transmission structure are electrically connected to the second wafer respectively;

[0085] S800: Remove a portion of the first wafer on the side where the second face is located to expose the electrical connection structure located in the through-hole;

[0086] S900: At least one signal lead-out structure is formed on the second surface, each signal lead-out structure corresponding to an electrical connection structure and electrically connected to the corresponding electrical connection structure.

[0087] In this embodiment, after bonding the first wafer 10 and the device wafer 20, a via 30 is formed, and polysilicon is filled in the via 30 to form an electrical connection structure 403. Subsequently, the device wafer 20 is patterned to form an independent sensitive structure 201 and a signal transmission structure 202, and the sensitive structure 201 and the signal transmission structure 202 are bonded to the second wafer 50. The first wafer 10 is also thinned to form a signal lead-out structure 604 on the second surface 102 of the first wafer 10, thereby realizing the effective lead-out of the internal electrical signals of the chip to the external connection terminal. Since the embodiment of this application uses polycrystalline silicon instead of metal material to form the electrical connection structure 403 in the through hole 30, the polycrystalline silicon material is more compatible with the silicon substrate of the first wafer 10 and the silicon substrate of the device wafer 20 in terms of thermal expansion coefficient. Therefore, the thermal stress caused by the difference in thermal expansion of materials can be significantly reduced during device fabrication and operation. This effectively reduces the concentration of stress in the area around the through hole and the transmission to the sensitive structure 201, thereby reducing the stress bias of the sensitive structure 201. This is beneficial to reduce the zero-bias drift of the MEMS sensor and improve the detection accuracy and long-term stability.

[0088] Compared to traditional metal-filling processes, polysilicon filling offers better adaptability to the shape and aspect ratio of vias 30, reducing the likelihood of common issues such as voids, gaps, or insufficient filling. This improves the conductivity reliability of the electrical connection structure 403 and enhances product consistency. Furthermore, since this embodiment does not require a large-sized via structure specifically designed for metal filling, the area occupied by the vias 30 is reduced, further facilitating chip area reduction and promoting the miniaturization and high integration of MEMS sensors.

[0089] Furthermore, since the second wafer 50 integrates metal wiring 501, a first bonding layer 502, etc., if vias 30 are formed on the side of the second wafer 50 and thinning is performed, the overall mechanical strength of the second wafer 50 will decrease. Local areas will be more prone to warping or stress concentration during packaging, thermal cycling, or operation, resulting in slight deformation of the metal wiring 501 and the first bonding layer 502. This deformation will further cause changes in the positional relationship and parasitic parameters of the metal wiring 501, causing the MEMS sensor to generate additional output deviation signals even without external input, thus exacerbating zero-bias drift. In this embodiment, there is no need for vias 30 on the second wafer 50, nor is there a need to thin the second wafer 50 to form the electrical connection structure 403. This avoids the problem of increased zero-bias drift caused by deformation of the metal wiring 501 and electrode structure after thinning of the second wafer 50, further improving the stability and accuracy of the MEMS sensor output. At the same time, this approach also helps to simplify the wiring design of the second wafer 50, improve the overall integration, and reduce design complexity and manufacturing costs.

[0090] S100: A first wafer 10 is provided, the first wafer 10 having a first surface 101 and a second surface 102 disposed opposite to each other along the thickness direction.

[0091] Reference Figure 2 In some embodiments, the first wafer 10 is made of silicon.

[0092] S200: A first insulating layer 104 is formed on the first surface 101.

[0093] Reference Figure 3 In some embodiments, the first insulating layer 104 is made of silicon oxide. In some embodiments, the first insulating layer 104 is formed by a thermal oxidation process. In other embodiments, the first insulating layer 104 is formed by a chemical vapor deposition process. The first insulating layer 104 covers the first surface 101 to form an insulating interface on the side of the first wafer 10 facing the device wafer 20.

[0094] S300: Provide device wafer 20 and bond device wafer 20 to first insulating layer 104.

[0095] Reference Figure 4 In some embodiments, the device wafer 20 is made of silicon. In some embodiments, the device wafer 20 is bonded to the side of the first insulating layer 104 opposite to the first wafer 10 by anodic bonding. In some embodiments, after the device wafer 20 is bonded to the first wafer 10, the device wafer 20 is thinned to reduce its thickness to 10 micrometers to 70 micrometers.

[0096] S400: Form at least one through hole 30, the through hole 30 including a first hole segment 301 and a second hole segment 302 connected to each other, the first hole segment 301 penetrates the device wafer 20, the second hole segment 302 extends into the first wafer 10 but does not penetrate the first wafer 10, and at least the hole wall of the second hole segment 302 is covered with a second insulating layer 303.

[0097] Reference Figure 5 In some embodiments, step S400 specifically includes the following steps:

[0098] After the device wafer 20 is bonded to the first insulating layer 104, etching is performed from the side of the device wafer 20 away from the first wafer 10 toward the first wafer 10 to form a first hole segment 301 that penetrates the device wafer 20 and a second hole segment 302 that communicates with the first hole segment 301 and extends into the first wafer 10.

[0099] Since the first insulating layer 104 covers the surface of the first wafer 10, the first hole segment 301 also penetrates the first insulating layer 104.

[0100] In some embodiments, the depth of the second hole segment 302 is greater than or equal to 80 μm, wherein the depth of the second hole segment 302 refers to the extension depth of the second hole segment 302 along the thickness direction within the first wafer 10.

[0101] It should be noted that, in some embodiments, the number of vias 30 is set according to the number of electrical signals to be brought out from the second wafer 50 side.

[0102] Reference Figure 6 In some embodiments, step S400 further includes the following steps:

[0103] A second insulating layer 303 is formed on the wall of the first hole segment 301, the wall of the second hole segment 302, and the surface of the device wafer 20 facing away from the first wafer 10.

[0104] In some embodiments, the second insulating layer 303 is made of silicon oxide. In some embodiments, the second insulating layer 303 is formed by thermal oxidation of the surface of the device wafer 20 facing away from the first wafer 10, the wall of the first via 301, and the wall of the second via 302. In other embodiments, the second insulating layer 303 is formed by deposition on the surface of the device wafer 20 facing away from the first wafer 10, the wall of the first via 301, and the wall of the second via 302.

[0105] After the second insulating layer 303 covers the hole wall of the first hole segment 301 and the hole wall of the second hole segment 302, the electrical connection structure 403 subsequently formed in the through hole 30 can be mutually insulated and isolated from the silicon substrate of the first wafer 10 and the device wafer 20, thereby enabling the electrical connection structure 403 to transmit signals as an independent conductive path.

[0106] S500: Polysilicon is filled in the via 30 to form an electrical connection structure 403.

[0107] In some embodiments, step S500 includes the following specific steps:

[0108] Reference Figure 7 A polycrystalline silicon seed layer 401 is deposited, which covers the surface of the second insulating layer 303.

[0109] Reference Figure 8 Polycrystalline silicon is epitaxially grown on the polycrystalline silicon seed layer 401 until the polycrystalline silicon fills the vias 30, forming the initial polycrystalline silicon layer 402.

[0110] Reference Figure 9The initial polysilicon layer 402 is planarized to remove the second insulating layer 303 and the initial polysilicon layer 402 covering the surface of the device wafer 20 away from the first wafer 10, until the surface of the device wafer 20 away from the first wafer 10 is exposed, and the polysilicon in the via 30 forms an electrical connection structure 403.

[0111] In this embodiment, a polysilicon seed layer 401 covers a second insulating layer 303 on the surface of the device wafer 20 opposite to the first wafer 10, and also covers a second insulating layer 303 on the surfaces of the first via segment 301 and the second via segment 302. By continuously covering the surface of the device wafer 20 and the via wall 30 with the polysilicon seed layer 401, the subsequently deposited polysilicon can be formed more uniformly and continuously along the surface of the polysilicon seed layer 401 and gradually thicken. This is more conducive to the synchronous filling of various positions within the via 30, reducing the risk of insufficient filling, voids in the via, or localized narrowing, and is beneficial to the formation of a continuous and complete electrical connection structure 403.

[0112] In some embodiments, the initial polysilicon layer 402 is planarized using the surface of the device wafer 20 facing away from the first wafer 10 as the stop surface for planarization. In other words, the initial polysilicon layer 402 is planarized until the surface of the device wafer 20 facing away from the first wafer 10 is exposed.

[0113] S600: The device wafer 20 is patterned to form a sensitive structure 201 and a signal transmission structure 202 that are independent of each other on the device wafer 20. The sensitive structure 201 includes at least one movable part 2011, and the movable part 2011 has a first gap with the first wafer 10. In the thickness direction, the projection of the through hole 30 is located within the projection range of the signal transmission structure 202.

[0114] Reference Figure 11 The sensing structure 201 and the signal transmission structure 202 are located on the same layer, and the electrical connection structure 403 is located in the signal transmission structure 202. The sensing structure 201 includes a movable part 2011 and a fixed part 2012. The movable part 2011 is used to generate a corresponding detection signal under the action of external inertia. Part of the fixed part 2012 is electrically connected to the second wafer 50 through subsequent bonding to transmit the detected electrical signal to the second wafer 50 for processing. The signal transmission structure 202 is electrically connected to the second wafer 50 through subsequent bonding. The electrical connection structure 403 located in the signal transmission structure 202 is exposed after the first wafer 10 is subsequently thinned, thereby further transmitting the electrical signal from the second wafer 50 side to the outside.

[0115] By designing the sensitive structure 201 and the signal transmission structure 202 as independent structures, inertial detection and signal extraction functions can be realized simultaneously within the same device layer, which helps to reduce signal coupling interference and improve device integration.

[0116] Reference Figure 11 After patterning the device wafer 20, an annular sealing structure 205 is formed on the device wafer 20. The sensitive structure 201 and the signal transmission structure 202 are located within the area surrounded by the annular sealing structure 205. The annular sealing structure 205 can be used to achieve sealing between the first wafer 10 and the device wafer 20, and provide an outer sealing area for sealing between the subsequent device wafer 20 and the second wafer 50, thereby improving the sealing performance and overall reliability of the device.

[0117] It is worth mentioning that, in the embodiments of this application, reference is made to... Figure 1 The method for forming a MEMS sensor further includes: before forming a first insulating layer 104 on the first surface 101, forming at least one first groove 103 on the first wafer 10; after forming the first insulating layer 104 on the first surface 101, the first insulating layer 104 also covers the inner wall of each first groove 103; wherein the first groove 103 corresponds to at least one movable part 2011, and in the thickness direction, the projection of the movable part 2011 is located within the projection range of the corresponding first groove 103, and the first groove 103 constitutes a first gap.

[0118] In other embodiments, the first gap between the movable part 2011 and the first wafer 10 is formed by removing part of the first insulating layer 104 between the device wafer 20 and the first wafer 10.

[0119] Reference Figure 10 In some embodiments, before the device wafer 20 is patterned, the method for forming a MEMS sensor further includes forming a second bonding layer 204 on the side of the device wafer 20 opposite to the first wafer 10.

[0120] In some embodiments, the specific steps for forming the second bonding layer 204 include: firstly forming an initial second bonding layer on the surface of the device wafer 20 opposite to the first wafer 10, the initial second bonding layer covering the surface of the device wafer 20 opposite to the first wafer 10; then patterning the initial second bonding layer to form a plurality of independent second bonding layers 204. In some embodiments, the material of the second bonding layer 204 includes doped germanium.

[0121] In some embodiments, the method for forming a MEMS sensor further includes, prior to forming the second bonding layer 204:

[0122] The device wafer 20 is etched on one side of the surface opposite to the first wafer 10 to form a plurality of bonding bumps 203 on the side of the device wafer 20 opposite to the first wafer 10; after the initial second bonding layer is patterned, the second bonding layer 204 formed is located at least on the side of the bonding bumps 203 opposite to the first wafer 10.

[0123] It should be noted that after the subsequent patterning processing of the device wafer 20 to form independent sensing structures 201, signal transmission structures 202, and sealing structures 205, bonding bumps 203 are provided on the surface of the signal transmission structure 202 and the sealing structure 205 facing away from the first wafer 10. On the signal transmission structure 202, the side of the electrical connection structure 403 facing away from the first wafer 10 is flush with the side of the bonding bump 203 facing away from the first wafer 10. The sensing structure 201 includes a movable part 2011 and a fixed part 2012. At least a portion of the fixed part 2012 has bonding bumps 203 on the surface of the side facing away from the first wafer 10, and each bonding bump 203 has a second bonding layer 204. The fixed part 2012 with bonding bumps 203 is used to transmit the electrical signal generated by the sensing structure 201 to the second wafer 50.

[0124] In some embodiments, the second bonding layer 204 wraps around the bonding bump 203, while in other embodiments, the second bonding layer 204 covers only the side surface of the bonding bump 203 facing away from the device wafer 20.

[0125] It should be noted that by forming bonding protrusions 203 and / or forming a second bonding layer 204, a gap can be formed between the movable part 2011 and the second wafer 50 after the device wafer 20 and the second wafer 50 are bonded, which is beneficial for the movement of the sensitive structure 201 during the detection process. In some embodiments, the height of the bonding protrusions 203 ranges from 1.5 μm to 3 μm. All bonding protrusions 203 have the same height. The height of the bonding protrusions 203 refers to the distance from the side surface of the bonding protrusion 203 facing away from the first wafer 10 to the side surface of the device wafer 20 facing away from the first wafer 10. When the bonding protrusions 203 on the fixed part 2012 are bonded to the second wafer 50, a deformation space of 1.5 μm to 3 μm can be formed between the second wafer 50 and the movable part 2011, thereby providing clearance space for the deformation and movement of the movable part 2011, facilitating the movement of the movable part 2011.

[0126] S700: Provide a second wafer 50, on which metal wiring 501 is laid; bond the side of the device wafer 20 away from the first surface 101 to the second wafer 50 so that the sensitive structure 201 and the signal transmission structure 202 are electrically connected to the second wafer 50 respectively.

[0127] Reference Figure 12In some embodiments, the second wafer 50 includes a substrate 503, metal wiring 501 disposed on the substrate 503, and a first bonding layer 502 formed on the side of the substrate 503 facing the first wafer 10. The first bonding layer 502 at least partially covers the metal wiring 501 and is electrically connected to the metal wiring 501. In some embodiments, the substrate 503 of the second wafer 50 is also made of silicon. In some embodiments, the first bonding layer 502 is made of aluminum. In some embodiments, the metal wiring 501 is made of aluminum or tungsten.

[0128] In some embodiments, step S700 includes the following specific steps:

[0129] The first bonding layer 502 and the second bonding layer 204 are bonded together so that the sensitive structure 201 and the signal transmission structure 202 are electrically connected to the second wafer 50, respectively.

[0130] The first bonding layer 502 and the second bonding layer 204 are connected by aluminum-germanium eutectic bonding. This method can achieve reliable bonding between the device wafer 20 and the second wafer 50 while forming an electrical connection path, thereby simultaneously realizing inter-wafer signal interconnection and wafer-level packaging.

[0131] In some embodiments, in the thickness direction, the projection of the second bonding layer 204 on the signal transmission structure 202 at least partially overlaps with the projection of the electrical connection structure 403. In other words, the second bonding layer 204 on the signal transmission structure 202 at least partially covers the electrical connection structure 403. With this configuration, the electrical signal output from the second wafer 50 is transmitted through the first bonding layer 502 to the second bonding layer 204, and then directly transmitted through the second bonding layer 204 to the electrical connection structure 403, so as to be output to an external device through the electrical connection structure 403.

[0132] S800: Remove a portion of the first wafer 10 on the side where the second surface 102 is located to expose the electrical connection structure 403 located within the via 30.

[0133] Reference Figure 13 In some embodiments, the first wafer 10 is thinned from the side where the second surface 102 of the first wafer 10 is located. The thinning process can employ grinding, polishing, etching, or a combination of the above processes. Specifically, in some embodiments, a portion of the thickness of the first wafer 10 is first removed by grinding, and then fine thinning is performed by polishing or etching until the electrical connection structure 403 located in the via 30 is exposed on the second surface 102.

[0134] S900: At least one signal lead-out structure 604 is formed on the second surface 102, each signal lead-out structure 604 corresponding to an electrical connection structure 403 and electrically connected to the corresponding electrical connection structure 403.

[0135] In some embodiments, step S900 includes the following specific steps:

[0136] Reference Figure 14 A dielectric layer 601 is formed, which covers the second surface 102. A second groove 6011 is formed on the dielectric layer 601, and each second groove 6011 corresponds to a through hole 30. The electrical connection structure 403 in the corresponding through hole 30 is exposed in the second groove 6011. In some embodiments, the material of the dielectric layer 601 includes silicon oxide.

[0137] Reference Figure 15 A redistribution layer 602 is formed, which covers the dielectric layer 601 and the electrical connection structure 403 exposed in the second groove 6011.

[0138] Reference Figure 16 A passivation layer 603 is formed, which covers the redistribution layer 602. The passivation layer 603 has a plurality of openings 6031, through which the redistribution layer 602 is exposed. In some embodiments, the material of the passivation layer 603 includes silicon oxide.

[0139] Reference Figure 17 A signal lead-out structure 604 is formed in the opening 6031 so that the signal lead-out structure 604 is electrically connected to the corresponding electrical connection structure 403 through the redistribution layer 602.

[0140] In some embodiments, the signal lead-out structure 604 includes a metal layer 6041 and solder balls 6042. The metal layer 6041 covers the redistribution layer 602 exposed in the opening 6031, and the solder balls 6042 are located on the metal layer 6041. At least one solder ball 6042 is formed above each opening 6031. In some embodiments, the solder ball 6042 is made of tin.

[0141] It is worth mentioning that, in this embodiment, the number of vias 30 can be set according to the number of electrical signals to be brought out from the second wafer 50 side. Figures 12 to 16This diagram only shows a partial schematic of the formation process of the signal lead-out structure 604. The multiple signal lead-out structures 604 adjacent to a via 30 are shown for illustrative purposes only and do not represent that multiple solder balls 6042 correspond to the same via 30. In some embodiments, each signal lead-out structure 604 is electrically connected to an electrical connection structure 403 within a via 30; a single signal lead-out structure 604 cannot be electrically connected to multiple electrical connection structures 403 within multiple vias 30. When multiple vias 30 are provided, the electrical connection structure 403 within each via 30 is electrically connected to at least one corresponding signal lead-out structure 604 through a corresponding redistribution layer 602, and each signal lead-out structure 604 includes a metal layer 6041 and solder balls 6042 corresponding to that via 30.

[0142] In another method for forming a MEMS sensor disclosed in this application embodiment, step S400 specifically includes the following steps:

[0143] Reference Figure 19 Before forming the first insulating layer 104, at least one second hole segment 302 is etched on the first surface 101 of the first wafer 10. The second hole segment 302 extends into the first wafer 10 along the thickness direction but does not penetrate the first wafer 10.

[0144] Reference Figure 20 When the first insulating layer 104 is formed, a second insulating layer 303 covering the hole wall of the second hole segment 302 is formed simultaneously.

[0145] Reference Figure 21 , Figure 22 After the device wafer 20 is bonded to the first insulating layer 104, a first hole segment 301 is etched on the device wafer 20 to form a through-hole segment 301. The first hole segment 301 corresponds to a second hole segment 302. In the thickness direction, the projection of the first hole segment 301 and the projection of the corresponding second hole segment 302 at least partially overlap, so that the first hole segment 301 and the second hole segment 302 are connected to form a through-hole 30.

[0146] In some embodiments, the specific steps of etching at least one second hole segment 302 on the first surface 101 of the first wafer 10 before forming the first insulating layer 104 include:

[0147] Reference Figure 18First, a mask layer 105 is formed on the first surface 101 of the first wafer 10. The mask layer 105 covers the first surface 101 and each first groove 103 to protect the corresponding area of ​​the first groove 103. Then, the mask layer 105 is patterned to form multiple notches 1051. Then, the patterned mask layer 105 is used as an etching mask to etch the first wafer 10 at the position corresponding to the notches 1051, thereby forming a second hole segment 302 on the first surface 101.

[0148] In some embodiments, the second aperture segment 302 extends into the first wafer 10 along the thickness direction of the first wafer 10, and the aperture depth of the second aperture segment 302 is greater than or equal to 80 micrometers. After the second aperture segment 302 is formed, the mask layer 105 is removed.

[0149] In some embodiments, the mask layer 105 is made of silicon oxide. The mask layer 105 can be formed by a thermal oxidation process; in other embodiments, the mask layer 105 can also be formed by a chemical vapor deposition process.

[0150] Reference Figure 20 After the second hole segment 302 is formed, a first insulating layer 104 is formed covering the first surface 101 and each first groove 103, and a second insulating layer 303 is simultaneously formed covering the hole wall of the second hole segment 302. The first insulating layer 104 and the second insulating layer 303 are integrally formed, both of which are silicon oxide, and are formed by the same process. In some embodiments, the first insulating layer 104 and the second insulating layer 303 are formed by a thermal oxidation process; in other embodiments, the first insulating layer 104 and the second insulating layer 303 are formed by a chemical vapor deposition process.

[0151] In some embodiments, after etching the second via 302, the mask layer 105, which serves as the etching mask, is removed first, and then the first insulating layer 104 and the second insulating layer 303 are reformed. This is because the aforementioned mask layer 105 is mainly used for patterned etching, and its surface flatness is usually affected after the etching process. Furthermore, the oxide layer covering the first surface 101 subsequently serves as the bonding interface between the first wafer 10 and the device wafer 20, thus requiring high surface flatness. By reforming the first insulating layer 104 and the second insulating layer 303, a flatter insulating layer surface can be obtained, thereby improving subsequent bonding effects and bonding reliability.

[0152] Furthermore, in this embodiment, by etching the second via segment 302 and the first via segment 301 in two separate etching operations, the etching process can be optimized based on the material characteristics, thickness, and target hole depth of the first wafer 10 and the device wafer 20, respectively. This helps reduce the process difficulty of a single deep etching operation and improves the control over the hole diameter and shape of each via segment. Compared to forming a through-hole 30 that penetrates the device wafer 20 and extends into the first wafer 10 in a single etching operation, two-stage etching is more conducive to achieving a smaller hole diameter via design, thereby reducing the area occupied by the through-hole 30 and facilitating the miniaturization and high integration of the device.

[0153] In some embodiments, step S500 includes the following specific steps:

[0154] Reference Figure 23 A polycrystalline silicon seed layer 401 is deposited, which covers the surface of the device wafer 20 away from the first wafer 10 and the inner wall of the via 30.

[0155] In the first segment 301 of the via 30, the polysilicon seed layer 401 directly covers the surface of the hole wall of the first segment 301; in the second segment 302 of the via 30, since the hole wall of the second segment 302 is covered by the second insulating layer 303, the polysilicon seed layer 401 covers the surface of the second insulating layer 303, thereby insulating and isolating the subsequently formed electrical connection structure 403 from the first wafer 10.

[0156] Reference Figure 24 Polycrystalline silicon is epitaxially grown on the polycrystalline silicon seed layer 401 until the polycrystalline silicon fills the vias 30, forming the initial polycrystalline silicon layer 402.

[0157] Reference Figure 25 The initial polysilicon layer 402 is planarized until the surface of the device wafer 20 facing away from the first wafer 10 is exposed, and an electrical connection structure 403 is formed in the via 30.

[0158] In this embodiment, the second insulating layer 303 only covers the hole wall of the second hole segment 302, and the electrical connection structure 403 is insulated from the first wafer 10 and electrically connected to the device wafer 20.

[0159] Reference Figure 26 and 27 The bonding boss 203, the second bonding layer 204, the sensitive structure 201 and the signal transmission structure 202 are formed in the same way as in the previous embodiments, and will not be described again here.

[0160] Unlike the aforementioned embodiments, referring to Figure 27 and 28In the thickness direction, the projection of the second bonding layer 204 of the signal transmission structure 202 does not overlap with the projection of the electrical connection structure 403. The electrical signal output from the second wafer 50 is transmitted to the signal transmission structure 202 through the first bonding layer 502 and the second bonding layer 204, then to the electrical connection structure 403 through the signal transmission structure 202, and finally output through the electrical connection structure 403.

[0161] This configuration allows the second bonding layer 204 to avoid the local uneven areas corresponding to the electrical connection structure 403, thereby improving the flatness of the bonding interface and the bonding reliability between it and the second wafer 50. At the same time, the electrical signals output from the second wafer 50 can still be led out through the second bonding layer 204, the signal transmission structure 202, and the electrical connection structure 403.

[0162] Reference Figure 17 This application also discloses a MEMS sensor, including:

[0163] The first wafer 10 has a first surface 101 and a second surface 102 disposed opposite to each other along the thickness direction;

[0164] The first insulating layer 104 covers the first surface 101;

[0165] The device wafer 20 includes a sensing structure 201 and a signal transmission structure 202 that are independent of each other. The side of the sensing structure 201 and the signal transmission structure 202 facing the first wafer 10 are both bonded to the first insulating layer 104. The sensing structure 201 includes at least one movable part 2011, and there is a first gap between the movable part 2011 and the first wafer 10.

[0166] The second wafer 50 has metal wiring 501 laid on it. The side of the second wafer 50 facing the first wafer 10 is bonded to the sensitive structure 201 and the signal transmission structure 202, so as to be electrically connected to the sensitive structure 201 and the signal transmission structure 202 respectively.

[0167] At least one through hole 30 includes a first hole segment 301 and a second hole segment 302 that are connected to each other. The first hole segment 301 passes through the signal transmission structure 202, and the second hole segment 302 extends into and through the first wafer 10. At least the hole wall of the second hole segment 302 is covered with a second insulating layer 303.

[0168] Electrical connection structure 403 is filled within through hole 30;

[0169] At least one signal lead-out structure 604 is located on the second surface 102. The signal lead-out structure 604 corresponds to a through hole 30 and is electrically connected to the electrical connection structure 403 in the corresponding through hole 30.

[0170] In some embodiments, refer to Figure 17 The second insulating layer 303 also covers the hole wall of the first hole segment 301. In other words, the second insulating layer 303 covers both the hole wall of the first hole segment 301 and the hole wall of the first hole segment 301.

[0171] In some embodiments, a first bonding layer 502 is deposited on the side of the second wafer 50 facing the first wafer 10, and a second bonding layer 204 is formed on the side of the sensitive structure 201 and the signal transmission structure 202 away from the first wafer 10. The corresponding first bonding layer 502 and second bonding layer 204 are connected. In the thickness direction, the projection of the second bonding layer 204 on the signal transmission structure 202 at least partially overlaps with the projection of the electrical connection structure 403.

[0172] Reference Figure 28 In other embodiments, within the first via 301, the electrical connection structure 403 is in direct contact with and electrically connected to the device wafer 20. In other words, the wall of the first via 301 is not covered with an insulating layer. A first bonding layer 502 is deposited on the side of the second wafer 50 facing the first wafer 10, and a second bonding layer 204 is formed on the side of the sensitive structure 201 and the signal transmission structure 202 facing away from the first wafer 10. The corresponding first bonding layer 502 and second bonding layer 204 are connected, and in the thickness direction, the projection of the second bonding layer 204 on the signal transmission structure 202 does not overlap with the projection of the electrical connection structure 403.

[0173] It is worth noting that the MEMS sensors disclosed in this application are illustrated using inertial sensors as an example, but are not limited to inertial sensors. The technical solutions disclosed in this application are also applicable to other types of MEMS sensors, such as MEMS microphones and MEMS pressure sensors. For different types of MEMS sensors, their specific structural forms, sensitive units, and functional implementation methods can be adjusted according to actual application requirements, but as long as the technical concept of this application is adopted, they should fall within the protection scope of this application.

[0174] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0175] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0176] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0177] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A method for forming a MEMS sensor, characterized in that, include: A first wafer is provided, the first wafer having a first surface and a second surface disposed opposite to each other along the thickness direction; A first insulating layer is formed on the first surface; A device wafer is provided, and the device wafer is bonded to the first insulating layer; At least one through-hole is formed, the through-hole comprising a first segment and a second segment connected to each other, the first segment penetrating the device wafer, the second segment extending into the first wafer but not penetrating the first wafer, and at least the wall of the second segment being covered with a second insulating layer. Polysilicon is filled into the through-hole to form an electrical connection structure; The device wafer is patterned to form a sensitive structure and a signal transmission structure that are independent of each other on the device wafer. The sensitive structure includes at least one movable part, and the movable part has a first gap with the first wafer. In the thickness direction, the projection of the via is located within the projection range of the signal transmission structure. A second wafer is provided, on which metal wiring is laid; the side of the device wafer opposite to the first surface is bonded to the second wafer, so that the sensitive structure and the signal transmission structure are electrically connected to the second wafer respectively; Remove a portion of the first wafer on the side containing the second surface to expose the electrical connection structure located within the via. At least one signal lead-out structure is formed on the second surface, each signal lead-out structure corresponding to one of the electrical connection structures and electrically connected to the corresponding electrical connection structure.

2. The method for forming a MEMS sensor according to claim 1, characterized in that, The specific steps of forming at least one through hole, the through hole including a first hole segment and a second hole segment connected to each other, the first hole segment penetrating the device wafer, the second hole segment extending into the first wafer but not penetrating the first wafer, and at least the hole wall of the second hole segment being covered with a second insulating layer include: Before forming the first insulating layer, at least one second hole segment is etched on the first side of the first wafer, the second hole segment extending into the interior of the first wafer along the thickness direction but not penetrating the first wafer; When the first insulating layer is formed, the second insulating layer covering the hole wall of the second hole segment is formed simultaneously; After the device wafer is bonded to the first insulating layer, a first hole segment is etched on the device wafer to penetrate the device wafer. The first hole segment corresponds to a second hole segment. In the thickness direction, the projection of the first hole segment and the projection of the corresponding second hole segment at least partially overlap, so that the first hole segment and the second hole segment are connected to form the through hole.

3. The method for forming a MEMS sensor according to claim 1, characterized in that, The specific steps of filling the via with polysilicon to form an electrical connection structure include: A polycrystalline silicon seed layer is deposited, the polycrystalline silicon seed layer covering the side surface of the device wafer opposite to the first wafer and the inner wall of the via; Polycrystalline silicon is epitaxially grown on the polycrystalline silicon seed layer until the polycrystalline silicon fills the vias, forming an initial polycrystalline silicon layer. The initial polysilicon layer is planarized until the surface of the device wafer facing away from the first wafer is exposed, and an electrical connection structure is formed within the via.

4. The method for forming a MEMS sensor according to claim 1, characterized in that, The specific steps of forming at least one through-hole, the through-hole comprising a first segment and a second segment connected to each other, the first segment penetrating the device wafer, the second segment extending into the first wafer but not penetrating it, and at least the wall of the second segment being covered by a second insulating layer include: After the device wafer is bonded to the first insulating layer, etching is performed from the side of the device wafer facing away from the first wafer toward the first wafer to form a first hole segment penetrating the device wafer and a second hole segment communicating with the first hole segment and extending into the first wafer.

5. The method for forming a MEMS sensor according to claim 4, characterized in that, The specific steps for forming at least one through hole also include: A second insulating layer is formed on the wall of the first aperture segment, the wall of the second aperture segment, and the surface of the device wafer facing away from the first wafer.

6. The method for forming a MEMS sensor according to claim 5, characterized in that, The specific steps of filling the via with polysilicon to form an electrical connection structure include: A polycrystalline silicon seed layer is deposited, the polycrystalline silicon seed layer covering the surface of the second insulating layer; Polycrystalline silicon is epitaxially grown on the polycrystalline silicon seed layer until the polycrystalline silicon fills the vias, forming an initial polycrystalline silicon layer. The initial polysilicon layer is planarized to remove the second insulating layer and the initial polysilicon layer covering the surface of the device wafer facing away from the first wafer, until the surface of the device wafer facing away from the first wafer is exposed, and the polysilicon located in the via forms the electrical connection structure.

7. The method for forming a MEMS sensor according to any one of claims 1 to 6, characterized in that, The second wafer has a first bonding layer deposited on the side facing the first wafer; the method for forming the MEMS sensor further includes: Before patterning the device wafer, a second bonding layer is formed on the side of the device wafer opposite to the first wafer; The specific steps of bonding the side of the device wafer away from the first surface to the second wafer include: The first bonding layer and the second bonding layer are bonded together so that the sensitive structure and the signal transmission structure are electrically connected to the second wafer, respectively.

8. The method for forming a MEMS sensor according to claim 7, characterized in that, Both the sensitive structure and the signal transmission structure have a second bonding layer formed on the side surface opposite to the first wafer, and the second bonding layer on the sensitive structure and the second bonding layer on the signal transmission structure are independent of each other.

9. The method for forming a MEMS sensor according to claim 8, characterized in that, When the second insulating layer covers both the hole wall of the first hole segment and the hole wall of the second hole segment, in the thickness direction, the projection of the second bonding layer on the signal transmission structure at least partially overlaps with the projection of the electrical connection structure.

10. The method for forming a MEMS sensor according to claim 8, characterized in that, When the second insulating layer covers the hole wall of the second hole segment, and the second insulating layer does not cover the hole wall of the first hole segment, the projection of the second bonding layer of the signal transmission structure and the projection of the electrical connection structure do not overlap in the thickness direction.

11. The method for forming a MEMS sensor according to claim 1, characterized in that, Also includes: Before forming the first insulating layer on the first surface, at least one first groove is formed on the first wafer; After forming a first insulating layer on the first surface, the first insulating layer also covers the inner wall of each of the first grooves; Wherein, the first groove corresponds to at least one of the movable parts, and in the thickness direction, the projection of the movable part is located within the projection range of the corresponding first groove, and the first groove constitutes the first gap.

12. The method for forming a MEMS sensor according to claim 1, characterized in that, The specific steps of forming at least one signal lead-out structure on the second surface, each signal lead-out structure corresponding to one of the electrical connection structures, and being electrically connected to the corresponding electrical connection structure include: A dielectric layer is formed, which covers the second surface. A second groove is formed on the dielectric layer, and each second groove corresponds to a through hole. The electrical connection structure corresponding to the through hole is exposed in the second groove. A redistribution layer is formed, which covers the dielectric layer and the electrical connection structure exposed in the second groove; A passivation layer is formed, which covers the redistribution layer. The passivation layer has multiple openings, and the redistribution layer is exposed in the openings. A signal lead-out structure is formed in the opening so that the signal lead-out structure is electrically connected to the corresponding electrical connection structure through the redistribution layer.

13. A MEMS sensor, characterized in that, include: The first wafer (10) has a first surface (101) and a second surface (102) disposed opposite to each other along the thickness direction. A first insulating layer (104) covers the first surface (101). The device wafer (20) includes a sensing structure (201) and a signal transmission structure (202) that are independent of each other. Both the sensing structure (201) and the signal transmission structure (202) are bonded to the first insulating layer (104) on the side facing the first wafer (10). The sensing structure (201) includes at least one movable part (2011) and there is a first gap between the movable part (2011) and the first wafer (10). The second wafer (50) has metal wiring (501) laid on it. The side of the second wafer (50) facing the first wafer (10) is bonded to the sensitive structure (201) and the signal transmission structure (202) to be electrically connected to the sensitive structure (201) and the signal transmission structure (202) respectively. At least one through hole (30) includes a first hole segment (301) and a second hole segment (302) that are connected to each other. The first hole segment (301) passes through the signal transmission structure (202), and the second hole segment (302) extends into the first wafer (10) and penetrates the first wafer (10). At least the hole wall of the second hole segment (302) is covered with a second insulating layer (303). An electrical connection structure (403) is filled within the through hole (30); At least one signal lead-out structure (604) is located on the second surface (102), each of the signal lead-out structures (604) corresponds to one of the through holes (30) and is electrically connected to the electrical connection structure (403) within the corresponding through hole (30).

14. The MEMS sensor according to claim 13, characterized in that, Within the first aperture segment (301), the electrical connection structure (403) is in direct contact with and electrically connected to the device wafer (20).

15. The MEMS sensor according to claim 14, characterized in that, The second wafer (50) has a first bonding layer (502) deposited on the side facing the first wafer (10). The sensitive structure (201) and the signal transmission structure (202) have a second bonding layer (204) formed on the side away from the first wafer (10). The corresponding first bonding layer (502) and the second bonding layer (204) are connected. In the thickness direction, the projection of the second bonding layer (204) on the signal transmission structure (202) does not overlap with the projection of the electrical connection structure (403).

16. The MEMS sensor according to claim 13, characterized in that, The second insulating layer (303) also covers the hole wall of the first hole segment (301).

17. The MEMS sensor according to claim 16, characterized in that, The second wafer (50) has a first bonding layer (502) deposited on the side facing the first wafer (10). The sensitive structure (201) and the signal transmission structure (202) each have a second bonding layer (204) formed on the side away from the first wafer (10). The corresponding first bonding layer (502) and the second bonding layer (204) are connected. In the thickness direction, the projection of the second bonding layer (204) on the signal transmission structure (202) at least partially overlaps with the projection of the electrical connection structure (403).

Images