Temperature sensing circuit, temperature sensor, memory device, and electronic device

Abstract

The application provides a temperature sensing circuit, a temperature sensor, a memory device and an electronic device. The temperature sensing circuit comprises an operational amplifier having a first input connected to a first node and a second input connected to a second node; a plurality of transistors each having a control terminal, a first terminal and a second terminal; a plurality of switch units each directly connected to the first node and the second node and each configured to connect the first terminal of a corresponding transistor to the first node or the second node; a plurality of preset resistors each connected between each switch unit and the first terminal of the corresponding transistor to connect the corresponding transistor to the second node via the preset resistor; and a current mirror configured to provide a first bias current to the first node and a second bias current to the second node and to copy the second bias current as a target current proportional to temperature.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a temperature sensing circuit, a temperature sensor, a storage device, and an electronic device. Background Technology

[0002] Semiconductor memories are classified into volatile memories such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM) and non-volatile memories such as Flash memory, Phase Change Material Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random-access Memory (RRAM), or Ferroelectric Random Access Memory (FRAM). Volatile memories lose the data stored in them when power is off, while non-volatile memories retain the data stored in them even when power is off.

[0003] DRAM memory is a common type of volatile memory. DRAM memory writes data by storing charge in the capacitors of the memory cells, and reads data from the memory by reading the charge from the capacitors of the memory cells. With the development of semiconductor technology, DRAM integration is becoming increasingly sophisticated, leading to thermal issues related to performance and reliability. Memory performance can be affected by temperature variations; therefore, high-precision temperature sensors are beneficial for monitoring and controlling the thermal characteristics of memory devices. Summary of the Invention

[0004] This application provides a temperature sensing circuit, a temperature sensor, a storage device, and an electronic device, which at least helps to improve the accuracy and linearity of the temperature sensor.

[0005] This application provides a temperature sensing circuit, including an operational amplifier having a first input terminal connected to a first node and a second input terminal connected to a second node; a transistor group including multiple transistors, each transistor having a control terminal, a first terminal, and a second terminal, the control terminal being coupled to the second terminal and receiving a preset voltage; multiple sets of switching units, each set of switching units corresponding to one of the transistors, each set of switching units being directly connected to the first node and the second node, and each set of switching units being used to connect the first terminal of the corresponding transistor to the first node or the second node; multiple preset resistors, each preset resistor corresponding to one of the transistors, each preset resistor being connected between each set of switching units and the first terminal of the corresponding transistor, so that the corresponding transistor is connected to the second node via the preset resistor; a current mirror configured to provide a first bias current to the first node and a second bias current to the second node based on the output voltage of the operational amplifier, and to replicate the second bias current as a target current proportional to temperature; wherein each set of switching units responds to a control signal to connect the first terminal of the corresponding transistor to one of the first node or the second node at the same time.

[0006] In addition, each of the transistors is the same size.

[0007] In addition, the transistor includes a bipolar junction transistor, with the control terminal being the base, the first terminal being the emitter, and the second terminal being the collector.

[0008] In addition, each set of switching units includes: a first switch, which is connected between the first node and the first terminal of the corresponding transistor; and a second switch, which is connected between the second node and the corresponding preset resistor.

[0009] In addition, during the same period, the first switches in the k1 group of switch units are all turned on, and the second switches in the k2 group of switch units are all turned on. k1 and k2 are both positive integers, and k2 > k1. Among them, the first switch and the second switch satisfy: Ron2 / Ron1 = k2 / k1, where Ron1 is the ideal on-resistance of the first switch and Ron2 is the ideal on-resistance of the second switch.

[0010] In addition, the first switch includes a first transmission gate, and the second switch includes a second transmission gate; wherein the size of the first transmission gate is k2 / k1 times the size of the second transmission gate.

[0011] In addition, the size of the first transmission gate includes the channel width-to-length ratio of the MOS transistor constituting the first transmission gate, and the size of the second transmission gate includes the channel width-to-length ratio of the MOS transistor constituting the second transmission gate.

[0012] In addition, the resistance value of each of the preset resistors is the same.

[0013] In addition, the first node is directly connected to the first input terminal of the operational amplifier, and the second node is directly connected to the second input terminal of the operational amplifier.

[0014] Furthermore, the multiple sets of switching units are configured such that, during a dynamic element matching cycle, if one of the first switch and the second switch in each set of switching units is turned on, the other is turned off; wherein, the dynamic element matching cycle includes multiple control phases performed sequentially, and in each control phase, only the first switch in one set of switching units is turned on, while the first switches in the remaining sets of switching units are turned off, so that during the dynamic element matching cycle, each of the multiple transistors is sequentially connected to the first node via its corresponding first switch, and the remaining transistors are connected to the second node via their corresponding second switches.

[0015] In addition, the temperature sensing circuit further includes a control circuit, which provides corresponding control signals to the multiple sets of switching units to control the state of the first switch and the state of the second switch.

[0016] Additionally, the current mirror includes: a first PMOS transistor, the control terminal of which is connected to the output terminal of the operational amplifier, and the first end of which is connected to the first node; a second PMOS transistor, the control terminal of which is connected to the control terminal of the first PMOS transistor, the first end of which is connected to the second node, and the second end of which is connected to the second end of the first PMOS transistor; and a third PMOS transistor, the control terminal of which is connected to the control terminal of the first PMOS transistor, the first end of which is used to output the target current, and the second end of which is connected to the second end of the first PMOS transistor.

[0017] In addition, the size of the first PMOS transistor is the same as that of the second PMOS transistor.

[0018] In addition, the third PMOS transistor has the same dimensions as the second PMOS transistor.

[0019] In addition, the temperature sensing circuit further includes a current generation circuit, configured to be connected to the first node, generating and outputting a reference current that is inversely proportional to the temperature.

[0020] This application also provides a temperature sensor, including: a temperature sensing circuit as described above; and a processing circuit configured to generate and output temperature information based at least on the target current.

[0021] In another aspect, this application also provides a storage device, including: a storage array; any of the above-described temperature sensing circuits, or any of the above-described temperature sensors.

[0022] Another aspect of this application provides an electronic device including the storage device described above.

[0023] The technical solution provided in this application has at least the following advantages: This application provides a high-performance temperature sensing circuit. Due to the clamping effect of the operational amplifier, the voltage of the first node is the same as the voltage of the second node. A preset resistor for generating the target current is connected between the switching unit and the corresponding transistor, so that each switching unit can be directly connected to the first and second nodes. The input voltage of each switching unit when it is on is either the voltage of the first node or the voltage of the second node. Therefore, the influence of the input voltage on each switching unit when it is on is consistent, making the total on-resistance of the switching unit connected to the first node the same as the total on-resistance of the switching unit connected to the second node. This avoids the additional error problem introduced by the mismatch of the conductivity resistance of the switching units, which helps to improve the linearity and accuracy of the obtained target current, thereby improving the linearity and accuracy of the temperature sensor. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a functional block diagram of a temperature sensor. Figure 2 for Figure 1 A schematic diagram of a circuit structure for a temperature sensing front-end circuit; Figure 3 for Figure 2 A schematic diagram of a circuit structure that incorporates dynamic component matching technology; Figure 4 A functional block diagram of a temperature sensing circuit provided in an embodiment of this application; Figure 5 for Figure 4 A schematic diagram of a switching unit; Figure 6 The diagram illustrates a case where transistors are connected to the first node and the second node corresponding to two different control stages within a dynamic element matching cycle. Figure 7 Another functional block diagram of the temperature sensing circuit provided in the embodiments of this application; Figure 8 A schematic diagram of another circuit structure of the temperature sensing circuit provided in the embodiments of this application; Figure 9 This is a schematic diagram of another structure of the temperature sensing circuit provided in an embodiment of this application; Figure 10 A functional block diagram of a temperature sensor provided in an embodiment of this application; Figure 11 A block diagram of a storage device provided in an embodiment of this application; Figure 12 A block diagram of an electronic device provided in an embodiment of this application.

[0026] Explanation of reference numerals in the attached figures: 11. Temperature sensing front-end circuit; i1, first current; i2, second current; bs, single-bit data; 17. Capacitor; 12. Clocked comparator; 13. DFF flip-flop; Tclk, clock signal; 15. First control unit; 16. Second control unit; Vref, reference voltage; 14. Inverter; A1. Operational amplifier; M1. First MOSFET; M2. Second MOSFET; M3. Third MOSFET; G1. First transmission gate; G2. Second transmission gate; Q1~Q9. BJT transistors; 101. Operational Amplifier; 102. Transistor Group; 103. Switching Unit; R0. Preset Resistor; 104. Current Mirror; IN-. First Input Terminal; IN+. Second Input Terminal; GND. Ground Terminal; net1. First Node; net2. Second Node; Iptat. Target Current; I1. First Bias Current; I2. Second Bias Current; C. Control Signal; Q1~Qm. Transistors; S1. First Switch; S2. Second Switch; dem1~demm. Control Code; dem1b~demmb. Inverted Code of Control Code; 105. Control Circuit; MP1. First PMOS Transistor; MP2. Second PMOS Transistor; MP3. Third PMOS Transistor; VDD. Power Supply Voltage; 106. Current Generation Circuit; Ictat. Reference Current; A2. Comparator; MP4. Fourth PMOS Transistor; MP5. Fifth PMOS Transistor; MN1. First NMOS Transistor; MN2. Second NMOS Transistor; Rctat. Voltage Divider Resistor; 201. Temperature sensing circuit; 202. Processing circuit; 300. Storage device; 301. Storage array; 302. Temperature sensor; 401. Processor. Detailed Implementation

[0027] Figure 1 This is a functional block diagram of a temperature sensor. Figure 2 for Figure 1 A schematic diagram of a circuit structure for a temperature sensing front-end circuit.

[0028] Reference Figure 1 and Figure 2 The temperature sensor includes a temperature sensing front-end circuit 11 and a modulator. The temperature sensing front-end circuit 11 generates a first current i1 that is proportional to the temperature and a second current Ictat that is inversely proportional to the temperature. The first current i1 and the second current i2 are fed into the modulator to generate single-bit data bs with a duty cycle related to the temperature.

[0029] A modulator is a circuit used to convert analog signals into digital signals. For example, a modulator can be a continuous-time delta-sigma modulator (CT-DSM), including a capacitor 17 for forming an integrator, a clocked comparator 12 for forming a quantizer, and a DFF flip-flop 13. Both the clocked comparator 12 and the DFF flip-flop 13 receive a clock signal Tclk. The output of the clocked comparator 12 is connected to the data input of the DFF flip-flop 13, and the output of the DFF flip-flop 13 is used to output a single-bit data bs.

[0030] The temperature sensor includes a first control unit 15 and a second control unit 16, both of which can be switches. When the first control unit 15 is on, a first current i1 is provided to the negative input terminal of the clocked comparator 12; when the second control unit 16 is on, a second current i2 is provided to the negative input terminal of the clocked comparator 12, and the positive input terminal of the clocked comparator 12 receives a reference voltage Vref. The temperature sensor also includes an inverter 14, whose input terminal is connected to the output terminal of the modulator and also controls the conduction state of the second control unit 16. The output terminal of the inverter 14 is used to control the conduction state of the first control unit 15. It can be understood that the first control unit 15 and the second control unit 16 are alternately turned on to realize the charging and discharging process of the capacitor 17. When the first control unit 15 is turned on, the capacitor 17 is charged based on the first current i1. When the second control unit 16 is turned on, the capacitor 17 is discharged based on the second current i2. Since the first current i1 increases with the temperature, the capacitor 17 charges faster, while the second current i2 decreases with the temperature, the capacitor 17 discharges slower. Through the cycle of charging and discharging, the output single-bit data bs is a pulse signal with a duty cycle that changes with temperature. Therefore, the single-bit data bs reflects the temperature change.

[0031] The single-bit data bs is fed into a digital circuit (such as a counter or time-to-digital converter), and by measuring the duty cycle, a digital code representing the temperature can be output.

[0032] refer to Figure 2 The temperature-sensing front-end circuit 11 is used to generate a first current i1 proportional to the temperature. The temperature-sensing front-end circuit 11 includes an operational amplifier A1, a first BJT transistor, and a second BJT transistor. The first BJT transistor is connected to the negative input terminal of the operational amplifier A1, and the second BJT transistor is connected to the non-inverting input terminal of the operational amplifier A1 via a resistor Rptat. The emitter area of ​​the second BJT transistor is n times the emitter area of ​​the first BJT transistor, where n is any positive integer greater than 1. Figure 2 Taking n=8 as an example, Q=1 and Q=8 indicate that the emitter area of ​​the second BJT is 8 times that of the first BJT. The collectors of both the first and second BJTs are connected to ground GND. The temperature sensing front-end circuit 11 also includes a current mirror composed of a first MOSFET M1, a second MOSFET M2, and a third MOSFET M3. The current mirror is used to provide a first bias current to the first BJT, a second bias current to the second BJT, and to replicate the second bias current as the first current i1.

[0033] BJT transistors meet the following characteristics:

[0034] Where Is is the reverse saturation current, Ic is the collector current, and V T It is the thermal voltage, and V T The calculation formula is as follows:

[0035] Where k is Boltzmann's constant (characterizing the relationship between energy and temperature in thermodynamics); q is the electron charge (characterizing the charge carried by a single electron); T is the absolute temperature, also known as thermodynamic temperature, with the unit Kelvin (K). It should be noted that, unless otherwise specified, the temperature mentioned in the embodiments of this application refers to absolute temperature. T It is directly proportional to temperature.

[0036] Since the emitter area of ​​the second BJT is 8 times that of the first BJT, then:

[0037] △VBE is the emitter voltage difference between the first and second BJT transistors, which is the voltage applied across resistor Rptat. VBE1 is the emitter voltage of the first BJT transistor, and VBE2 is the emitter voltage of the second BJT transistor. Since V... T It is directly proportional to temperature, so that ΔVBE is a voltage that is directly proportional to temperature.

[0038] The first current Iptat is related to the voltage ΔVBE across the resistor Rptat. The magnitude of the first current i1 can be obtained based on the ratio between ΔVBE and the resistance value of Rptat. Due to manufacturing mismatch errors in the first and second BJT transistors, the accuracy of the voltage ΔVBE is affected, thus impacting the accuracy of the first current i1, resulting in relatively low precision of the temperature sensor.

[0039] To achieve high-precision temperature sensors, conventional layout devices suffer from process mismatch errors. Therefore, Dynamic Element Matching (DEM) technology is introduced. By periodically swapping the connection positions of unit components, the mismatch error in a single cycle is significantly offset after averaging over multiple cycles, thereby improving the overall matching accuracy and temperature measurement linearity, and thus enhancing the measurement accuracy of the temperature sensor.

[0040] Figure 3 for Figure 2 The diagram illustrates a circuit structure that incorporates dynamic component matching technology. The second BJT with an emitter area of ​​Q=8 is composed of eight BJTs connected in parallel, while the first BJT with an emitter area of ​​Q=1 is composed of a single BJT.

[0041] refer to Figure 2 The circuit includes multiple BJTs, each with the same emitter area, denoted as Q1~Q9=1. The emitter of each BJT is connected to two sets of transmission gates: a first transmission gate G1 and a second transmission gate G2. The first transmission gate G1 is controlled by a first signal, and the second transmission gate G2 is controlled by a second signal, which are inverted signals. When the first transmission gate G1 is turned on, the corresponding BJT is connected to the negative input of operational amplifier A1; when the second transmission gate G2 is turned on, the corresponding BJT is connected to the positive input of operational amplifier A1. Furthermore, at any given time, only one of the first transmission gate G1 and the second transmission gate G2 corresponding to a given BJT can be turned on.

[0042] At the same time, one BJT is connected to the negative input terminal of operational amplifier A1 (denoted as the first branch), and eight BJTs are connected to the positive input terminal of operational amplifier A1 (denoted as the second branch). Thus, the second branch consists of eight BJTs connected in parallel. The equivalent emitter area of ​​the BJTs in the second branch is eight times that of the BJTs in the first branch, which can be equivalent to... Figure 2 The correspondence is shown. The first signal has eight phases that change periodically: 1000_0000 / 0100_0000 / ... / 0000_0010 / 0000_0001. In this way, the BJT transistors that make up the first branch periodically traverse between Q1 and Q8, in order to eventually offset the error caused by process deviation.

[0043] However, even with dynamic component matching, the accuracy of the temperature sensor still did not meet expectations.

[0044] Further analysis revealed that, to match the ratio of the equivalent emitter areas of the first and second branches, the size of the first transmission gate G1 was designed to be n times the size of the second transmission gate G2. For example, if n is 8, then it is 8 times. Ideally, the on-resistance of the first transmission gate G1 should be 1 / 8 of the resistance of the second transmission gate G2, and the voltage drop caused by the conduction of the first transmission gate G1 on the first branch should be the same as the voltage drop caused by the conduction of all corresponding second transmission gates G2 on the second branch. However, simulations showed that the on-resistance of the first transmission gate G1 on the first branch is not 1 / 8 of the on-resistance of the second transmission gate G2 when the circuit is working. This results in a mismatch in the on-resistances of the transmission gates on the first and second branches. This mismatch in on-resistance introduces an additional IR voltage drop (the voltage drop generated when current flows through the resistor) to the voltage ΔVBE, causing poor overall linearity of the current Iptat and deviating the expected accuracy of the temperature sensor.

[0045] Although the size of the first transmission gate G1 is designed to be 8 times the size of the second transmission gate G2, the voltage transmitted by the first transmission gate G1 to the negative input terminal of the first operational amplifier is approximately 0V. The gate control voltages of both the first transmission gate G1 and the second transmission gate G2 are Vtsc. The voltage of the first transmission gate G1 is VGS1 = Vtsc - 0 = Vtsc. The voltage transmitted by the second transmission gate G2 is the voltage across the resistor ΔVBE. Therefore, the voltage of the second transmission gate G2 is VGS2 = Vtsc - ΔVBE < Vtsc. Since VGS1 and VGS2 are different, the actual on-resistance of the first transmission gate G1 and the actual on-resistance of the second transmission gate G2 are not in a 1 / 8 relationship.

[0046] To at least solve or improve the above-mentioned technical problems, embodiments of this application provide a temperature sensing circuit. By designing and arranging the connection relationship between transistor groups, multiple sets of switching units, and preset resistors, the circuit solves the problem of mismatch between the on-resistance of the switching unit when the transistor is connected to the first node and the on-resistance of the switching unit when the transistor is connected to the second node. This suppresses the additional measurement error introduced due to the mismatch of the on-resistance of the switching units, improves the accuracy and linearity of the output target current, and thus improves the measurement accuracy and linearity of the temperature sensor.

[0047] Furthermore, it should be noted that, without contradiction, the relevant operating principles of the aforementioned circuits also apply to the following embodiments.

[0048] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0049] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined. Similarly, "multiple sets" refers to two or more sets (including two sets), and "multiple pieces" refers to two or more pieces (including two pieces).

[0050] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0051] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0052] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application. For example, if the device or element in the illustration is inverted, then the element described as "below," "under," "below," or "bottom" of other elements or features will be oriented "above" or "top" of said other elements or features. Therefore, the term "below" may cover both above and below orientation depending on the context in which the term is used, which will be obvious to those skilled in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0053] In the description of embodiments of this application, the terms "about," "approximately," "roughly," or "about" for a numerical value referring to a specific parameter include the numerical value, and those skilled in the art will understand that the deviation from the numerical value is within the acceptable tolerance of the specific parameter. For example, "about" or "about" for a numerical value may include additional numerical values ​​that are in the range of 90.0% to 110.0% of the numerical value, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0054] In the accompanying drawings corresponding to the embodiments of this application, the thickness and / or area of ​​layers, films, panels, regions, etc., are enlarged for better understanding and ease of description. Throughout the specification, the same reference numerals denote the same elements. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0055] In the description of embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be an intermediate component between the two components. Conversely, when describing a component on the surface of another component, or a component "directly" on another component, or a component surface on which another component is formed or disposed, it indicates that there is no intermediate component between the two components. For simplicity and clarity, various components may be drawn at any scale. In the drawings, some components may be omitted for simplicity.

[0056] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "the component" is also intended to include the plural form unless the context clearly indicates otherwise.

[0057] The aforementioned components can refer to layers, films, regions, parts, structures, or plates, etc.

[0058] Figure 4 This is a functional block diagram of a temperature sensing circuit provided in an embodiment of this application.

[0059] refer to Figure 4 The temperature sensing circuit includes an operational amplifier 101, a transistor group 102, multiple switching units 103, multiple preset resistors R0, and a current mirror 104.

[0060] Operational amplifier 101 has a first input terminal IN- connected to a first node net1 and a second input terminal IN+ connected to a second node net2.

[0061] Transistor group 102 includes multiple transistors, each transistor having a control terminal (not shown), a first terminal (not shown), and a second terminal (not shown). The control terminal is coupled to the second terminal and receives a preset voltage. In some examples, both the control terminal and the second terminal are connected to ground (GND), and the preset voltage can be the ground voltage.

[0062] Each group of switching units 103 is directly connected to the first node net1 and the second node net2, and each group of switching units 103 is used to connect the first terminal of the corresponding transistor to the first node net1 or the second node net2.

[0063] Each preset resistor R0 corresponds to a transistor. Each preset resistor R0 is connected between each group of switching units 103 and the first terminal of the corresponding transistor, so that the corresponding transistor is connected to the second node net2 via the preset resistor R0.

[0064] The current mirror 104 is configured to provide a first bias current I1 to the first node net1 and a second bias current I2 to the second node net2 based on the output voltage of the operational amplifier 101, and to replicate the second bias current I2 as a target current Iptat that is proportional to temperature.

[0065] In addition, each group of switching units 103 responds to the control signal C to connect the first terminal of the corresponding transistor to either the first node net1 or the second node net2 at the same time.

[0066] In the above technical solution, since the switching units 103 are all directly connected to the first node net1 and the second node net2, and the operational amplifier 101 has the characteristic that the voltage of the first node net1 is the same as the voltage of the second node net2, the on-resistance of the switching unit 103 used to connect the transistor to the first node net1 and the on-resistance of the switching unit 103 used to connect the transistor to the second node net2 are well matched. This avoids the problem of mismatch in conduction resistance caused by the difference in input voltage of each switching unit 103, which is beneficial to improving the linearity and accuracy of the target current Iptat, thereby improving the accuracy and linearity of the temperature sensor.

[0067] The temperature sensing circuit provided in the embodiments of this application will be described in more detail below with reference to the accompanying drawings.

[0068] The temperature sensing circuit generates a target current Iptat that is proportional to the temperature. This target current Iptat serves as the basis for the temperature sensor to generate temperature-related codes. Therefore, the accuracy of the correspondence between the target current Iptat and the temperature directly affects the accuracy of the temperature sensor. By setting multiple transistors and multiple sets of switching units 103, and ensuring that each set of switching units 103 operates in a specific state, it is guaranteed that at any given time, each transistor can only be connected to either the first node net1 or the second node net2. No switching unit 103 will have a transistor simultaneously connected to both the first node net1 and the second node net2.

[0069] Understandably, during the operation of the temperature sensing circuit, i.e. when the temperature sensing circuit needs to generate the target current Iptat, each group of switching units 103 will not have a situation where the corresponding transistor is neither connected to the first node net1 nor to the second node net2. In this way, it can be ensured that each transistor can participate in the dynamic component matching process.

[0070] During the dynamic component matching process, the connection state of each transistor with the first node net1 and the second node net2 is periodically adjusted so that the inherent mismatch error of each transistor can be averaged out over multiple cycles, thereby improving the accuracy of the target current Iptat.

[0071] The temperature sensing circuit includes a first branch and a second branch. The first branch connects the first node net1 to the ground terminal GND, and the second branch connects the second node net2 to the ground terminal GND. The first branch includes a first equivalent transistor connected to the first input terminal IN- of the operational amplifier 101. This first equivalent transistor generates a temperature-dependent voltage VBE. The second branch includes a second equivalent transistor connected to the second input terminal IN+ of the operational amplifier 101. The current density of this second equivalent transistor differs from that of the first equivalent transistor. This second equivalent transistor generates a voltage difference ΔVBE proportional to the temperature, which is the voltage across a preset resistor R0.

[0072] It is understandable that by controlling the conduction status of each switching unit 103, the number of transistors connected in parallel in the first branch and the number of transistors connected in parallel in the second branch can be reasonably selected.

[0073] Since the first node net1 is directly coupled to the first input terminal IN- and the second node net2 is directly coupled to the second input terminal IN+, based on the virtual short and virtual open characteristics of the operational amplifier 101, the voltage at the first input terminal IN- is the same or substantially the same as the voltage at the second input terminal IN+. Therefore, for any switching unit 103, whether the transistor is connected to the first node net1 or the second node net2 via the switching unit 103, the input voltage applied to the switching unit 103 is the same (the input voltage is either the voltage at the first input terminal IN- or the voltage at the second input terminal IN+). Thus, the problem of mismatched actual on-resistance of the switching unit 103 due to different input voltages applied to it at different times can be reduced or even avoided. In other words, the error in voltage difference ΔVBE caused by the mismatched on-resistance of the switching unit 103 can be reduced, thereby improving the linearity of the target current Iptat and its temperature-related accuracy, and ultimately improving the accuracy of the temperature sensor.

[0074] Transistor group 102 includes m transistors, each of which is identified as Q1, Q2...Qm-1, Qm, where m can be a positive integer greater than or equal to 3.

[0075] In some examples, each transistor can be of the same size. This ensures that during dynamic component matching adjustment, the ratio of the current density of the second equivalent transistor in the second branch to the current density of the first equivalent transistor in the first branch remains constant each time the conduction state of each switching unit 103 is adjusted, thus achieving a precise current density ratio to ensure the linearity and accuracy of the target current Iptat output. Furthermore, the identical size of each transistor allows the dynamic component matching adjustment process to function effectively, and the high degree of matching of the electrical parameters of each transistor effectively suppresses the impact of transistor process mismatch on measurement accuracy.

[0076] The transistor can include a bipolar junction transistor, with the base as the control terminal, the emitter as the first terminal, and the collector as the second terminal. Each transistor has the same dimensions, including the same emitter area. Because the emitter area is identical, the saturation current of each transistor exhibits good consistency, suppressing systematic errors caused by differences in emitter area and further improving the accuracy of the target current Iptat.

[0077] Each switching unit 103 is controlled by a control signal C to adjust the connection state between the corresponding transistor and the first node net1 and the second net2. Each switching unit 103 is configured such that, at the same time, k1 transistors are connected to the first node net1, and k2 transistors are connected to the second node net2. k1 + k2 = m, and k2 > k1, and k2 is q times k1, where k is a positive integer. It is understandable that k1 can be 1, which helps reduce the number of transistors required in the temperature sensing circuit and saves the area occupied by the temperature sensing circuit. Of course, k1 can also be any positive integer greater than 1.

[0078] Figure 5 for Figure 4 A schematic diagram of a switching unit.

[0079] refer to Figure 4 and Figure 5 Each set of switching units 103 includes a first switch S1 and a second switch S2. The first switch S1 is connected between the first node net1 and the first terminal of the corresponding transistor, and the second switch S2 is connected between the second node net2 and the corresponding preset resistor R0.

[0080] The control signal C includes a multi-bit control code, which is sequentially identified as dem1, dem2, ..., demm. The control signal C also includes the inverse code of the multi-bit control code, which is sequentially identified as dem1b, dem2b, ..., demmb. For example, dem1b is the inverse code of control code dem1. If control code dem1 is logic "1", then the corresponding inverse code demb1 is logic "0", and if control code dem1 is logic "0", then the corresponding inverse code dem1b is logic "1". Control code dem1 and its corresponding inverse code dem1b are used to control the conduction of the switching unit 103 connected to transistor Q1. Control code dem2 and its corresponding inverse code dem2b are used to control the conduction of the switching unit 103 connected to transistor Q2, and so on. Control code demm-1 and its corresponding inverse code demm-1b are used to control the conduction of the switching unit 103 connected to transistor Qm-1, and control code demm and its corresponding inverse code demmb are used to control the conduction of the switching unit 103 connected to transistor Qm.

[0081] The first switch S1 and the second switch S2 are controlled by the corresponding control code and the inverse code of the control code, so that at the same time, for the same group of switch units 103, if the first switch S1 is turned on, the second switch S2 is turned off, and if the first switch S1 is turned off, the second switch S2 is turned on.

[0082] In some examples, at the same time, the first switch S1 in switch unit 103 of group k1 is turned on, and the second switch S2 in switch unit 103 of group k2 is turned on, where k1 and k2 are both positive integers, and k2 > k1. The first switch S1 and the second switch S2 satisfy: Ron2 / Ron1 = k2 / k1, where Ron1 is the ideal on-resistance of the first switch S1, and Ron2 is the ideal on-resistance of the second switch S2.

[0083] It is understandable that the ideal on-resistance of the first switch S1 and the second switch S2 refers to the equivalent resistance presented when the first switch S1 or the second switch S2 is fully turned on under ideal operating conditions. For example, the first switch S1 and the second switch S2 with the same structure have exactly the same ideal on-resistance, which does not change with the current flowing through them, the voltage across them, or the temperature.

[0084] Since the input terminal of the first switch S1 is directly connected to the first node net1, and the input terminal of the second switch S2 is directly connected to the second node net2, and the voltages of the first node net1 and the second node net2 are the same or substantially the same, the influence of the voltage of the first node net1 on the conduction of the first switch S1 is consistent with the influence of the voltage of the second node net2 on the conduction of the second switch S2. This makes the actual on-resistance of the first switch S1 the same as its ideal on-resistance, and the actual on-resistance of the second switch S2 the same as its ideal on-resistance. Therefore, during the operation of the temperature sensing circuit, the conduction characteristics of the first switch S1 and the second switch S2 are consistent with expectations, avoiding additional errors introduced due to deviations in the actual on-resistance of the first switch S1 and / or the second switch S2 from expectations.

[0085] To reduce the design difficulty of the first switch S1 and the second switch S2, k2 / k1 can be a positive integer.

[0086] In some examples, the first switch S1 can be a first transmission gate, and the second switch S2 can be a second transmission gate, with the size of the first transmission gate being k2 / k1 times the size of the second transmission gate. Both the first and second transmission gates are CMOS transmission gates.

[0087] The dimensions of the first transmission gate include the channel width-to-length ratio of the MOS transistor constituting the first transmission gate, and the dimensions of the second transmission gate include the channel width-to-length ratio of the MOS transistor constituting the second transmission gate.

[0088] Understandably, for a CMOS transmission gate, it is composed of NMOS transistors and PMOS transistors connected in parallel. The channel width-to-length ratio of the CMOS transmission gate is the sum of the channel width-to-length ratios of the NMOS transistors and the PMOS transistors. To maximize the process compatibility between different devices, the channel width-to-length ratio of the NMOS transistor in the first transmission gate can be k2 / k1 times that of the second NMOS transistor, and the channel width-to-length ratio of the PMOS transistor in the first transmission gate can be k2 / k1 times that of the second PMOS transistor.

[0089] It should be noted that in other embodiments, the first switch may also be composed of an NMOS transistor or a PMOS transistor, and the second switch may also be composed of an NMOS transistor or a PMOS transistor.

[0090] In some examples, the resistance value of each preset resistor R0 can be identical. This ensures that the current flowing through each transistor remains consistent, avoiding uneven current distribution caused by different preset resistor R0 values. This guarantees that each transistor operates at the same current density, preventing errors introduced by resistance mismatch of the preset resistors R0. Furthermore, during dynamic component matching and adjustment, deviations caused by resistance mismatch of the preset resistors R0 can be avoided, maximizing the effectiveness of dynamic component matching. Therefore, by designing the preset resistor R0 to have the same value, the accuracy of the target current Iptat can be further improved, thereby further enhancing the measurement accuracy of the temperature sensor.

[0091] Continue to refer to Figure 5 The first node net1 is directly connected to the first input terminal IN- of operational amplifier 101, and the second node net2 is directly connected to the second input terminal IN+ of operational amplifier 101. That is, there are no other components between the first node net1 and the first input terminal IN-, and there are no other components between the second node net2 and the second input terminal IN+. This helps ensure voltage consistency between the first node net1 and the first input terminal IN-, and ensures voltage consistency between the second node net2 and the second input terminal IN+, thereby improving the voltage consistency between the first node net1 and the second node net2. In other words, the voltage of the first node net1 is the same as the voltage of the second node net2, avoiding unacceptable voltage drops between the first input terminal IN- and the first node net1, or between the second input terminal IN+ and the second node net2. This prevents the actual on-resistance of the first switch S1 or the second switch S2 from deviating from the ideal on-resistance.

[0092] Continue to refer to Figure 4 and Figure 5 In some examples, multiple sets of switching units 103 are configured such that, during a dynamic element matching cycle, one of the first switch S1 and the second switch S2 in each set of switching units 103 is turned on while the other is turned off. The dynamic element matching cycle includes multiple control phases performed sequentially, and in each control phase, only the first switch S1 in one set of switching units 103 is turned on, while the first switches S1 in the remaining sets of switching units 103 are turned off. This ensures that, during the dynamic element matching cycle, each of the multiple transistors is sequentially connected to the first node net1 via its corresponding first switch S1, and the remaining transistors are connected to the second node net2 via their corresponding second switches S2.

[0093] Taking m = 9 as an example, in each control phase (i.e., the same period), the number of transistors connected to the first node net1 is 1, and the number of transistors connected to the second node net2 is 9. Taking the first bias current I1 and the second bias current I2 as having the same magnitude as an example, the target current Iptat is calculated as follows: In the first branch, the voltage VBE between the first node net1 and the ground terminal GND is as follows:

[0094] Among them, V T Let Ic be the collector current and Is be the reverse saturation current. Since the second branch has 8 transistors connected in parallel, the voltage difference ΔVBE across each preset resistor R0 is as follows:

[0095] The current I flowing through each preset resistor R0 is as follows:

[0096] Where r is the resistance value of each preset resistor R0.

[0097] Thus, the second bias current I2 is obtained, as shown below:

[0098] When the current mirror 104 replicates the second bias current I2 as the target current Iptat in a 1:1 manner, the target current Iptat is as follows:

[0099] Furthermore, during the dynamic element matching cycle, the first switch S1 corresponding to one of the multiple transistors can be fixedly turned off and the second switch S2 fixedly turned on, and this transistor does not participate in the rotation of dynamic element matching. By setting the branch corresponding to this transistor as a fixed reference branch, the fixed reference branch helps to provide a stable electrical reference, reduce the complexity of control logic and noise interference, and further improve the accuracy of the target current Iptat output by the temperature sensing circuit.

[0100] It should be noted that the above dynamic element matching cycle is illustrated with k1 being 1 and k2 being a positive integer greater than 1. It can be understood that in each control pre-stage, the first switch in the k1 group of switch units can be turned on, and the first switch in the other groups of switch units can be turned off, where k1 is any positive integer greater than 1.

[0101] Figure 6The diagram illustrates the case where transistors are connected to the first node and the second node corresponding to two different control stages within a dynamic element matching cycle.

[0102] Reference Figure 5 and Figure 6 Taking m as 9 as an example, transistor group 102 includes multiple transistors, sequentially labeled Q1 to Q9. These nine transistors can be arranged in a 3×3 array layout. The center of the array is transistor Q9, which serves as a fixed reference branch. Transistor Q9 does not participate in phase switching and always serves as a reference unit with a 1x emitter area. The eight surrounding positions of transistor Q9 are occupied by transistors Q1 to Q8. This array-style layout can minimize process variations. In each control stage, transistors at different positions on the layout are connected in turn to the first node net1 to form the first branch, while the remaining transistors are connected to the second node net2 to form the second branch.

[0103] like Figure 6 As shown, Figure 6 The diagram illustrates the two control phases. In the first control phase, transistor Q1 is connected to the first node net1, and the remaining transistors Q2-Q9 are connected to the second node net2. In the second control phase, transistor Q8 is connected to the first node, and the remaining transistors Q1-Q7 and transistor Q9 are connected to the second node net2.

[0104] After a single dynamic element matching cycle consisting of multiple control stages, all transistors except transistor Q9 are connected to the first node net1 in turn. In this way, after one or more dynamic element matching cycles, the process error of the eight transistors can be converted into an average error, ultimately reducing or even eliminating the error caused by process deviation, thereby improving the linearity and accuracy of the target current Iptat.

[0105] Figure 7 This is another functional block diagram of the temperature sensing circuit.

[0106] Reference Figure 4 and Figure 7 The temperature sensing circuit also includes a control circuit 105, which provides corresponding control signals C to multiple sets of switch units 103 to control the state of the first switch S1 and the state of the second switch S2.

[0107] For a description of the control signal C, please refer to the description of the foregoing embodiments, which will not be repeated here. The control circuit 105 can be any circuit capable of providing a multi-bit control code and whose phase changes during each dynamic element matching cycle.

[0108] Figure 8This is a schematic diagram of another circuit structure for a temperature sensing circuit.

[0109] refer to Figure 8 The current mirror 104 includes a first PMOS transistor MP1, a second PMOS transistor MP2, and a third PMOS transistor MP3. The control terminal of the first PMOS transistor MP1 is connected to the output terminal of the operational amplifier 101, and the first terminal of the first PMOS transistor MP1 is connected to the first node net1. The control terminal of the second PMOS transistor MP2 is connected to the control terminal of the first PMOS transistor MP1, the first terminal of the second PMOS transistor MP2 is connected to the second node net2, and the second terminal of the first PMOS transistor MP1 is connected to the second terminal of the second PMOS transistor MP2. The control terminal of the third PMOS transistor MP3 is connected to the control terminal of the first PMOS transistor MP1, the first terminal of the third PMOS transistor MP3 is used to output the target current Iptat, and the second terminal of the third PMOS transistor MP3 is connected to the second terminal of the first PMOS transistor MP1.

[0110] The second terminals of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are all connected to the power supply voltage VDD.

[0111] The first terminal of the first PMOS transistor MP1 is used to output the first bias current I1, and the first terminal of the second PMOS transistor MP2 is used to output the second bias current I2. The first bias current I1 and the second bias current I2 can be the same.

[0112] In some examples, the dimensions of the first PMOS transistor MP1 are the same as those of the second PMOS transistor MP2. For instance, the channel width-to-length ratio of the first PMOS transistor MP1 can be the same as that of the second PMOS transistor MP2. Thus, a simple circuit can be used to achieve the requirement that the magnitude of the first bias current I1 is the same as that of the second bias current I2.

[0113] The dimensions of the third PMOS transistor MP3 can also be the same as those of the second PMOS transistor MP2. For example, the channel width-to-length ratio of the first PMOS transistor MP1 can be the same as that of the third PMOS transistor MP3. In this way, a simple circuit can be used to achieve the requirement that the target current Iptat is the same as the second bias current I2.

[0114] It is understandable that the size of the third PMOS transistor can also be different from that of the second PMOS transistor, that is, the target current is not a 1:1 replica of the second bias current. Based on the ratio between the size of the third PMOS transistor and the size of the second PMOS transistor, the ratio between the second bias current and the target current can be obtained, and then the corresponding target current can be obtained based on the second bias current.

[0115] Figure 9This is a schematic diagram of another structure of the temperature sensing circuit.

[0116] refer to Figure 9 The temperature sensing circuit may also include a current generation circuit 106. The current generation circuit 106 is configured to be connected to the first node net1, and to generate and output a reference current Ictat that is inversely proportional to the temperature.

[0117] In some examples, the current generation circuit 106 may include a comparator A2, the negative input of which is connected to the first node net1, and a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a first NMOS transistor MN1, and a second NMOS transistor MN2. The non-inverting input of comparator A2 is connected to the first terminal of the fourth PMOS transistor MP4. The control terminals of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are both connected to the output terminal of comparator A2. The second terminals of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are both connected to the power supply voltage VDD. The first terminal of the fourth PMOS transistor MP4 is connected to the ground terminal GND via the voltage divider resistor Rctat. The second terminal of the fifth PMOS transistor MP5 is connected to the first terminal of the first NMOS transistor MN1. The control terminal of the first NMOS transistor MN1 is connected to the first terminal of the first NMOS transistor MN1 and the control terminal of the second NMOS transistor. The second terminal of the first NMOS transistor MN1 is connected to the ground terminal GND. The second terminal of the second NMOS transistor MN2 is connected to the ground terminal GND, and the first terminal of the second NMOS transistor MN2 is used to output the reference current Ictat flowing to the second terminal of the second NMOS transistor MN2.

[0118] It is understandable that the voltage across the voltage divider resistor Rctat is the same as the voltage between the first node net1 and the ground terminal GND mentioned above.

[0119] In the above technical solution, due to the clamping effect of the operational amplifier, the voltage of the first node is the same as the voltage of the second node. The position of the preset resistor used to generate the target current in the circuit is adjusted, placing it between the switching unit and the corresponding transistor, so that each switching unit can be directly connected to both the first and second nodes. The input voltage of each switching unit when it is conducting is either the voltage of the first node or the voltage of the second node. Therefore, the influence of the input voltage on each switching unit when it is conducting is consistent, making the total on-resistance of the switching units connected to the first node the same as the total on-resistance of the switching units connected to the second node, avoiding additional error problems introduced by mismatched conductivity of the switching units. Thus, adopting the above technical solution helps improve the linearity and accuracy of the obtained target current, thereby improving the linearity and accuracy of the temperature sensor.

[0120] Simulations revealed that, during the same period, the actual on-resistance of each switch unit connected to the first node and the actual on-resistance of each switch unit connected to the second node were the same or nearly the same. It can be understood that the actual on-resistance of each switch unit connected to the first node refers to the parallel equivalent on-resistance of each switch unit connected to the first node, i.e., the total on-resistance of the switch units connected to the first node mentioned above; and the actual on-resistance of each switch unit connected to the second node refers to the parallel on-resistance of each switch unit connected to the second node, i.e., the total on-resistance of the switch units connected to the second node mentioned above.

[0121] Understandably, this is in conjunction with references. Figure 3 and Figure 4 Taking k2 / k1=8 as an example, Figure 4 The preset resistor R0 shown is designed with the following resistance value: Figure 3 If the resistance of the resistor Rptat shown is 8 times its value, then... Figure 4 The target current output by the temperature sensing circuit shown is Figure 3 The first current output by the temperature sensing circuit shown is equivalent.

[0122] Accordingly, this application also provides a temperature sensor, including the temperature sensing circuit provided in any of the above embodiments. The descriptions in the foregoing embodiments are also applicable to the embodiments of the temperature sensor. Therefore, for descriptions that are the same as or corresponding to those in the foregoing embodiments, please refer to the detailed descriptions in the foregoing embodiments, which will not be repeated hereafter.

[0123] Figure 10 This is a functional block diagram of a temperature sensor provided in an embodiment of this application.

[0124] refer to Figure 10 The temperature sensor may include a temperature sensing circuit 201 and a processing circuit 202. The processing circuit 202 is configured to generate and output temperature information based at least on the target current Iptat.

[0125] The processing circuit may include a first circuit for generating single-bit data with a duty cycle varying with temperature, and a second circuit for generating a temperature code reflecting temperature information based on the single-bit data.

[0126] Accordingly, this application also provides a storage device, including the temperature sensing circuit or temperature sensor provided in any of the foregoing embodiments. The descriptions in the foregoing embodiments are also applicable to the embodiments of the storage device. Therefore, for descriptions that are the same as or corresponding to those in the foregoing embodiments, please refer to the detailed descriptions in the foregoing embodiments, which will not be repeated hereafter.

[0127] Figure 11 This is a block diagram of a storage device provided in an embodiment of this application.

[0128] refer to Figure 11 The storage device 300 includes a storage array 301 and a temperature sensor 302 or a temperature sensing circuit.

[0129] In some embodiments, storage device 300 may be a storage device including volatile memory cells. For example, storage device 300 may include various dynamic random access memories (DRAMs), such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, or Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM).

[0130] In other embodiments, the storage device 300 includes, in addition to volatile memory cells, non-volatile memory cells such as SRAM, NAND flash memory, NOR flash memory, RRAM, FRAM, PRAM, TRAM, or MRAM.

[0131] The memory array 301 may include multiple memory cells and word lines and bit lines connected to the memory cells.

[0132] Accordingly, embodiments of this application may also provide an electronic device that may include the storage device provided in the above embodiments.

[0133] Figure 12 A block diagram of an electronic device provided in an embodiment of this application.

[0134] refer to Figure 12 The electronic device includes a processor 401 and a storage device 300, the storage device 300 being coupled to the processor 401, and the storage device 300 including the storage device provided in any of the foregoing embodiments.

[0135] The processor 401 described above can refer to one or more processors. For example, processor 401 may include one or more central processing units (CPUs), or it may include a CPU and a graphics processing unit (GPU), or it may include an application processor and a coprocessor (e.g., a microcontroller unit or neural network processor). When processor 401 includes multiple processors, these multiple processors may be integrated on the same chip or may be independent chips. A processor may include one or more physical cores, where a physical core is the smallest processing module.

[0136] As illustrated, the processor 401 can be implemented in at least one of the following hardware forms: Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), and Programmable Logic Array (PLA).

[0137] Processor 401 may integrate one or more of the following: a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Electronic devices may include one or more of the following: for example, smartphones, personal computers (PCs), mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable media players (PMPs), MPEG 1 audio layer 3 (Moving Picture Experts Group Audio Layer III) players, mobile medical devices, cameras, home appliances, medical devices, Internet of Things (IoT) devices, and wearable devices. Wearable devices may be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices may include, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted displays (HMDs). This electronic device can also be used in large servers, such as data centers or AI computers.

[0138] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes can be made in form and detail without departing from the spirit and scope of the embodiments of this application. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this application; therefore, the scope of protection of the embodiments of this application should be determined by the scope defined in the claims.

Claims

1. A temperature sensing circuit, characterized in that, include: An operational amplifier having a first input terminal connected to a first node and a second input terminal connected to a second node; A transistor array includes multiple transistors, and each transistor has a control terminal, a first terminal, and a second terminal. The control terminal is coupled to the second terminal and receives a preset voltage. Multiple sets of switching units, each set of switching units corresponding to one of the transistors, each set of switching units being directly connected to the first node and the second node, and each set of switching units being used to connect the first terminal of the corresponding transistor to the first node or the second node; Multiple preset resistors, each preset resistor corresponding to one of the transistors, each preset resistor being connected between each group of switching units and the first terminal of the corresponding transistor, so that the corresponding transistor is connected to the second node via the preset resistor; A current mirror is configured to provide a first bias current to the first node and a second bias current to the second node based on the output voltage of the operational amplifier, and to replicate the second bias current as a target current proportional to temperature. Each set of switching units responds to a control signal to connect the first terminal of the corresponding transistor to one of the first node or the second node at the same time. Each set of switching units includes: a first switch, which is connected between the first node and the first terminal of the corresponding transistor; and a second switch, which is connected between the second node and the corresponding preset resistor. At the same time, the first switches in the k1 group of switch units are all turned on, and the second switches in the k2 group of switch units are all turned on. k1 and k2 are both positive integers, and k2 > k1. The first switch and the second switch satisfy: Ron2 / Ron1 = k2 / k1, where Ron1 is the ideal on-resistance of the first switch and Ron2 is the ideal on-resistance of the second switch.

2. The temperature sensing circuit according to claim 1, characterized in that, Each of the transistors is the same size.

3. The temperature sensing circuit according to claim 1 or 2, characterized in that, The transistor includes a bipolar junction transistor, with the control terminal being the base, the first terminal being the emitter, and the second terminal being the collector.

4. The temperature sensing circuit according to claim 1, characterized in that, The first switch includes a first transmission gate, and the second switch includes a second transmission gate; wherein the size of the first transmission gate is k2 / k1 times the size of the second transmission gate.

5. The temperature sensing circuit according to claim 4, characterized in that, The size of the first transmission gate includes the channel width-to-length ratio of the MOS transistor constituting the first transmission gate, and the size of the second transmission gate includes the channel width-to-length ratio of the MOS transistor constituting the second transmission gate.

6. The temperature sensing circuit according to claim 1, characterized in that, The resistance value of each of the preset resistors is the same.

7. The temperature sensing circuit according to claim 1, characterized in that, The first node is directly connected to the first input terminal of the operational amplifier, and the second node is directly connected to the second input terminal of the operational amplifier.

8. The temperature sensing circuit according to claim 1, characterized in that, The multiple sets of switching units are configured as follows: During the dynamic element matching cycle, if one of the first switch and the second switch in each group of switching units is turned on, the other is turned off. The dynamic element matching cycle includes multiple control stages performed sequentially, and in each control stage, only the first switch in one set of switching units is turned on, while the first switches in the remaining sets of switching units are turned off, so that during the dynamic element matching cycle, each of the plurality of transistors is sequentially connected to the first node via the corresponding first switch, and the remaining transistors are connected to the second node via the corresponding second switch.

9. The temperature sensing circuit according to claim 8, characterized in that, The temperature sensing circuit also includes: A control circuit is provided to provide corresponding control signals to the plurality of switch units to control the state of the first switch and the state of the second switch.

10. The temperature sensing circuit according to claim 1, characterized in that, The current mirror includes: The first PMOS transistor has its control terminal connected to the output terminal of the operational amplifier, and its first terminal is connected to the first node. The second PMOS transistor has its control terminal connected to the control terminal of the first PMOS transistor, its first terminal connected to the second node, and the second terminal of the first PMOS transistor connected to the second terminal of the second PMOS transistor. The third PMOS transistor has its control terminal connected to the control terminal of the first PMOS transistor. The first terminal of the third PMOS transistor is used to output the target current, and the second terminal of the third PMOS transistor is connected to the second terminal of the first PMOS transistor.

11. The temperature sensing circuit according to claim 10, characterized in that, The first PMOS transistor has the same dimensions as the second PMOS transistor.

12. The temperature sensing circuit according to claim 11, characterized in that, The third PMOS transistor has the same dimensions as the second PMOS transistor.

13. The temperature sensing circuit according to claim 1, characterized in that, The temperature sensing circuit also includes: A current generation circuit is configured to connect to the first node and generate and output a reference current that is inversely proportional to temperature.

14. A temperature sensor, characterized in that, include: The temperature sensing circuit as described in any one of claims 1 to 13; The processing circuit is configured to generate and output temperature information based at least on the target current.

15. A storage device, characterized in that, include: Storage array; The temperature sensing circuit as described in any one of claims 1 to 13, or the temperature sensor as described in claim 14.

16. An electronic device, characterized in that, Includes the storage device as described in claim 15.

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