High-precision load resistance measurement circuit

Abstract

The application discloses a high-precision load resistance measurement circuit, comprising a reference current source generation module, a first operational amplifier, a power tube, a mirror tube and an ADC sampling module; the first end of the power tube and the first end of the mirror tube are used for connecting a power supply voltage; the controlled end of the power tube and the controlled end of the mirror tube are connected and the output end of the first operational amplifier is connected; the input end of the reference current source generation module is used for connecting a reference voltage; the reference current source generation module is arranged in a path between the second end of the mirror tube and the ground; the reference current source generation module is used for adjusting the current flowing through the path from the mirror tube to the ground into a corresponding reference current value based on the reference voltage; the noninverting input end of the first operational amplifier is connected with the second end of the mirror tube, the inverting input end of the first operational amplifier is connected with the second end of the power tube and the first end of a load; the second end of the load is grounded; and the input end of the ADC sampling module is connected with the inverting input end of the first operational amplifier.

Description

Technical Field

[0001] This invention relates to the field of load resistance measurement technology, and in particular to a high-precision load resistance measurement circuit. Background Technology

[0002] In modern electronic devices, accurate detection of load resistance is crucial for system status monitoring, fault prevention, and reliability improvement. Especially in high-current applications (e.g., load current greater than 1 ampere), real-time monitoring of load resistance can effectively assess the circuit's operating status, providing critical information for system protection and control.

[0003] In existing technologies, common methods for measuring the resistance of high-current loads include... Figure 1 As shown in the diagram, this scheme first turns on the power transistor, then uses a current sampling transistor to mirror the load driver transistor (power transistor). The current flowing through the load is obtained through the mirror ratio, and the load resistance is calculated by combining this with the load terminal voltage. Specifically, the load driver transistor and the sampling transistor form a current mirror structure. The load driver transistor operates in the linear region to reduce its on-resistance, and the sampling transistor mirrors the load current at a certain ratio. By detecting the current in the sampling transistor branch and combining it with the load voltage, the load resistance can be calculated. However, the above-mentioned existing technology suffers from insufficient current detection accuracy in practical applications. In this type of scheme, the detection of the load current depends on the mirror ratio of the current mirror. However, the mirror ratio is easily affected by various factors: on the one hand, inherent deviations in semiconductor manufacturing processes can lead to large dispersion in the mirror ratio between different chips; on the other hand, directly turning on the power transistor generates a large current, causing temperature changes, which in turn cause drift in the device's electrical parameters, further exacerbating the uncertainty of the mirror ratio. The combined effect of these factors makes it difficult to meet the requirements of high-precision applications in terms of current detection or control accuracy. Summary of the Invention

[0004] This invention proposes a high-precision load resistance measurement circuit, comprising: Reference current source generation module, first operational amplifier, power transistor, image transistor and ADC sampling module; The first terminal of the power transistor and the first terminal of the image transistor are used to connect to the power supply voltage; the controlled terminal of the power transistor and the controlled terminal of the image transistor are connected to each other and connected to the output terminal of the first operational amplifier. The input terminal of the reference current source generation module is used to connect to a reference voltage; the reference current source generation module is set in the path between the second terminal of the mirror tube and ground; the reference current source generation module is used to adjust the current flowing through the mirror tube to ground to the corresponding reference current value based on the reference voltage. The non-inverting input of the first operational amplifier is connected to the second terminal of the image transistor, and the inverting input of the first operational amplifier is connected to the second terminal of the power transistor and the first terminal of the load; the second terminal of the load is grounded. The input terminal of the ADC sampling module is connected to the inverting input terminal of the first operational amplifier.

[0005] Optionally, the reference current source generation module includes: Reference resistor, second operational amplifier, and first NMOS transistor; The non-inverting input of the second operational amplifier is used to connect to the reference voltage; the output of the second operational amplifier is connected to the gate of the first NMOS transistor; the drain of the first NMOS transistor is connected to the second terminal of the mirror transistor and the non-inverting input of the first operational amplifier; the source of the first NMOS transistor is connected to the first terminal of the reference resistor and the inverting input of the second operational amplifier. The second terminal of the reference resistor is grounded.

[0006] Optionally, the reference resistor is an adjustable zero-temperature-drift resistor.

[0007] Optionally, the high-precision load resistance measurement circuit further includes: a voltage source generation module; The voltage source generation module includes: a bandgap reference power supply, a reference voltage generation circuit, a first resistor, a second resistor, and a trimming resistor; The output terminal of the bandgap reference power supply is connected to the input terminal of the reference voltage generation circuit. The output terminal of the reference voltage generation circuit is connected to the first terminal of the first resistor. The second terminal of the first resistor is connected to the first terminal of the adjustment resistor and the non-inverting input terminal of the second operational amplifier. The second terminal of the adjustment resistor is connected to the first terminal of the second resistor, and the second terminal of the second resistor is grounded. The bandgap reference power supply is used to output the original reference voltage; The reference voltage generating circuit is used to convert the original reference voltage into a reference voltage and then output it.

[0008] Optionally, the high-precision load resistance measurement circuit further includes: Transmission gate array circuit and power transistor drive control module; The transmission gate array circuit is disposed in the path between the output terminal of the second operational amplifier and the controlled terminal of the power transistor; the transmission gate array circuit is used to open the path between the output terminal of the second operational amplifier and the controlled terminal of the power transistor when a detection enable signal is received. The output terminal of the power transistor drive control module is connected to the controlled terminal of the power transistor and the controlled terminal of the mirror transistor. The power transistor drive control module is used to stop outputting load control signals upon receiving the detection enable signal.

[0009] Optionally, the transmission gate array circuit includes: First transmission gate, second transmission gate, and third transmission gate; The first transmission terminal of the first transmission gate is connected to the output terminal of the first operational amplifier, and the second transmission terminal is connected to the second transmission terminal of the second transmission gate and the second transmission terminal of the third transmission gate; the first transmission terminal of the second transmission gate is connected to the second terminal of the mirror transistor and the non-inverting input terminal of the first operational amplifier; the first transmission terminal of the third transmission gate is connected to the controlled terminal of the power transistor, the controlled terminal of the mirror transistor, and the output terminal of the power transistor drive control module.

[0010] Optionally, the power transistor drive control module includes: Logic control circuit and push-pull output circuit; The input terminal of the push-pull output circuit is connected to the power supply voltage, and the output terminal is connected to the controlled terminal of the power transistor and the controlled terminal of the image transistor. The first output terminal of the logic control circuit is connected to the controlled terminal of the pull-up transistor in the push-pull output circuit, and the second output terminal of the logic control circuit is connected to the controlled terminal of the pull-down transistor in the push-pull output circuit. The logic control circuit is used to control the pull-up transistor and the pull-down transistor to turn off when a detection enable signal is received.

[0011] Optionally, the control terminal of the third transmission gate is used to receive the first timing signal; the inverting control terminal of the third transmission gate is used to receive the first inverted timing signal. The control terminal of the first transmission gate is used to receive the second timing signal; the inverting control terminal of the first transmission gate is used to receive the second inverted timing signal. The inverting control terminal of the second transmission gate is used to receive the third timing signal; the control terminal of the second transmission gate is used to receive the third inverting timing signal.

[0012] Optionally, the high-precision load resistance measurement circuit further includes: a third NMOS transistor and a sixth resistor; The source of the third NMOS transistor is connected to the inverting input of the first operational amplifier, and the drain is connected to the first terminal of the sixth resistor; the second terminal of the sixth resistor is connected to the second terminal of the power transistor. The gate of the third NMOS transistor is used to receive the first timing signal.

[0013] Optionally, the high-precision load resistance measurement circuit further includes: an electrostatic protection circuit; The first terminal of the electrostatic protection circuit is connected to the first terminal of the sixth resistor, and the second terminal is grounded.

[0014] The high-precision load resistance measurement circuit provided by this invention improves the current mirror accuracy by forcing the drain-source voltage of the image transistor and the power transistor to be equal through the first operational amplifier AMP1. It also provides a precise and stable reference current in conjunction with a reference current source generation module. This reference current is adjustable, which solves the problem of poor consistency in the high-precision mirror ratio of the detection current between chips. By applying a constant reference current of a certain multiple to the load, the temperature change caused by the large current generated by directly turning on the power transistor is avoided. In summary, this achieves high-precision mirroring of the detection current, solving the technical problem of insufficient detection accuracy caused by process deviations, temperature changes, power supply voltage fluctuations, and other factors in the prior art. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of an embodiment of the high-precision load resistance measurement circuit of the present invention; Figure 2 This is a schematic diagram of another embodiment of the high-precision load resistance measurement circuit of the present invention; Figure 3 This is a schematic diagram of another embodiment of the high-precision load resistance measurement circuit of the present invention; Figure 4 This is a schematic diagram of another embodiment of the high-precision load resistance measurement circuit of the present invention; Figure 5 This is a schematic diagram of another embodiment of the high-precision load resistance measurement circuit of the present invention; Figure 6 This is a schematic diagram of another embodiment of the high-precision load resistance measurement circuit of the present invention; Figure 7 This is a schematic diagram of another embodiment of the high-precision load resistance measurement circuit of the present invention; Figure 8 This is a schematic diagram of another embodiment of the high-precision load resistance measurement circuit of the present invention.

[0017] Explanation of icon numbers: R1-R6, first resistor to sixth resistor; R_meas, reference resistor; MN1-MN3, first NMOS transistor to third NMOS transistor; AMP1-AMP2, first operational amplifier to second operational amplifier; TG1-TG4, first transmission gate to fourth transmission gate; R_trim, trimming resistor; RL, load; MP1-MP2, first PMOS transistor to second PMOS transistor.

[0018] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0021] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0022] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0023] This invention proposes a high-precision load resistance measurement circuit. In the first embodiment, as shown... Figure 2 As shown, the high-precision load resistance measurement circuit includes: Reference current source generation module, first operational amplifier AMP1, power transistor, image transistor and ADC sampling module; The first terminal of the power transistor and the first terminal of the image transistor are used to connect to the power supply voltage; the controlled terminal of the power transistor and the controlled terminal of the image transistor are connected to each other and connected to the output terminal of the first operational amplifier AMP1. The input terminal of the reference current source generation module is used to connect to a reference voltage; the reference current source generation module is set in the path between the second terminal of the mirror tube and ground; the reference current source generation module is used to adjust the current flowing through the mirror tube to ground to the corresponding reference current value based on the reference voltage. The non-inverting input of the first operational amplifier AMP1 is connected to the second terminal of the image transistor, and the inverting input of the first operational amplifier AMP1 is connected to the second terminal of the power transistor and the first terminal of the load RL; the second terminal of the load RL is grounded. The input terminal of the ADC sampling module is connected to the inverting input terminal of the first operational amplifier AMP1.

[0024] It should be explained that both the power transistor and the image mirror are PMOS transistors. The first terminal (source) of both the power transistor and the image mirror are connected to the power supply voltage VDD to receive power. The controlled terminal (gate) of the power transistor and the controlled terminal (gate) of the image mirror are interconnected and connected to the output of the first operational amplifier AMP1.

[0025] A reference current source generation module is connected between the second terminal (drain) of the image transistor and ground. This module receives a reference voltage and, based on this reference voltage, adjusts the current flowing through the image transistor to ground to a precise reference current value. In this embodiment, the reference current source generation module can be implemented in various ways, such as a voltage-to-current conversion circuit composed of an operational amplifier and resistors, which can generate a high-precision reference current independent of process and temperature. The non-inverting input of the first operational amplifier AMP1 is connected to the drain of the image transistor, and its inverting input is connected to the drain of the power transistor, and simultaneously connected to the first terminal of the load. The second terminal of the load is grounded. The input of the ADC sampling module is connected to the inverting input of the first operational amplifier AMP1, and is used to acquire the voltage signal at the drain of the power transistor (i.e., the voltage Vout across the load).

[0026] The following section, based on the circuit structure described above, elaborates on its working principle and the technical mechanism for achieving high-precision load resistance measurement.

[0027] First, the reference current source generation module generates a precise reference current IR. This reference current IR flows through the mirror transistor, meaning the drain current of the mirror transistor equals IR. Since the gates of the power transistor and the mirror transistor are connected and their sources are shared by VDD, they form a current mirror structure. Ideally, if the channel length modulation effect is ignored, the ratio of the drain currents of the power transistor and the mirror transistor should be strictly equal to their width-to-length ratio, i.e., the drain current of the power transistor IL = X * IR, where X is the mirror ratio. However, in actual circuits, MOSFETs exhibit a channel length modulation effect, and their drain current is controlled not only by the gate-source voltage but also by the drain-source voltage. When the power supply voltage VDD or the load RL changes, the drain-source voltage of the power transistor (i.e., VDD - Vout) will change accordingly. If the drain-source voltage of the mirror transistor is not equal to that of the power transistor, the ratio of their drain currents will deviate from their width-to-length ratio, thus causing an error in the proportional relationship between the sensed current IL and the reference current IR.

[0028] To address the aforementioned problems, this invention introduces a first operational amplifier AMP1. The non-inverting input of AMP1 is connected to the drain of the image transistor, and the inverting input is connected to the drain of the power transistor (Vout). Its output is connected to the gates of both the power transistor and the image transistor. Utilizing the "virtual short" characteristic of operational amplifiers, AMP1 forces the voltages at its non-inverting and inverting inputs to be equal, i.e., forces the drain voltage of the image transistor to be equal to the drain voltage (Vout) of the power transistor. Simultaneously, since the sources of both the power transistor and the image transistor are connected to VDD, their drain-source voltages are also necessarily equal, both being VDD - Vout. Through this structure, this invention eliminates the influence of the drain-source voltage difference between the power transistor and the image transistor on the current mirroring accuracy. At this point, the ratio of the drain currents of the power transistor and the image transistor is strictly equal to the ratio of their width-to-length ratios, i.e., IL = X * IR. Thus, a precise proportional relationship is established between the detection current IL and the reference current IR.

[0029] Furthermore, the reference current IR provided by the reference current source generation module is accurate and stable. Through proper design, IR can be made independent of factors such as process deviations and temperature changes. Therefore, the detection current IL also possesses high accuracy and high stability, and does not drift with power supply voltage fluctuations, temperature changes, or changes in load size. After obtaining the accurate detection current IL, the load resistance RL is calculated as follows: the ADC sampling module acquires the load terminal voltage Vout. Since the detection current IL is a known accurate value, according to Ohm's law, the load resistance RL = Vout / IL. Compared to existing technologies that require simultaneous acquisition of the load voltage and the sampling tube branch voltage and subsequent division, this invention only requires acquisition of a single voltage signal to complete the measurement, simplifying the measurement process and reducing the risk of calculation errors.

[0030] In summary, the high-precision load resistance measurement circuit provided by this invention achieves high-precision mirroring of the detection current by forcing the drain-source voltage of the image transistor and the power transistor to be equal through the first operational amplifier AMP1, and by providing a precise and stable reference current in conjunction with the reference current source generation module. This solves the technical problem of insufficient detection accuracy caused by factors such as process deviation, temperature change, and power supply voltage fluctuation in the prior art.

[0031] It should be noted that the use of PMOS transistors for the power transistor and the image transistor in this embodiment is merely an example. In other embodiments of the present invention, the power transistor and the image transistor can also be controllable devices such as NMOS transistors or bipolar transistors. Only the circuit connection method needs to be adjusted accordingly to ensure that the first operational amplifier AMP1 can force the output voltages of both transistors to be equal, thus achieving the same function. Furthermore, the specific circuit structure of the reference current source generation module can be modified in various ways according to actual accuracy requirements and process conditions. As long as it can generate an accurate and stable reference current, it does not depart from the protection scope of the present invention.

[0032] In one example, to facilitate direct calculation of the load resistance value in the digital domain, the high-precision load resistance measurement circuit can be designed with parameters in conjunction with the conversion characteristics of the ADC sampling module.

[0033] Specifically, the ADC sampling module is assumed to be an N-bit successive approximation analog-to-digital converter, and its reference voltage is the reference voltage VREF output by the reference voltage generation circuit. The ADC sampling module acquires the voltage Vout at the inverting input of the first operational amplifier AMP1 and converts it into a digital code value reg_adc, with the conversion relationship satisfying: According to Ohm's law, the load resistance RL satisfies: RL = Vout / IL, where IL is the sensing current flowing through the load, and its expression is: , In the formula, VR is the reference voltage connected to the input terminal of the reference current source generation module, R_meas is the resistance value of the reference resistor, and X is the width-to-length ratio of the power transistor and the image transistor.

[0034] Substituting the expression for Vout into the RL expression, we get: , Further organized as follows: , As can be seen from the above formula, if the detection current IL and the reference voltage VREF are designed reasonably, the denominator can be reduced to a certain value. If K is a preset constant (e.g., 1000), then the load resistance RL can be directly obtained by dividing the ADC conversion code value by K, that is: This design approach offers the following technical advantages: Firstly, the calculation of the load resistance does not require floating-point division, only integer division or shift operations, facilitating digital circuit implementation and reducing system complexity. Secondly, the calculation results are largely independent of factors such as process deviations, temperature variations, and power supply voltage fluctuations, further improving the accuracy and consistency of the measurement results. It should be noted that the specific value of the preset constant K can be flexibly set according to actual application requirements. For example, the precise configuration of K can be achieved by adjusting the reference resistor R_meas or adjusting the reference voltage VR.

[0035] In the second embodiment, as Figure 3 As shown, the reference current source generation module includes: Reference resistor R_meas, second operational amplifier AMP2, and first NMOS transistor MN1; The non-inverting input of the second operational amplifier AMP2 is used to connect to the reference voltage; the output of the second operational amplifier AMP2 is connected to the gate of the first NMOS transistor MN1; the drain of the first NMOS transistor MN1 is connected to the second terminal of the mirror transistor and the non-inverting input of the first operational amplifier AMP1; the source of the first NMOS transistor MN1 is connected to the first terminal of the reference resistor R_meas and the inverting input of the second operational amplifier AMP2. The second terminal of the reference resistor R_meas is grounded.

[0036] It should be explained that this embodiment provides a preferred implementation structure for the reference current source generation module. Specifically, the non-inverting input of the second operational amplifier AMP2 is used to connect a reference voltage VR. This reference voltage can be generated by a bandgap reference circuit, possessing high accuracy characteristics independent of process and temperature, providing a stable voltage reference for the entire measurement circuit. The drain of the first NMOS transistor MN1 is connected to the second terminal of the mirror transistor (i.e., the drain of the mirror transistor), and also to the non-inverting input of the first operational amplifier AMP1. The source of the first NMOS transistor MN1 is connected to the first terminal of the reference resistor R_meas, and also to the inverting input of the second operational amplifier AMP2. The second terminal of the reference resistor R_meas is grounded. The output of the second operational amplifier AMP2 is connected to the gate of the first NMOS transistor MN1.

[0037] The above connection method constitutes a closed-loop feedback structure, and its working principle is as follows: The second operational amplifier AMP2 utilizes its "virtual short" characteristic to force the voltage at its non-inverting input terminal to be equal to the voltage at its inverting input terminal. Since the non-inverting input terminal of the second operational amplifier AMP2 is connected to the reference voltage VR, and its inverting input terminal is connected to the source of the first NMOS transistor MN1 (i.e., the first terminal of the reference resistor R_meas), the voltage at the first terminal of the reference resistor R_meas is precisely clamped to VR. Since the second terminal of the reference resistor R_meas is grounded, the voltage across the reference resistor R_meas is VR. According to Ohm's law, the current flowing through the reference resistor R_meas is VR divided by the resistance of the reference resistor R_meas. This current is the source current of the first NMOS transistor MN1. During normal operation, the first NMOS transistor MN1 operates in the saturation region, and its drain current is equal to its source current (ignoring the channel length modulation effect). Therefore, the drain current of the first NMOS transistor MN1 is also equal to VR divided by the resistance of the reference resistor R_meas. The drain current is the reference current IR output by the reference current source generation module, and its expression is IR = VR / R_meas, where R_meas is the resistance value of the reference resistor.

[0038] With the above structure, the reference current source generation module accurately converts the input reference voltage VR into a reference current IR. The accuracy of this reference current depends on two factors: the accuracy of the reference voltage VR and the accuracy of the reference resistor R_meas. In practical applications, high accuracy of the reference current can be ensured through the following methods: First, the reference voltage VR can be generated by a bandgap reference circuit, which can output a stable voltage that is basically independent of temperature and power supply voltage changes, thereby eliminating the influence of environmental factors on the reference current.

[0039] Second, the reference resistor R_meas can be a high-precision resistor type, such as a thin-film resistor or a laser-adjusted diffused resistor. In this embodiment, the reference resistor R_meas is preferably an adjustable zero-temperature-drift resistor, that is, its resistance value can be adjusted by means of adjustment during chip manufacturing or mass production testing, and its resistance value changes very little with temperature, thereby ensuring that the reference current remains highly stable over the entire temperature range.

[0040] It should be noted that in this embodiment, the negative feedback loop formed by the first NMOS transistor MN1 and the second operational amplifier AMP2 not only achieves accurate voltage-to-current conversion but also ensures that the output reference current IR has a high output impedance. This means that even if the drain voltage of the mirror transistor changes due to load variations or power supply fluctuations, the reference current IR remains stable and will not generate additional errors due to changes in the operating point of subsequent circuits. In summary, the reference current source generation module provided in this embodiment, through the negative feedback structure formed by the second operational amplifier AMP2 and the first NMOS transistor MN1, accurately converts the high-precision reference voltage VR into the reference current IR, and utilizes the adjustable reference resistor R_meas to eliminate the influence of process deviations. This provides a high-precision reference current source independent of process and temperature for the entire load resistance measurement circuit, laying a solid foundation for the subsequent realization of high-precision current mirroring.

[0041] like Figure 4 As shown, in one example, the high-precision load resistance measurement circuit further includes: a voltage source generation module; The voltage source generation module includes: a bandgap reference power supply, a reference voltage generation circuit, a first resistor R1, a second resistor R2, and a trimming resistor R_trim; The output terminal of the bandgap reference power supply is connected to the input terminal of the reference voltage generation circuit. The output terminal of the reference voltage generation circuit is connected to the first terminal of the first resistor R1. The second terminal of the first resistor R1 is connected to the first terminal of the trimming resistor R_trim and the non-inverting input terminal of the second operational amplifier AMP2. The second terminal of the trimming resistor R_trim is connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2 is grounded. The bandgap reference power supply is used to output the original reference voltage; The reference voltage generating circuit is used to convert the original reference voltage into a reference voltage and then output it.

[0042] It should be explained that the voltage source generation module is used to provide a high-precision, adjustable reference voltage that is unaffected by the process to the reference current source generation module.

[0043] The voltage source generation module specifically includes a bandgap reference power supply, a reference voltage generation circuit, a first resistor R1, a second resistor R2, and a trimming resistor R_trim. Specifically, the output of the bandgap reference power supply is connected to the input of the reference voltage generation circuit. The bandgap reference power supply outputs a raw reference voltage, which is essentially independent of process, temperature, and power supply voltage variations, and is a commonly used high-precision voltage source in integrated circuits. The reference voltage generation circuit receives this raw reference voltage and converts it into the desired reference voltage VREF before outputting it. The reference voltage generation circuit may include sub-circuits such as level conversion and buffer amplification to adjust the output voltage of the bandgap reference power supply to a voltage level suitable for the operation of subsequent circuits.

[0044] The output of the reference voltage generation circuit is connected to the first terminal of the first resistor R1. The second terminal of the first resistor R1 is connected to the first terminal of the adjustment resistor R_trim, and simultaneously connected to the non-inverting input of the second operational amplifier AMP2 (i.e., the reference voltage input of the reference current source generation module). The second terminal of the adjustment resistor R_trim is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is grounded. The first resistor R1, the adjustment resistor R_trim, and the second resistor R2 together form a series voltage divider network, which divides the VREF voltage output by the reference voltage generation circuit to generate the final reference voltage VR. Specifically, the reference voltage VR is the sum of the voltages across the adjustment resistor R_trim and the second resistor R2, and its expression is: VR = VREF × (R2 + R_trim) / (R1 + R2 + R_trim), Where R1 is the resistance value of the first resistor, R2 is the resistance value of the second resistor, and R_trim is the resistance value of the adjustment resistor.

[0045] The voltage divider network described above allows for precise adjustment of the reference voltage VR. The trimming resistor R_trim is a variable resistor whose value can be set during chip manufacturing or mass production testing using methods such as laser trimming, fuse trimming, or electrical programming trimming. By changing the value of the trimming resistor R_trim, the voltage division ratio can be adjusted, thereby calibrating the final reference voltage VR to the target value. This adjustable design effectively compensates for resistance value errors in the voltage divider caused by process variations, ensuring that the reference voltage VR output by each chip is precisely consistent with the design value.

[0046] Since the reference voltage VR is directly used as the input voltage of the reference current source generation module, its accuracy directly affects the accuracy of the reference current IR. The voltage source generation module provided in this embodiment utilizes the inherent characteristics of the bandgap reference power supply to ensure that the reference voltage VR is independent of temperature and power supply voltage. Furthermore, the adjustable voltage divider network eliminates the influence of process deviations on the absolute value of the reference voltage. Therefore, the voltage source generation module provides a high-precision, calibrable reference voltage source for the subsequent reference current source generation module, laying a solid foundation for achieving high-precision measurement of the entire load resistance measurement circuit that is independent of process and temperature. It should be noted that the specific resistance values ​​of the first resistor R1, the second resistor R2, and the adjustment resistor R_trim in this embodiment can be selected according to actual design requirements. Generally, to reduce the load effect of the voltage divider network on VREF, the first resistor R1, the second resistor R2, and the adjustment resistor R_trim should be resistors with relatively large resistance values. In addition, the adjustment range of the adjustment resistor R_trim should cover the voltage offset that may be caused by process deviations to ensure that VR can be calibrated to the target value at all process angles.

[0047] In summary, the voltage source generation module provided in this embodiment provides an original reference voltage that is independent of temperature and power supply voltage through a bandgap reference power supply and a reference voltage generation circuit. Then, through a voltage divider network composed of a first resistor R1, a second resistor R2, and an adjustable resistor R_trim, it achieves high-precision generation and flexible calibration of the reference voltage. This provides a stable, accurate, and mass-producible adjustable voltage reference for the reference current source generation module, thereby ensuring the high-precision characteristics of the entire load resistance measurement circuit from the source.

[0048] In the third embodiment, as Figure 5 As shown, the high-precision load resistance measurement circuit further includes: Transmission gate array circuit and power transistor drive control module; The transmission gate array circuit is disposed in the path between the output terminal of the second operational amplifier AMP2 and the controlled terminal of the power transistor; the transmission gate array circuit is used to open the path between the output terminal of the second operational amplifier AMP2 and the controlled terminal of the power transistor when a detection enable signal is received. The output terminal of the power transistor drive control module is connected to the controlled terminal of the power transistor and the controlled terminal of the mirror transistor. The power transistor drive control module is used to stop outputting load control signals upon receiving the detection enable signal.

[0049] It should be explained that this embodiment introduces a transmission gate array circuit and a power transistor drive control module to achieve switching control between the detection mode and the drive mode. Specifically, the high-precision load resistance measurement circuit also includes a transmission gate array circuit and a power transistor drive control module to achieve flexible switching between the load resistance detection mode and the normal load drive mode.

[0050] A transmission gate array (GGA) circuit is positioned in the path between the output of the first operational amplifier AMP1 and the controlled terminal of the power transistor. Specifically, one end of the GGA circuit is connected to the output of the first operational amplifier AMP1, and the other end is connected to the controlled terminal of the power transistor. The GGA circuit is in a conducting state when it receives a detection enable signal, connecting the output of the first operational amplifier AMP1 to the controlled terminal of the power transistor; it is in a turning-off state when no detection enable signal is received, cutting off the path. The output of the power transistor drive control module is connected to the controlled terminal of the power transistor, and also to the controlled terminal of the image transistor. The power transistor drive control module outputs a load control signal in normal operating mode, driving the power transistor to provide a large current to the load. When a detection enable signal is received, the power transistor drive control module stops outputting the load control signal, causing its output to be connected to the power supply only through a pull-up resistor (resistance > 10KΩ), thus avoiding conflict with the transmission gate array circuit simultaneously driving the power transistor control terminal.

[0051] Through the above structure, this embodiment achieves switching control of the circuit operating mode. When it is necessary to measure the load resistance, the detection enable signal is set to an active state. At this time, the transmission gate array circuit is turned on, connecting the output terminal of the first operational amplifier AMP1 to the controlled terminal of the power transistor; simultaneously, the power transistor drive control module stops outputting, and its output terminal is in a high-impedance state. In this state, the voltage at the controlled terminal of the power transistor is controlled by the first operational amplifier AMP1, the power transistor operates in the saturation region, and the entire circuit enters a high-precision current mirror detection state, as described above, enabling high-precision measurement of the load resistance.

[0052] When normal load driving is required, the detection enable signal is set to an invalid state. At this time, the transmission gate array circuit is turned off, disconnecting the connection between the first operational amplifier AMP1 and the power transistor control terminal; the power transistor drive control module resumes normal operation, outputting a load control signal to drive the power transistor. In this state, the controlled terminal of the power transistor is controlled by the power transistor drive control module, and the power transistor can operate in the linear region or switching state according to the actual application requirements to provide sufficient drive capability to deliver a large current to the load.

[0053] The advantages of the above mode switching design are as follows: on the one hand, it integrates the high-precision load resistance detection function and the high-current drive function into the same circuit, realizing function reuse and reducing system cost and chip area; on the other hand, through the coordinated control of the transmission gate array circuit and the power tube drive control module, it ensures that the two modes work mutually exclusively, avoids signal conflicts, and ensures the stability and reliability of the circuit under different working states.

[0054] It should be noted that the detection enable signal can be provided by an external controller (such as a microcontroller, digital signal processor, or dedicated logic circuit), and its effective level can be flexibly defined according to the actual circuit design (e.g., active high or active low). In this embodiment, the detection enable signal is active in detection mode and inactive in drive mode, but this should not be used to limit the scope of protection of this invention. Furthermore, the mode switching structure introduced in this embodiment allows the detection current flowing through the load to be independently determined by an internal reference current source, independent of the drive current during normal load operation. This characteristic has significant engineering implications: in mass production testing, since the detection current can be designed to be much smaller than the rated operating current of the load (e.g., less than 500 mA), the calibration difficulties caused by the inability of test instrument probes or sockets to handle large currents, as seen in existing technologies, are avoided, providing convenient conditions for mass production calibration of each chip.

[0055] In summary, this implementation method achieves flexible switching between detection mode and driving mode through the coordinated setting of transmission gate array circuit and power transistor drive control module. It retains the high-precision measurement capability of the aforementioned scheme, while also taking into account the high-current drive function, and creates favorable conditions for mass production testing and calibration.

[0056] In one example, such as Figure 6 As shown, the transmission gate array circuit includes: First transmission gate TG1, second transmission gate TG2, and third transmission gate TG3; The first transmission terminal of the first transmission gate TG1 is connected to the output terminal of the first operational amplifier AMP1, and the second transmission terminal is connected to the second transmission terminal of the second transmission gate TG2 and the second transmission terminal of the third transmission gate TG3; the first transmission terminal of the second transmission gate TG2 is connected to the second terminal of the mirror transistor and the non-inverting input terminal of the first operational amplifier AMP1; the first transmission terminal of the third transmission gate TG3 is connected to the controlled terminal of the power transistor, the controlled terminal of the mirror transistor, and the output terminal of the power transistor drive control module.

[0057] It should be explained that the transmission gate array circuit described in this example uses a switching network composed of three transmission gates, specifically including the first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3, to realize the switching control of different working stages in the detection mode.

[0058] The specific connection relationships of the three transmission gates are as follows: The first transmission terminal of the first transmission gate TG1 is connected to the output terminal of the first operational amplifier AMP1. The second transmission terminal of the first transmission gate TG1 is connected to the second transmission terminals of the second transmission gate TG2 and the third transmission gate TG3. In other words, the second transmission terminal of the first transmission gate TG1 is interconnected with the second transmission terminals of the second transmission gate TG2 and the third transmission gate TG3, forming a common node. The first transmission terminal of the second transmission gate TG2 is connected to the second terminal of the image transistor (i.e., the drain of the image transistor) and simultaneously connected to the non-inverting input terminal of the first operational amplifier AMP1. The first transmission terminal of the third transmission gate TG3 is connected to the controlled terminal of the power transistor, the controlled terminal of the image transistor, and the output terminal of the power transistor drive control module.

[0059] Through the above connection method, this embodiment utilizes the coordinated switching control of three transmission gates to realize the sequential switching between the two working stages of "circuit start-up" and "precise detection" in the detection mode.

[0060] Specifically, after the circuit enters the detection mode, it first enters the circuit startup phase. In this phase, the first transmission gate TG1 is turned off, the second transmission gate TG2 is turned on, and the third transmission gate TG3 is turned on. At this time, the second transmission gate TG2 connects the drain of the image transistor and the output of the first operational amplifier AMP1 (through a common node and the third transmission gate TG3) to the controlled terminal of the power transistor. Because the drain and source of the image transistor form a low-impedance path through the second transmission gate TG2 and other paths, the drain-source voltage of the image transistor is forcibly pulled low, enabling the first operational amplifier AMP1 to start normally and avoiding the operational amplifier failing to start normally due to uncertain initial states.

[0061] After the circuit startup phase is completed, the circuit enters the precision detection phase. In this phase, the first transmission gate TG1 is turned on, the second transmission gate TG2 is turned off, and the third transmission gate TG3 remains on. At this time, the output of the first operational amplifier AMP1 is directly connected to the controlled terminal of the power transistor through the first transmission gate TG1 and the third transmission gate TG3, forming a complete feedback loop. Simultaneously, the second transmission gate TG2 is turned off, cutting off the connection between the drain of the mirror transistor and the common node, allowing the mirror transistor to enter normal operating mode. In this state, the first operational amplifier AMP1 utilizes its "virtual short" characteristic to force the drain voltage of the mirror transistor to be equal to the drain voltage of the power transistor, thereby achieving high-precision current mirroring as described above.

[0062] The three-transmission gate structure used in this embodiment has the following technical advantages: First, by using phased control, the risk that the first operational amplifier AMP1 would fail to start due to the lack of a feedback loop at the moment of circuit startup is avoided.

[0063] Secondly, the coordinated operation of the three transmission gates enables flexible switching of the signal path. During the circuit startup phase, the second transmission gate TG2 and the third transmission gate TG3 work together to quickly pull the drain voltage of the image transistor to a reasonable potential; during the precise detection phase, the first transmission gate TG1 and the third transmission gate TG3 work together to establish a complete feedback path. This time-division multiplexing design fully utilizes the characteristics of fast switching speed, low on-resistance, and no threshold loss in signal transmission of the transmission gates, ensuring the accurate transmission of analog signals.

[0064] Third, the transmission gate is composed of complementary NMOS and PMOS transistors connected in parallel, enabling full-swing transmission of the input signal without the threshold voltage loss problem associated with switching a single MOS transistor. This is particularly important for applications requiring precise transmission of analog voltage signals, ensuring signal integrity between the input and output terminals of the first operational amplifier AMP1.

[0065] It should be noted that in this embodiment, the on and off states of the first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3 are controlled by corresponding control signals (such as timing signals). The timing coordination of the control signals can be designed according to the actual circuit requirements. As long as the bias establishment stage and the accurate detection stage are executed sequentially, the technical effects described in this embodiment can be achieved.

[0066] In summary, this embodiment achieves sequential switching between the two stages of circuit startup and precise detection in the detection mode through specific connection and coordinated control of the first transmission gate TG1, the second transmission gate TG2, and the third transmission gate TG3. This ensures the reliable startup and stable operation of the high-precision current mirror circuit and provides structural protection for high-precision measurement of load resistance.

[0067] In another example, such as Figure 7 As shown, the power transistor drive control module includes: Logic control circuit and push-pull output circuit; The input terminal of the push-pull output circuit is connected to the power supply voltage, and the output terminal is connected to the controlled terminal of the power transistor and the controlled terminal of the image transistor. The first output terminal of the logic control circuit is connected to the controlled terminal of the pull-up transistor in the push-pull output circuit, and the second output terminal of the logic control circuit is connected to the controlled terminal of the pull-down transistor in the push-pull output circuit. The logic control circuit is used to control the pull-up transistor and the pull-down transistor to turn off when a detection enable signal is received.

[0068] It should be explained that the logic control circuit and the push-pull output circuit work together to provide a drive signal to the power transistor in drive mode, and to connect the output terminal to the power supply only through a pull-up resistor in detection mode to avoid conflict with the detection path.

[0069] The input of the push-pull output circuit is connected to the power supply voltage VDD, and its output is connected to the controlled terminal of the power transistor and also to the controlled terminal of the image transistor. The push-pull output circuit uses a classic push-pull structure, typically including one pull-up transistor and one pull-down transistor. The control terminals of the pull-up and pull-down transistors receive control signals from the logic control circuit, and by alternately turning them on or off, the output can provide a high-level or low-level drive signal. When the pull-up transistor is on and the pull-down transistor is off, the output is pulled high to VDD; when the pull-up transistor is off and the pull-down transistor is on, the output is pulled low to ground; when both the pull-up and pull-down transistors are off, the output is only connected to the power supply through the pull-up resistor. The logic control circuit has a first output and a second output. The first output is connected to the control terminal of the pull-up transistor in the push-pull output circuit to control its on / off state; the second output is connected to the control terminal of the pull-down transistor in the push-pull output circuit to control its on / off state. The logic control circuit receives the detection enable signal and the load control signal, and generates the corresponding output control level based on these input signals.

[0070] The core function of the logic control circuit is as follows: When a detection enable signal is received (i.e., the circuit enters detection mode), the logic control circuit simultaneously controls the pull-up and pull-down transistors to turn off through its first and second output terminals. In this state, both the pull-up and pull-down transistors of the push-pull output circuit are in the off state, and its output terminal is in a high-impedance state. Since the controlled terminal of the power transistor is connected to both the output terminal of the push-pull output circuit and the transmission gate array circuit (through the third transmission gate TG3), when the output terminal of the push-pull output circuit is only pulled up to the power supply by the pull-up resistor, the transmission gate array circuit can transmit the output signal of the first operational amplifier AMP1 to the controlled terminal of the power transistor without conflict, thereby achieving precise control of the gate voltage of the power transistor, enabling the power transistor to enter the saturation region and complete high-precision current detection. When no detection enable signal is received (i.e., the circuit enters drive mode), the logic control circuit normally controls the conduction and turn-off of the pull-up and pull-down transistors according to the load control signal (e.g., PWM signal or enable signal). At this time, the transmission gate array circuit is in the off state, cutting off the connection between the first operational amplifier AMP1 and the power transistor control terminal. The drive signal output by the push-pull output circuit directly controls the gate of the power transistor, making the power transistor work in the linear region or in the switching state, and providing the required large current to the load.

[0071] The structure combining logic control circuit and push-pull output circuit used in this embodiment has the following technical advantages: First, electrical isolation between the driving path and the detection path is achieved. By simultaneously turning off the pull-up and pull-down transistors of the push-pull output circuit in detection mode, its output is connected to the power supply only through the pull-up resistor. This effectively avoids signal conflicts caused by the push-pull output circuit and the transmission gate array circuit simultaneously driving the power transistor control terminal. This ensures that the gate voltage of the power transistor in detection mode is completely controlled by the first operational amplifier AMP1, thereby guaranteeing the high accuracy of the current mirror.

[0072] Second, the structure is simple and reliable. The logic control circuit can be implemented using basic digital logic gates (such as AND gates, OR gates, inverters, etc.), and the push-pull output circuit can use a standard CMOS inverter structure. There is no need for complex analog circuit design, which makes it easy to integrate and consumes less power.

[0073] Third, it has a fast response speed. The pull-up and pull-down transistors in the push-pull output circuit can quickly switch states under the drive of the logic control circuit. When switching between detection mode and drive mode, it can quickly establish or cut off the drive path, meeting the requirements of mode switching speed in practical applications.

[0074] It should be noted that the specific types of pull-up and pull-down transistors described in this embodiment can be designed according to the process technology. In standard CMOS processes, pull-up transistors are typically PMOS transistors, and pull-down transistors are typically NMOS transistors, forming a complementary push-pull structure. The logic control circuit can generate corresponding control levels based on the logical relationship between the detection enable signal and the load control signal, ensuring that the pull-up and pull-down transistors are simultaneously turned off in detection mode, and that the circuit drives normally according to the load control signal in drive mode.

[0075] In summary, this embodiment, through the coordinated arrangement of logic control circuit and push-pull output circuit, realizes the flexible switching between the normal driving function of power transistor in drive mode and the power supply function of output terminal through pull-up resistor in detection mode, providing structural guarantee for the reliable switching of high-precision load resistance measurement circuit between detection mode and drive mode.

[0076] In one example, the logic control circuit includes: AND gate, OR gate, fourth transmission gate TG4, and first PMOS transistor; The AND gate has three input terminals; The first input terminal of the OR gate is used to receive a control signal, and the second input terminal is connected to the output terminal of the AND gate and the controlled terminal of the pull-down transistor; the output terminal of the OR gate is connected to the first transmission terminal of the fourth transmission gate TG4 and the first input terminal of the AND gate; the second input terminal of the AND gate is used to receive a control signal. The control terminal of the fourth transmission gate TG4 is connected to the gate of the first PMOS transistor, and the second transmission terminal of the fourth transmission gate TG4 is connected to the drain of the first PMOS transistor and the controlled terminal of the pull-up transistor; the source of the first PMOS transistor is connected to the power supply voltage.

[0077] It should be explained that the logic control circuit adopts a specific structure consisting of AND gates, OR gates, a fourth transmission gate TG4, and a first PMOS transistor, which is used to generate the control level required by the push-pull output circuit based on the detection enable signal and the load control signal.

[0078] Specifically, the logic control circuit includes an AND gate, an OR gate, a fourth transmission gate TG4, and a first PMOS transistor. The AND gate has three inputs. The OR gate has two inputs and one output; its first input is used to receive a load control signal (e.g., a PWM signal or an enable signal), and its second input is connected to the output of the AND gate, which is also connected to the control terminal of the pull-down transistor in the push-pull output circuit. The output of the OR gate is connected to the first transmission terminal of the fourth transmission gate TG4, and also to the first input of the AND gate. The second input of the AND gate is used to receive a control signal. The third input of the AND gate is used to receive a timing control signal for finer timing management.

[0079] The fourth transmission gate TG4 has a first transmission terminal, a second transmission terminal, a control terminal, and an inverting control terminal. The first transmission terminal of TG4 is connected to the output of the OR gate. The second transmission terminal of TG4 is connected to the drain of the first PMOS transistor and simultaneously to the control terminal of the pull-up transistor in the push-pull output circuit. The control terminal of TG4 is connected to the gate of the first PMOS transistor to receive the corresponding control signal. The inverting control terminal of TG4 receives the inverted signal of this control signal. The source of the first PMOS transistor is connected to the power supply voltage VDD.

[0080] The working principle of the above circuit structure is as follows: When the circuit enters the detection mode, the detection enable signal is active. At this time, the third input of the AND gate is set to a low level, forcibly pulling the output of the AND gate low. This low-level signal directly controls the control terminal of the pull-down transistor in the push-pull output circuit, turning off the pull-down transistor. On the other hand, this low-level signal is input to the second input of the OR gate. The first input of the OR gate is connected to the load control signal, but since the second input of the OR gate is low, the output state of the OR gate depends entirely on the load control signal. However, in the detection mode, the timing control signal is usually set to a specific state, so that the first input of the AND gate (connected to the output of the OR gate) cooperates with the third input to ensure that the output of the OR gate can be effectively controlled. More importantly, the fourth transmission gate TG4 is in the off state in this mode, so that the connection between the drain of the first PMOS transistor and the output of the OR gate is cut off. At the same time, the gate of the first PMOS transistor receives the control signal to turn it on, pulling the drain of the first PMOS transistor (i.e., the control terminal of the pull-up transistor) high to VDD, thereby turning off the pull-up transistor. Therefore, when both the pull-up and pull-down transistors are turned off, the output of the push-pull output circuit is connected to the power supply only through the pull-up resistor, thus cutting off the drive path in the detection mode.

[0081] When the circuit enters drive mode, the enable signal is detected as invalid, and the third input of the AND gate is set to a high level. The other inputs of the AND gate (the first and second inputs) are also set to appropriate states, allowing the output of the AND gate to change accordingly based on the load control signal. Specifically, when the load control signal is high, the output of the OR gate is high. This high level is transmitted to the drain of the first PMOS transistor through the fourth transmission gate TG4 (which is currently on), causing the control terminal of the pull-up transistor to go high and turning it off. Simultaneously, the output of the AND gate is high, controlling the pull-down transistor to turn on, and the output of the push-pull output circuit is pulled low. Conversely, when the load control signal is low, the output of the OR gate is low. This low level is transmitted to the control terminal of the pull-up transistor through the fourth transmission gate TG4, turning it on. Simultaneously, the output of the AND gate is low, controlling the pull-down transistor to turn off, and the output of the push-pull output circuit is pulled high. Thus, the push-pull output circuit drives the power transistor normally according to the load control signal.

[0082] The logic control circuit structure used in this embodiment has the following technical advantages: First, reliable switching between detection mode and drive mode is achieved. By responding to the detection enable signal through the AND gate, the pull-down transistor is forcibly turned off in detection mode. At the same time, the pull-up transistor is forcibly turned off through the cooperation of the fourth transmission gate TG4 and the first PMOS transistor. This ensures that the output terminal of the push-pull output circuit is connected to the power supply only through the pull-up resistor in detection mode, avoiding signal conflict with the detection path.

[0083] Secondly, it achieves level conversion. Since the pull-up transistor in the push-pull output circuit is a PMOS transistor, its conduction requires a low-level control, while the OR gate output is at a CMOS level. By combining the fourth transmission gate TG4 with the first PMOS transistor, the output level of the OR gate is converted into a signal suitable for pull-up transistor control: when the fourth transmission gate TG4 is on, the OR gate output is directly transmitted to the pull-up transistor control terminal; when the fourth transmission gate TG4 is off, the first PMOS transistor pulls the pull-up transistor control terminal high. This structure effectively solves the control signal level matching problem.

[0084] Third, the logic function is flexible and adjustable. The AND gate has three input terminals, which can be connected to different timing control signals according to the actual application requirements to realize more complex logic functions. For example, delay or sequential control can be introduced during the detection mode switching process to further improve the stability and reliability of the circuit.

[0085] It should be noted that the signals at the three input terminals of the AND gate in this embodiment can be configured according to the specific application. For example, the first input terminal of the AND gate can be connected to the output terminal of the OR gate to form feedback, the second input terminal of the AND gate can be connected to a control signal, and the third input terminal of the AND gate can be connected to a timing control signal (such as the inverted signal of the detection enable signal) to ensure that no race conditions occur during the switching of the detection mode. The control signals of the fourth transmission gate TG4 and the first PMOS transistor can also be designed according to timing requirements. As long as it is ensured that the pull-up and pull-down transistors are turned off simultaneously in the detection mode and that normal driving is achieved in the driving mode, it does not deviate from the protection scope of this embodiment.

[0086] In summary, this embodiment achieves reliable switching between detection and drive modes of the logic control circuit through specific connections and coordinated operation of AND gates, OR gates, the fourth transmission gate TG4, and the first PMOS transistor. It provides precise control signals for the push-pull output circuit and ensures the correct operation of the power transistor drive control module in different working modes.

[0087] In one example, the push-pull output circuit includes: The second PMOS transistor, the second NMOS transistor MN2, the third resistor R3, the fourth resistor R4, and the fifth resistor R5; The source of the second PMOS transistor is connected to the source of the first PMOS transistor and the first terminal of the fifth resistor R5; the gate of the second PMOS transistor is connected to the second transmission terminal of the fourth transmission gate TG4 and the drain of the first PMOS transistor; the drain of the second PMOS transistor is connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is connected to the first terminal of the fourth resistor R4, the second terminal of the fifth resistor R5, the controlled terminal of the power transistor, and the controlled terminal of the mirror transistor. The second end of the fourth resistor R4 is connected to the drain of the second NMOS transistor MN2, the source of the second NMOS transistor MN2 is grounded, and the gate is connected to the output of the AND gate.

[0088] It should be explained that the push-pull output circuit provides a drive signal to the power transistor in drive mode and ensures that the output is connected to the power supply only through a pull-up resistor in detection mode. Specifically, the push-pull output circuit includes a second PMOS transistor, a second NMOS transistor MN2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The source of the second PMOS transistor is connected to the source of the first PMOS transistor and simultaneously to the first terminal of the fifth resistor R5, i.e., they are all connected to the power supply voltage VDD. The gate of the second PMOS transistor is connected to the second transmission terminal of the fourth transmission gate TG4 and simultaneously to the drain of the first PMOS transistor, i.e., it receives the pull-up control signal from the logic control circuit. The drain of the second PMOS transistor is connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to the first terminal of the fourth resistor R4 and simultaneously to the second terminal of the fifth resistor R5. This common node is the output terminal of the push-pull output circuit, connected to the controlled terminal of the power transistor and the controlled terminal of the mirror transistor. The second terminal of the fourth resistor R4 is connected to the drain of the second NMOS transistor MN2. The source of the second NMOS transistor MN2 is grounded, and its gate is connected to the output of the AND gate, thus receiving the pull-down control signal from the logic control circuit. The fifth resistor R5 is the pull-up resistor shown in this example.

[0089] The working principle of the above circuit structure is as follows: When the circuit is in drive mode, the logic control circuit generates corresponding pull-up and pull-down control signals according to the load control signal. When it is necessary to pull the output terminal of the push-pull output circuit high, the pull-up control signal is low and the pull-down control signal is low. At this time, the second PMOS transistor is turned on and the second NMOS transistor MN2 is turned off. The power supply voltage VDD provides current to the output terminal through the second PMOS transistor and the third resistor R3, pulling the output terminal high. The fifth resistor R5 is connected in parallel between the power supply and the output terminal, playing an auxiliary pull-up and voltage stabilization role during the output terminal pull-up process.

[0090] When the output of the push-pull output circuit needs to be pulled low, the pull-up control signal is high and the pull-down control signal is high. At this time, the second PMOS transistor is turned off and the second NMOS transistor MN2 is turned on. The output is discharged to ground through the fourth resistor R4 and the second NMOS transistor MN2, pulling the output low. During this process, the third resistor R3 and the fifth resistor R5 together limit the maximum output current when the second PMOS transistor is turned on, preventing overcurrent damage due to load short circuit or accidental grounding of the output; at the same time, the fourth resistor R4 limits the discharge current when the second NMOS transistor MN2 is turned on, providing current limiting protection.

[0091] The introduction of the third resistor R3, the fourth resistor R4, and the fifth resistor R5 serves the following important purposes: First, current limiting protection. When a short circuit or transient large current occurs at the output of the push-pull output circuit, these resistors can limit the peak current flowing through the second PMOS transistor and the second NMOS transistor MN2, preventing the transistors from being damaged due to overcurrent. Second, controlling drive strength. By appropriately selecting the resistor values, the rise time and fall time of the push-pull output circuit can be adjusted, thereby controlling the charging and discharging speed of the power transistor gate and optimizing switching losses and electromagnetic interference performance. Third, output level adjustment. When the output is pulled high, the fifth resistor R5 and the third resistor R3 form a voltage divider network to ensure that the output high level is close to VDD; when the output is pulled low, the fourth resistor R4 ensures that the output low level is close to ground. Fourth, in detection mode, when both the second PMOS transistor and the second NMOS transistor MN2 are turned off, the interference of the push-pull output circuit to the power transistor control terminal is effectively isolated only through the pull-up resistor to the power supply.

[0092] When the circuit is in detection mode, the logic control circuit sets the pull-up control signal to high and the pull-down control signal to low, simultaneously turning off the second PMOS transistor and the second NMOS transistor MN2. At this time, the output of the push-pull output circuit is only connected to the power supply through the pull-up resistor. Since the value of the fifth resistor R5 is typically chosen to be in the kiloohm range or higher, the equivalent impedance of the output to ground and to the power supply is high, which will not significantly affect the output signal of the first operational amplifier AMP1 transmitted by the transmission gate array circuit, thus ensuring precise control of the power transistor gate voltage in detection mode.

[0093] The push-pull output circuit structure used in this embodiment has the following technical advantages: First, it achieves a balance between driving capability and protection function. By introducing the third resistor R3, the fourth resistor R4, and the fifth resistor R5, while maintaining the strong driving capability of the push-pull output circuit, it adds current limiting protection function, thereby improving the reliability and robustness of the circuit.

[0094] Second, the high impedance state at the output terminal ensures reliability during mode switching. In detection mode, the second PMOS transistor and the second NMOS transistor MN2 are simultaneously turned off, and the resistor network maintains a high impedance between the output terminal and the power supply and ground, effectively avoiding signal interference with the detection path.

[0095] Third, the driving parameters are adjustable. The resistance values ​​of the third resistor R3, the fourth resistor R4, and the fifth resistor R5 can be optimized according to factors such as actual load characteristics, switching frequency, and electromagnetic compatibility requirements, providing good design flexibility.

[0096] In the fourth embodiment, the control terminal of the third transmission gate TG3 and the inverting control terminal of the fourth transmission gate TG4 are used to access the first timing signal; the inverting control terminal of the third transmission gate TG3, the control terminal of the fourth transmission gate TG4, and the third input terminal of the AND gate are used to access the first inverted timing signal. The control terminal of the first transmission gate TG1 is used to receive the second timing signal; the inverting control terminal of the first transmission gate TG1 is used to receive the second inverted timing signal. The inverting control terminal of the second transmission gate TG2 is used to access the third timing signal; the control terminal of the second transmission gate TG2 is used to access the third inverting timing signal.

[0097] It should be noted that the high-precision load resistance measurement circuit described in this embodiment introduces multiple sets of timing signals to precisely control the conduction and cutoff of each transmission gate in the detection mode, thereby realizing the sequential switching between the two working stages of bias establishment and precise detection. Specifically, the timing signals include a first timing signal sel1 and its inverted signal seln1 (first inverted timing signal), a second timing signal seld1 and its inverted signal selnd1 (second inverted timing signal), and a third timing signal seld2 and its inverted signal selnd2 (third inverted timing signal). seln1 and sel1 are logically complementary, selnd1 and seld1 are logically complementary, and selnd2 and seld2 are logically complementary. These timing signals can be generated by the on-chip timing control circuit or an external controller, and their logic levels are set according to the needs of the working stage.

[0098] The connection relationships between the above timing signals and each transmission gate and logic gate are as follows: The control terminal of the third transmission gate TG3 and the inverting control terminal of the fourth transmission gate TG4 are both connected to the first timing signal sel1. The inverting control terminal of the third transmission gate TG3, the control terminal of the fourth transmission gate TG4, and the third input terminal of the AND gate are all connected to the first inverted timing signal seln1. The control terminal of the first transmission gate TG1 is connected to the second timing signal seld1, and the inverting control terminal of the first transmission gate TG1 is connected to the second inverted timing signal selnd1. The inverting control terminal of the second transmission gate TG2 is connected to the third timing signal seld2, and the control terminal of the second transmission gate TG2 is connected to the third inverted timing signal selnd2.

[0099] Through the above connection method, this embodiment utilizes the timing coordination of sel1, seld1, seld2 and their inverted signals to achieve orderly switching between the bias establishment stage and the precise detection stage in the detection mode. The specific timing coordination is as follows: When the circuit enters detection mode and bias setup is required first, sel1 is set to high level, and seln1 is set to low level accordingly; seld1 is set to low level, and selnd1 is set to high level; seld2 is set to high level, and selnd2 is set to low level. In this state: the third transmission gate TG3 is turned on because its control terminal is high level and its inverting control terminal is low level; the fourth transmission gate TG4 is turned off because its control terminal is low level and its inverting control terminal is high level. At this time, the fourth transmission gate TG4 is in the off state, and the third input terminal of the AND gate is connected to a high level; the first transmission gate TG1 is turned off because its control terminal is low level and its inverting control terminal is high level; the second transmission gate TG2 is turned on because its inverting control terminal is high level and its control terminal is low level. At this time, the second transmission gate TG2 and the third transmission gate TG3 are turned on, connecting the drain of the mirror transistor to the controlled terminal of the power transistor. Simultaneously, the path between the output of the first operational amplifier AMP1 and the control terminal of the power transistor is cut off by the first transmission gate TG1, and the fourth transmission gate TG4 is turned off, isolating the pull-up control signal from the OR gate output. This state corresponds to the bias setup stage, where the circuit completes the initial bias setup. It should be noted that during this stage, since sel1 is high and seln1 is low, and the fourth transmission gate TG4 is turned off, the pull-up and pull-down transistors of the push-pull output circuit are simultaneously turned off under the action of the logic control circuit, resulting in a high-impedance output, thus avoiding signal interference with the detection path.

[0100] When the bias is established and the precise detection phase is ready, the timing signals switch to another set of states: sel1 remains high, seln1 remains low; seld1 switches to high, selnd1 switches to low; seld2 switches to low, selnd2 switches to high. In this state: the third transmission gate TG3 remains on because its control terminal is high and its inverting control terminal is low; the fourth transmission gate TG4 remains off because its control terminal is low and its inverting control terminal is high; the first transmission gate TG1 is on because its control terminal is high and its inverting control terminal is low; the second transmission gate TG2 is off because its inverting control terminal is low and its control terminal is high. At this time, the first transmission gate TG1 and the third transmission gate TG3 are on, connecting the output of the first operational amplifier AMP1 to the controlled terminal of the power transistor, while the second transmission gate TG2 is off, cutting off the connection between the drain of the mirror transistor and the common node. This state corresponds to the precise detection stage, where the first operational amplifier AMP1 forms a complete feedback loop to achieve high-precision current mirroring.

[0101] During the two phases described above, sel1 remains high and seln1 remains low. This means that the fourth transmission gate TG4 is always off, and the third input of the AND gate is always connected to a low level. This setting ensures that in detection mode, the push-pull output circuit is always isolated from the power transistor control terminal, and its output remains in a high-impedance state, preventing interference with the detection path. Simultaneously, the low level at the third input of the AND gate forces its output low, further ensuring that the pull-down transistor remains off in detection mode.

[0102] The timing signal connection and coordination scheme adopted in this embodiment has the following technical effects: First, it achieves strict sequential execution of the two stages: bias setup and precise detection. Through the coordinated switching of seld1 and seld2, it ensures that during the bias setup stage, the first operational amplifier AMP1 is not yet connected to the feedback loop, and the drain of the image transistor is forced to a stable potential. During the precise detection stage, the feedback loop is established, and the drain voltages of the image transistor and the power transistor are precisely clamped. This staged startup method effectively prevents the op-amp from failing to start normally.

[0103] Secondly, through the continuous control of sel1 and seln1, the fourth transmission gate TG4 is kept off at all times in detection mode, ensuring isolation between the push-pull output circuit and the power transistor control terminal, thus achieving electrical separation between the drive path and the detection path. This design not only avoids signal conflicts but also provides structural assurance for calibration with low current during mass production testing.

[0104] Third, the complementary control method of timing signals and transmission gates fully utilizes the bidirectional conduction and threshold loss characteristics of transmission gates, ensuring the accurate transmission of analog signals. The control terminals and inverting control terminals of each transmission gate are respectively connected to complementary timing signals, enabling the transmission gate to transmit full-swing signals when it is on and to achieve complete isolation when it is off.

[0105] Fourth, the seln1 signal is connected to the third input terminal of the AND gate to synchronize the timing of the logic control circuit with the detection stage. In the detection mode, the AND gate is forced to output a low level to ensure that the pull-down transistor is turned off, thus avoiding signal conflicts or glitches that may occur during mode switching and improving the stability and anti-interference capability of the circuit.

[0106] It should be noted that the effective levels (active high) of sel1, seld1, and seld2 in this embodiment can be defined according to the specific circuit design. As long as the on / off states of each transmission gate and logic gate meet the above timing requirements during the bias setup and accurate detection phases, the same technical effect can be achieved. In addition, the switching timing of the timing signals can be set with an appropriate delay according to the actual needs of the circuit to ensure normal circuit startup and operation.

[0107] In summary, this implementation achieves reliable switching between the two stages of circuit startup and precise detection in detection mode through the precise connection and timing coordination of sel1, seld1, seld2 and their inverted signals seln1, selnd1, selnd2. At the same time, it ensures complete isolation of the drive path in detection mode, providing a stable timing control foundation for high-precision load resistance measurement circuits.

[0108] In one example, such as Figure 8 As shown, the high-precision load resistance measurement circuit further includes: a third NMOS transistor MN3 and a sixth resistor R6; The source of the third NMOS transistor MN3 is connected to the inverting input terminal of the first operational amplifier AMP1, and the drain is connected to the first terminal of the sixth resistor R6; the second terminal of the sixth resistor R6 is connected to the second terminal of the power transistor. The gate of the third NMOS transistor MN3 is used to receive the first timing signal.

[0109] It should be explained that, through the above connection, this embodiment introduces a sampling path consisting of the third NMOS transistor MN3 and the sixth resistor R6 connected in series between the drain of the power transistor and the inverting input of the first operational amplifier AMP1. The first timing signal sel1 is the main control signal for the detection mode, and its level determines the on / off state of this sampling path.

[0110] The specific working principle is as follows: When the circuit enters the detection mode, the first timing signal sel1 is set to a high level. At this time, the third NMOS transistor MN3 is turned on, connecting the inverting input terminal of the first operational amplifier AMP1 to the drain of the power transistor through the sixth resistor R6. Since the resistance of the sixth resistor R6 can be designed to be relatively large (e.g., on the order of kiloohms), and the inverting input terminal of the first operational amplifier AMP1 is a high-impedance node, almost no current flows through the sixth resistor R6, and its voltage drop is negligible. Therefore, the voltage at the inverting input terminal of the first operational amplifier AMP1 is approximately equal to the drain voltage of the power transistor, i.e., the load voltage Vout. The ADC sampling module can accurately acquire Vout by connecting to the inverting input terminal of the first operational amplifier AMP1.

[0111] When the circuit enters drive mode, the first timing signal sel1 is set to low. At this time, the third NMOS transistor MN3 is turned off, cutting off the connection between the inverting input of the first operational amplifier AMP1 and the drain of the power transistor. Since the drain of the power transistor may exhibit large voltage fluctuations in drive mode, this turn-off state effectively isolates the high-current path of the load from the high-precision detection circuit, avoiding transient interference in drive mode from impacting or damaging the input of the first operational amplifier AMP1.

[0112] The third NMOS transistor MN3 and the sixth resistor R6 introduced in this example have the following technical advantages: First, electrical isolation between the sampling path and the driving path is achieved. By turning off the third NMOS transistor MN3 in driving mode, the inverting input terminal of the first operational amplifier AMP1 is completely disconnected from the drain of the power transistor, preventing large voltage swings or noise generated at the drain of the power transistor in driving mode from coupling to the detection circuit. This protects the first operational amplifier AMP1 and the input stage of the ADC sampling module, improving the reliability of the circuit.

[0113] Secondly, it ensures high accuracy of voltage sampling in detection mode. In detection mode, the third NMOS transistor MN3 is turned on, but since no current flows through the sixth resistor R6 (the input impedance of the inverting input terminal of the first operational amplifier AMP1 is extremely high), there is no voltage drop across the sixth resistor R6. Therefore, the voltage at the inverting input terminal of the first operational amplifier AMP1 is precisely equal to the drain voltage of the power transistor, achieving lossless sampling. At the same time, the presence of the sixth resistor R6 provides electrostatic discharge protection for the third NMOS transistor MN3: when the third NMOS transistor MN3 is turned off, if a transient high voltage occurs at the drain of the power transistor, the sixth resistor R6 can limit the current flowing into the drain of the third NMOS transistor MN3, playing a certain current-limiting protection role.

[0114] Third, it simplifies circuit design. The third NMOS transistor MN3 is directly controlled by the first timing signal sel1, without the need for additional control signals or level conversion circuits. It is fully compatible with the aforementioned detection mode control logic and is easy to integrate.

[0115] It should be noted that the resistance value of the sixth resistor R6 in this embodiment must balance sampling accuracy and protection functionality. If the resistance value is too large, it may introduce additional thermal noise, affecting the signal-to-noise ratio of the ADC sampling; if the resistance value is too small, the protection effect will be limited. Typically, a resistor in the range of several thousand ohms to tens of thousands of ohms can be selected to provide sufficient current-limiting protection while ensuring sampling accuracy. Furthermore, the dimensions of the third NMOS transistor MN3 should be designed based on the impact of its on-resistance on sampling accuracy, ensuring that its on-resistance is much smaller than that of the sixth resistor R6, thereby ignoring its voltage division effect on the sampling voltage.

[0116] In summary, this embodiment achieves high-precision sampling of the load terminal voltage in detection mode and effective isolation between the detection circuit and the high-current path in driving mode by introducing the third NMOS transistor MN3 and the sixth resistor R6, thereby further improving the reliability and measurement accuracy of the circuit.

[0117] In one example, the high-precision load resistance measurement circuit further includes: an electrostatic protection circuit; The first terminal of the electrostatic protection circuit is connected to the first terminal of the sixth resistor R6, and the second terminal is grounded.

[0118] It's easy to understand that electrostatic discharge (ESD) protection circuits are used to discharge transient high voltages and large currents generated during electrostatic discharge events, preventing damage to internal circuits due to electrostatic shocks. In integrated circuits, ESD protection circuits are typically implemented using diode structures, silicon controlled rectifier (SCR) structures, or gate-grounded NMOS structures. When an electrostatic pulse appears at the first terminal of the sixth resistor R6, the ESD protection circuit quickly conducts, providing a low-impedance discharge path to ground for the electrostatic charge. This clamps the voltage at the first terminal of the sixth resistor R6 within a safe range, protecting the connected third NMOS transistor MN3, the first operational amplifier AMP1, and other internal circuits from damage.

[0119] In this example, the electrostatic protection circuit is connected between the first terminal of the sixth resistor R6 and ground. The location of this circuit is chosen based on the following technical considerations: First, the sixth resistor, R6, plays a current-limiting role in electrostatic discharge (ESD) protection. When an ESD pulse is applied to the drain of the power transistor, the sixth resistor R6 can limit the current flowing into the third NMOS transistor MN3, thus forming a multi-level protection mechanism in conjunction with the ESD protection circuit. The resistance value of the sixth resistor R6 can be optimized according to the ESD protection requirements, providing sufficient current-limiting capability while ensuring sampling accuracy during normal operation.

[0120] Secondly, this connection node is located at a critical position in the sampling path. The first end of the sixth resistor R6 is connected to the drain of the third NMOS transistor MN3, which is an important node on the signal transmission path in detection mode. Setting up an electrostatic discharge (ESD) protection circuit here can effectively protect sensitive devices in the sampling path, while avoiding adverse effects on the high-current drive path caused by the ESD protection circuit being directly connected to the drain of the power transistor.

[0121] Third, the connection of the grounding terminal of the electrostatic discharge (ESD) protection circuit ensures the integrity of the discharge path. Directly grounding the second terminal of the ESD protection circuit provides the shortest discharge path for static charges, reduces the clamping voltage of the ESD protection circuit, and improves the protection effect.

[0122] It should be noted that the specific implementation of the electrostatic discharge (ESD) protection circuit in this embodiment can be selected according to the semiconductor process and ESD protection level requirements. In standard CMOS processes, a bidirectional ESD protection structure combining power clamping and ground clamping can be used, or a unidirectional protection structure with a single diode connected to ground can be used. Regardless of the specific implementation method, as long as its first terminal is connected to the first terminal of the sixth resistor R6 and its second terminal is grounded, it will not deviate from the protection scope of this embodiment.

[0123] Furthermore, the introduction of the electrostatic discharge (ESD) protection circuit does not affect the circuit's performance in normal detection and drive modes. Under normal operating conditions, the ESD protection circuit is in a high-resistance state and has no effect on the potential of the first terminal of the sixth resistor R6; the ESD protection circuit only conducts and performs its protective function when an ESD event occurs. Therefore, the inclusion of this ESD protection circuit improves the circuit's reliability while maintaining the high-precision characteristics of the original measurement circuit.

[0124] In summary, this embodiment provides effective electrostatic discharge protection for the high-precision load resistance measurement circuit by setting an electrostatic protection circuit between the first terminal of the sixth resistor R6 and ground, thereby enhancing the reliability and robustness of the circuit in practical applications, without affecting its normal detection and driving functions.

[0125] The above description is merely an optional embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A high-precision load resistance measurement circuit, characterized in that, include: Reference current source generation module, first operational amplifier, power transistor, image transistor and ADC sampling module; The first terminal of the power transistor and the first terminal of the image transistor are used to connect to the power supply voltage; the controlled terminal of the power transistor and the controlled terminal of the image transistor are connected to each other and connected to the output terminal of the first operational amplifier. The input terminal of the reference current source generation module is used to connect to the reference voltage; the reference current source generation module is located in the path between the second terminal of the mirror tube and ground; The reference current source generation module is used to adjust the current flowing through the mirror tube to ground to the corresponding reference current value based on the reference voltage. The non-inverting input of the first operational amplifier is connected to the second terminal of the image transistor, and the inverting input of the first operational amplifier is connected to the second terminal of the power transistor and the first terminal of the load; the second terminal of the load is grounded. The input terminal of the ADC sampling module is connected to the inverting input terminal of the first operational amplifier; The reference current source generation module includes: Reference resistor, second operational amplifier, and first NMOS transistor; The non-inverting input of the second operational amplifier is used to connect to the reference voltage; the output of the second operational amplifier is connected to the gate of the first NMOS transistor; the drain of the first NMOS transistor is connected to the second terminal of the mirror transistor and the non-inverting input of the first operational amplifier; the source of the first NMOS transistor is connected to the first terminal of the reference resistor and the inverting input of the second operational amplifier. The second terminal of the reference resistor is grounded; The reference resistor is an adjustable zero-temperature-drift resistor; The high-precision load resistance measurement circuit also includes: a voltage source generation module; The voltage source generation module includes: a bandgap reference power supply, a reference voltage generation circuit, a first resistor, a second resistor, and a trimming resistor; The output terminal of the bandgap reference power supply is connected to the input terminal of the reference voltage generation circuit. The output terminal of the reference voltage generation circuit is connected to the first terminal of the first resistor. The second terminal of the first resistor is connected to the first terminal of the adjustment resistor and the non-inverting input terminal of the second operational amplifier. The second terminal of the adjustment resistor is connected to the first terminal of the second resistor, and the second terminal of the second resistor is grounded. The bandgap reference power supply is used to output the original reference voltage; The reference voltage generating circuit is used to convert the original reference voltage into a reference voltage and then output it. The high-precision load resistance measurement circuit also includes: Transmission gate array circuit and power transistor drive control module; The transmission gate array circuit is disposed in the path between the output terminal of the second operational amplifier and the controlled terminal of the power transistor; the transmission gate array circuit is used to open the path between the output terminal of the second operational amplifier and the controlled terminal of the power transistor when a detection enable signal is received. The output terminal of the power transistor drive control module is connected to the controlled terminal of the power transistor and the controlled terminal of the mirror transistor. The power transistor drive control module is used to stop outputting load control signals upon receiving the detection enable signal.

2. The high-precision load resistance measurement circuit as described in claim 1, characterized in that, The transmission gate array circuit includes: First transmission gate, second transmission gate, and third transmission gate; The first transmission terminal of the first transmission gate is connected to the output terminal of the first operational amplifier, and the second transmission terminal is connected to the second transmission terminal of the second transmission gate and the second transmission terminal of the third transmission gate; the first transmission terminal of the second transmission gate is connected to the second terminal of the mirror transistor and the non-inverting input terminal of the first operational amplifier; the first transmission terminal of the third transmission gate is connected to the controlled terminal of the power transistor, the controlled terminal of the mirror transistor, and the output terminal of the power transistor drive control module.

3. The high-precision load resistance measurement circuit as described in claim 2, characterized in that, The power transistor drive control module includes: Logic control circuit and push-pull output circuit; The input terminal of the push-pull output circuit is connected to the power supply voltage, and the output terminal is connected to the controlled terminal of the power transistor and the controlled terminal of the image transistor. The first output terminal of the logic control circuit is connected to the controlled terminal of the pull-up transistor in the push-pull output circuit, and the second output terminal of the logic control circuit is connected to the controlled terminal of the pull-down transistor in the push-pull output circuit. The logic control circuit is used to control the pull-up transistor and the pull-down transistor to turn off when a detection enable signal is received.

4. The high-precision load resistance measurement circuit as described in claim 3, characterized in that, The control terminal of the third transmission gate is used to receive the first timing signal; the inverting control terminal of the third transmission gate is used to receive the first inverted timing signal. The control terminal of the first transmission gate is used to receive the second timing signal; the inverting control terminal of the first transmission gate is used to receive the second inverted timing signal. The inverting control terminal of the second transmission gate is used to receive the third timing signal; the control terminal of the second transmission gate is used to receive the third inverting timing signal.

5. The high-precision load resistance measurement circuit as described in claim 4, characterized in that, The high-precision load resistance measurement circuit also includes: a third NMOS transistor and a sixth resistor; The source of the third NMOS transistor is connected to the inverting input of the first operational amplifier, and the drain is connected to the first terminal of the sixth resistor; the second terminal of the sixth resistor is connected to the second terminal of the power transistor. The gate of the third NMOS transistor is used to receive the first timing signal.

6. The high-precision load resistance measurement circuit as described in claim 5, characterized in that, The high-precision load resistance measurement circuit also includes: an electrostatic protection circuit; The first terminal of the electrostatic protection circuit is connected to the first terminal of the sixth resistor, and the second terminal is grounded.

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