Controller IO channel test and calibration device and method based on dynamic port switching

Abstract

This application relates to a controller I / O channel testing and calibration device and method based on dynamic port switching, belonging to the field of industrial test fixture technology. The device includes: a test fixture motherboard and a human-machine interface module that interact with the controller under test (DUT) via a communication bus, and a power supply module that supplies power to the test fixture motherboard. The test fixture motherboard includes a microprocessor, a test signal generation unit, a signal selection unit, an I / O port selection unit, a signal conditioning and acquisition unit, a calibration control unit, a unique pair of interactive interfaces, and multiple independent motherboard I / O ports. These ports are used by the microprocessor to receive and parse the test / calibration commands sent sequentially by the DUT, thereby completing the testing and calibration of all I / O channels of the DUT in sequence. This device can achieve an integrated closed loop of testing, calibration, write operation, and retesting, improving the consistency and automation level of I / O channel testing and calibration for various types of controllers.

Description

Technical Field

[0001] This application relates to the field of industrial testing tooling technology, and in particular to a device and method for testing and calibrating controller I / O channels based on dynamic port switching. Background Technology

[0002] In the field of industrial automation, the stability, accuracy, and consistency of the controller's I / O channels directly affect the overall functionality, factory consistency, and field maintenance efficiency. Existing controller I / O testing solutions typically suffer from the following problems:

[0003] First, existing solutions mostly rely on external standard signal sources, voltage and current generators, and independent signal conditioning equipment. The test links are long, which can easily introduce additional noise and errors. In addition, the equipment connections are cumbersome, and the problem-finding cycle is long.

[0004] Second, existing tooling is often designed for a single controller model or a single test type. When the controller model under test changes, the IO type changes, or the test items change, the tooling usually needs to be reconfigured or the program modified, resulting in poor versatility.

[0005] Third, most existing solutions only focus on "whether the test is passed", lacking a closed-loop mechanism to complete the generation, writing and retesting of calibration parameters around the same communication link. This leads to the separation of testing and calibration, excessive manual intervention, and difficulty in ensuring production consistency.

[0006] Fourth, existing test fixtures lack the ability to dynamically schedule test signal paths, port mapping paths, and calibration processes, making it difficult to complete automated testing and calibration of multiple types of IO channels on a single fixture. Summary of the Invention

[0007] Therefore, it is necessary to provide a device and method for testing and calibrating controller I / O channels based on dynamic port switching to address the above-mentioned technical problems, so as to reduce dependence on external devices, improve the test path reuse capability, and realize an integrated closed loop for testing, calibration, parameter writing, and retesting of controller I / O channels.

[0008] A controller I / O channel testing and calibration device based on dynamic port switching, the device comprising: a test fixture motherboard and a human-machine interface module that interact with the controller under test via a communication bus, and a power supply module that supplies power to the test fixture motherboard; The human-machine interaction module is used to receive the parameter information of the controller under test input by the user after power-on, send the start test / calibration command to the controller under test, and receive and display the test, calibration and retest results returned by the controller under test. The test fixture motherboard includes a microprocessor, a test signal generation unit, a signal matching unit, an IO port matching unit, a signal conditioning and acquisition unit, a calibration control unit, a unique pair of interactive interfaces, and multiple independent motherboard IO ports. It is used to receive and parse the test / calibration instructions sent by the controller under test one by one using the microprocessor, so as to complete the test and calibration of all IO channels under test of the controller under test in sequence. Each test / calibration instruction corresponds to the test / calibration of a pair of IO channels under test with the same test / calibration type, and every two motherboard IO ports form a group and are selectively connected to an IO channel under test. The microprocessor is configured as follows: During input testing, the test signal generation unit first generates a test signal based on the current test type and test parameters. Then, the signal selection unit selects the corresponding test signal for the current test type and sends it to the interactive interface, forming a test signal output path. Simultaneously, the IO port selection unit connects the interactive interface to the currently selected set of motherboard IO ports, forming a connection path for the IO channel pair under test. Furthermore, the test signal output path and the connection path for the IO channel pair under test are dynamically switched based on different test commands, and the test signal is output to the corresponding IO channel pair under test to complete the input test. During output testing, the control IO port selection unit connects the currently selected set of motherboard IO ports to the interaction interface, transmits signals to the signal conditioning and acquisition unit through the interaction interface, forms a signal conditioning and acquisition path, and dynamically switches the signal conditioning and acquisition path based on different test commands to acquire the output signals of the corresponding IO channel under test, and sends the acquisition results to the controller under test for test result determination. During calibration, the data interaction between the I / O channel pair under test and the corresponding set of motherboard I / O ports is completed according to the calibration point sequence obtained by parsing. The calibration control unit is controlled to generate calibration correction data for each calibration point and write it into the calibration parameter storage area of ​​the controller under test. After writing, the corresponding channel is retested until the retest result meets the error threshold requirement, thus completing the calibration closed loop.

[0009] In one embodiment, the test instruction includes a test execution type field, a current test type field, a port mapping field, and a test parameter field. The test execution type field indicates whether an input test or an output test is currently being performed. The test type field indicates any one of the following: analog voltage input, analog current input, analog resistance input, analog frequency input, digital high-side input, digital low-side input, digital high-side output, or digital low-side output. The port mapping field indicates the corresponding connection between the I / O channel pair under test and a set of motherboard I / O ports. For analog input tests, the test parameter field indicates the definition of the I / O channel pair under test and the values ​​of the voltage, current, resistance, and frequency to be tested. For digital input / output tests, the test parameter field only indicates the definition of the I / O channel pair under test. The calibration instruction includes a calibration execution type field, a port mapping field, a calibration point field, and an error threshold field. The calibration execution type field indicates whether input calibration or output calibration is currently being performed. The calibration point field indicates the calibration point sequence, which includes any combination of zero-point calibration points, full-scale calibration points, and one or more intermediate calibration points. The error threshold field indicates the maximum permissible retest error value.

[0010] In one embodiment, the test signal generation unit is equipped with a DAC conversion module, a configurable high-precision resistor box, a frequency signal generation circuit, and a relay switching circuit. The DAC conversion module is used to generate the test signals required for analog voltage / current input testing; A configurable high-precision resistance box can be used to generate the test signals required for analog resistance input testing; The frequency signal generation circuit is used to generate the test signal required for analog frequency input testing; The relay switching circuit is used to generate the test signal required for digital high-side / low-side input testing.

[0011] In one embodiment, the signal selection unit includes a multiplexer and a test signal output enable circuit; the multiplexer is used to generate an enable signal corresponding to the current test type based on the selection signal output by the microprocessor; the test signal output enable circuit is used to connect only one test signal output path corresponding to the current test type based on the enable signal that is in an active state.

[0012] In one embodiment, the test signal output enable circuit consists of an NPN transistor, a relay, and circuit protection elements. In this NPN transistor, the base receives an enable signal through an external current-limiting resistor, the emitter is grounded, and the collector is connected to the relay coil. This allows the transistor to control the conduction state based on the level of the enable signal, thereby controlling the on / off state of the relay coil contacts and enabling the switching control of the signal path connected to the relay. One end of the relay coil is connected to the positive terminal of the power supply, and the other end is connected to the collector of the NPN transistor. It adopts a double-pole double-throw structure. When energized, the relay contacts close, connecting the common terminal with the normally open terminal, so that the test signal input through the common terminal is output through the only pair of interactive interfaces connected to the normally open terminal; otherwise, the relay contacts open, cutting off the control test signal output path. The circuit protection components include a pull-down resistor connected between the base of the NPN transistor and ground to stabilize the base potential; and a Schottky diode connected in parallel across the relay coil to absorb the reverse induced electromotive force generated when the relay coil is de-energized.

[0013] In one embodiment, the IO port selection unit includes multiple IO port selection circuits, each corresponding to a set of motherboard IO ports. The microprocessor controls the IO port selection circuit corresponding to the currently selected set of motherboard IO ports to be turned on according to the parsed port mapping field, so as to select the interaction interface to be connected to the currently selected set of motherboard IO ports, thereby outputting the test signal forwarded by the interaction interface to the IO channel pair under test corresponding to the currently selected set of motherboard IO ports to complete the input test.

[0014] In one embodiment, the optional circuitry for each I / O port includes an NPN transistor, a relay, and circuit protection components; In this NPN transistor, the base receives the I / O port selection signal through an external current-limiting resistor, the emitter is grounded, and the collector is connected to the relay coil. This is used to control the conduction state according to the I / O port selection signal, thereby controlling the on / off state of the relay coil contacts and realizing the switching control of the signal path connected to the relay. One end of the relay coil is connected to the positive terminal of the power supply, and the other end is connected to the collector of an NPN transistor. It adopts a double-pole double-throw structure. When energized, the relay contacts close, connecting the common terminal and the normally open terminal. This allows the test signal input through the only pair of interactive interfaces connected to the common terminal to be output through the I / O port of the currently selected test fixture motherboard connected to the normally open terminal. Otherwise, the relay contacts open, cutting off the control test signal output path. The circuit protection components include a pull-down resistor connected between the base of the NPN transistor and ground to stabilize the base potential; and a Schottky diode connected in parallel across the relay coil to absorb the reverse induced electromotive force generated when the relay coil is de-energized.

[0015] In one embodiment, the signal conditioning and acquisition unit includes a signal conditioning circuit and an ADC acquisition circuit. The signal conditioning circuit includes one or more of a voltage divider circuit, a filter circuit, an overvoltage protection circuit, and an inverting processing circuit. The signal conditioning and acquisition unit is used to condition and then acquire the output signal of the I / O channel under test.

[0016] In one embodiment, for input calibration, calibration correction data is calculated from the difference between the target value and the actual sampled value at each calibration point, including one or more of zero bias correction value, gain correction value, segmentation correction table and digital threshold correction data, and calibration points include zero calibration point, full scale calibration point and intermediate calibration point; for output calibration, calibration correction data is generated from the difference between the actual sampled value at each calibration point and the preset high and low level criteria, including one or more of high level identification threshold, low level identification threshold and hysteresis parameter.

[0017] A method for testing and calibrating controller I / O channels based on dynamic port switching, the method being implemented using the aforementioned device for testing and calibrating controller I / O channels based on dynamic port switching, includes the following steps: S1. After the device is powered on, the human-machine interface module receives the parameter information of the controller under test input by the user and sends a start test / calibration command to the controller under test. S2. The controller under test returns test confirmation information and sends test / calibration commands to the test fixture motherboard one by one according to the preset logic; S3. The microprocessor in the test fixture motherboard receives and parses each test / calibration command; S4. When performing an input test, the microprocessor first controls the test signal generation unit to generate a test signal according to the current test type and test parameters, and then controls the signal selection unit to select one of the test signals corresponding to the current test type to the interaction interface, forming a test signal output path; at the same time, it controls the IO port selection unit to connect the interaction interface with the currently selected set of motherboard IO ports, forming a connection path for the IO channel pair under test; then, based on different test instructions, it dynamically switches the test signal output path and the connection path for the IO channel pair under test, and outputs the test signal to the corresponding IO channel pair under test to complete the input test; S5. When the output test is performed, the microprocessor controls the IO port selection unit to connect the currently selected set of motherboard IO ports and the interaction interface, and transmits the signal to the signal conditioning and acquisition unit through the interaction interface to form a signal conditioning and acquisition path. The signal conditioning and acquisition path is dynamically switched based on different test commands to acquire the output signal of the corresponding IO channel under test, and the acquisition result is sent to the controller under test for test result judgment. S6. During calibration, the microprocessor completes the data interaction between the I / O channel pair under test and the corresponding set of motherboard I / O ports according to the calibration point sequence obtained by parsing. It controls the calibration control unit to generate calibration correction data for each calibration point and writes it into the calibration parameter storage area of ​​the controller under test. After the controller under test completes the writing of calibration parameters, it triggers the retest of the corresponding channel. If the retest error is not greater than the error threshold, the calibration is determined to be successful. Otherwise, the next round of correction and retest continues. S7. The controller under test feeds back the test, calibration and retest results to the human-computer interaction module for display and export.

[0018] The aforementioned controller I / O channel testing and calibration device and method based on dynamic port switching has the following advantages compared to existing technologies: 1. The test / calibration instructions sent by the controller under test one by one serve as the process-driven basis, enabling the test fixture motherboard to dynamically perform tests and calibrations for different controllers, different port mappings and different test types, thereby improving general adaptability.

[0019] 2. A single pair of interactive interfaces, consisting of a signal selection unit and an I / O port selection unit, enables dynamic switching of the test signal output path and the connection path of the I / O channel under test. Similarly, this single pair of interactive interfaces, used in conjunction with the I / O port selection unit and the signal conditioning and acquisition unit, enables dynamic switching of the signal conditioning and acquisition paths. Based on this unified path switching mechanism, various test types can share this single pair of interactive interfaces and the same port switching architecture. Dynamic switching between different signal sources and different port groups can be completed simply by following test commands, eliminating the need for additional hardware links. This effectively reduces the number of dedicated test links, simplifies hardware layout, and significantly improves the reusability of tooling structures and the versatility of the test system.

[0020] 3. By integrating test signal generation, dynamic switching output based on test commands, signal conditioning and acquisition, and calibration control functions into the test fixture motherboard, the signal transmission link is shortened, the number of external devices is reduced, and noise and error introduction are reduced.

[0021] 4. By introducing a calibration control unit and a calibration correction data writing mechanism, testing, calibration, parameter writing, and retesting form a closed loop, which can not only determine whether the channel is qualified, but also automatically correct channel errors and improve product consistency. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a controller I / O channel testing and calibration device based on dynamic port switching in one embodiment. Figure 2 This is a schematic diagram of the test signal output enable circuit in one embodiment; Figure 3This is a schematic diagram of an I / O port selection circuit in one embodiment; wherein, Figure 3 (a) is a schematic diagram of the IO port matching circuit that connects the IO ports IO#00 and IO#01 of the test fixture motherboard to the unique pair of interactive interfaces IO#S1 and IO#S2 based on the IO port matching signal IO_SEL_01. Figure 3 (b) is a schematic diagram of the IO port matching circuit that connects the IO ports IO#02 and IO#03 of the test fixture motherboard to the unique pair of interactive interfaces IO#S1 and IO#S2 based on the IO port matching signal IO_SEL_02. Figure 4 This is a schematic diagram of the signal conditioning circuit corresponding to the high-side output test of a digital quantity in one embodiment; Figure 5 This is a schematic diagram of the signal conditioning circuit corresponding to the low-side output test of a digital quantity in one embodiment; Figure 6 This is a schematic diagram of the input testing and input calibration logic in one embodiment; wherein, Figure 6 (a) is a schematic diagram of the input test logic. Figure 6 (b) is a schematic diagram of the input calibration logic; Figure 7 This is a schematic diagram of the output testing and output calibration logic in one embodiment; wherein, Figure 7 (a) is a schematic diagram of the output test logic. Figure 7 (b) is a schematic diagram of the output calibration logic; Figure 8 This is a schematic diagram of the process for calibrating the closed loop in one embodiment; Figure 9 This is a schematic diagram illustrating the data interaction between the human-computer interaction module, the controller under test, and the test fixture motherboard in one embodiment. Figure 10 This is a schematic diagram of the general switching architecture of the test fixture motherboard in one embodiment; Figure 11 This is a schematic diagram of the calibration parameter writing and retest verification logic in one embodiment; Figure 12 This is a schematic diagram of the content displayed by the human-computer interaction module in one embodiment.

[0023] Figure 13 This is a flowchart illustrating a controller I / O channel testing and calibration method based on dynamic port switching in one embodiment. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0025] In one embodiment, such as Figure 1 As shown, a controller I / O channel testing and calibration device based on dynamic port switching is provided. It includes a test fixture motherboard and a human-machine interface module that interact with the controller under test via a CAN communication bus or an RS485 serial communication bus, as well as a power supply module that supplies power to the test fixture motherboard. The following will describe the various components of the device in detail.

[0026] 1. The power module is used to provide operating power and auxiliary power required for testing to the motherboard of the test fixture.

[0027] 2. The human-machine interaction module has functions such as startup, display, and record export. After power-on, it receives the parameter information of the controller under test input by the user, sends the start test / calibration command to the controller under test, and receives the test, calibration and retest results returned by the controller under test for display, thereby facilitating production line traceability and after-sales analysis.

[0028] 3. The test fixture motherboard includes a microprocessor, a test signal generation unit, a signal matching unit, an IO port matching unit, a signal conditioning and acquisition unit, a calibration control unit, a unique pair of interactive interfaces, and multiple independent motherboard IO ports. It is used to receive and parse the test / calibration instructions sent by the controller under test one by one using the microprocessor, so as to complete the test and calibration of all IO channels under test of the controller under test in sequence. Each test / calibration instruction corresponds to the test / calibration of a pair of IO channels under test with the same test / calibration type, and every two motherboard IO ports form a group and are selectively connected to one IO channel under test.

[0029] The test instructions include a test execution type field, a current test type field, a port mapping field, and a test parameter field. The test execution type field indicates whether an input or output test is currently being performed. The test type field indicates any one of the following: analog voltage input, analog current input, analog resistance input, analog frequency input, digital high-side input, digital low-side input, digital high-side output, or digital low-side output. The port mapping field indicates the corresponding connection between the I / O channel pair under test and a set of motherboard I / O ports. For analog input tests, the test parameter field indicates the definition of the I / O channel pair under test and the values ​​of the voltage, current, resistance, and frequency to be tested. For digital input / output tests, the test parameter field only indicates the definition of the I / O channel pair under test.

[0030] The calibration instruction includes a calibration execution type field, a port mapping field, a calibration point field, and an error threshold field. The calibration execution type field indicates whether input calibration or output calibration is currently being performed. The calibration point field indicates the calibration point sequence, which includes any combination of zero-point calibration points, full-scale calibration points, and one or more intermediate calibration points. The error threshold field indicates the maximum permissible retest error value.

[0031] Specifically, the microprocessor is configured as follows when performing tests / calibrations: (1) When performing input testing, the microprocessor is configured to: first control the test signal generation unit to generate test signals according to the current test type and test parameters, then control the signal selection unit to select one test signal corresponding to the current test type to the interaction interface to form a test signal output path; at the same time, control the IO port selection unit to connect the interaction interface with a set of motherboard IO ports currently selected to form a connection path for the IO channel pair under test; and then dynamically switch the test signal output path and the connection path for the IO channel pair under test based on different test instructions, and output the test signal to the corresponding IO channel pair under test to complete the input test.

[0032] The test signal generation unit is equipped with a DAC (digital-to-analog) converter module, a configurable high-precision resistor box, a frequency signal generation circuit, and a relay switching circuit. The DAC converter module is used to generate the test signals required for analog voltage / current input tests. The configurable high-precision resistor box is used to generate the test signals required for analog resistance input tests. The frequency signal generation circuit is used to generate the test signals required for analog frequency input tests. The relay switching circuit is used to generate the test signals required for digital high-side / low-side input tests.

[0033] The signal selection unit includes a multiplexer and a test signal output enable circuit. The multiplexer is used to generate an enable signal that corresponds one-to-one with the current test type based on the selection signal output by the microprocessor. The test signal output enable circuit is used to connect only one test signal output path corresponding to the current test type based on the enable signal that is in an active state.

[0034] Specifically, such as Figure 2As shown, the test signal output enable circuit consists of an NPN transistor Q301 (model L8050HQLT1G), a relay F301 (model HFD4 / 5-SR), and circuit protection components. The base (B) of the NPN transistor Q301 receives the enable signal through an external current-limiting resistor R301, its emitter (E) is grounded, and its collector (C) is connected to the coil of the relay F301. This allows the transistor to control the conduction state based on the level of the enable signal (SEL_IN_Current), thereby controlling the on / off state of the relay coil contacts and achieving switching control of the signal path connected to the relay. One end of the relay F301 coil is connected to the positive terminal of the power supply (DC5V), and the other end is connected to the collector C of the NPN transistor Q301. It employs a double-pole double-throw structure. When energized, the relay F301 contacts close, connecting the common terminal (pins 4 and 5 of F301) with the normally open terminal (pins 3 and 6 of F301). This allows test signals input through the common terminal (such as the analog voltage input test signals Voltage S1 and Voltage S2) to be output through the unique pair of interfaces connected to the normally open terminal. Otherwise, the relay F301 contacts open, cutting off the test signal output path. Circuit protection components include a pull-down resistor R305 connected between the base B of the NPN transistor Q301 and ground GND to stabilize the base potential; and a Schottky diode D301 (model SS36) connected in parallel across the relay F301 coil to absorb the reverse induced electromotive force generated when the relay coil F301 is de-energized.

[0035] The IO port selection unit includes multiple IO port selection circuits, each corresponding to a set of motherboard IO ports. The microprocessor controls the IO port selection circuits corresponding to the currently selected set of motherboard IO ports to be turned on according to the parsed port mapping field, so as to connect the interaction interface to the currently selected set of motherboard IO ports, thereby outputting the test signal forwarded by the interaction interface to the IO channel pair under test corresponding to the currently selected set of motherboard IO ports, and completing the input test.

[0036] Specifically, such as Figure 3 (a) and Figure 3 As shown in (b), the optional circuitry for each I / O port includes an NPN transistor, a relay, and circuit protection components. Figure 3(a) Taking this as an example, the base B of the NPN transistor Q501 (model L8050HQLTIG) receives the I / O port selection signal through an external current-limiting resistor R501. The emitter E is grounded, and the collector C is connected to the coil of relay F501 (model HFD4 / 5-SR). This control is used to regulate the conduction state based on the I / O port selection signal, thereby controlling the on / off state of the relay F501 coil contacts and achieving switching control of the signal path connected to relay F501. One end of the relay F501 coil is connected to the positive terminal of the power supply, and the other end is connected to the collector C of the NPN transistor Q501. It uses a double-pole double-throw structure; when energized, the relay F501 contacts close, turning the transistor into a single-pole double-throw circuit. When the common terminal (pins 4 and 5 of relay F501) is connected to the normally open terminal (pins 3 and 6 of relay F501), the test signal input from the only pair of interactive interfaces connected to the common terminal is output through the I / O port of the currently selected test fixture motherboard connected to the normally open terminal; otherwise, the relay F501 contacts are open, cutting off the control test signal output path; the circuit protection components include a pull-down resistor R505 connected between the base B of the NPN transistor Q501 and ground GND to stabilize the base potential; and a Schottky diode D501 (model SS36) connected in parallel across the coil of relay F501 to absorb the reverse induced electromotive force generated when the coil of relay F501 is de-energized.

[0037] Specifically, the relays used in the test signal output enable circuit and the IO port selection circuit are both HFD4 / 5-SR miniature electromagnetic relays, which are used to realize the functions of circuit switching and signal control, while preventing electrical interference between different circuits and improving the stability and reliability of the circuit.

[0038] (2) When performing output testing, the microprocessor is configured to: control the IO port selection unit to connect the currently selected set of motherboard IO ports and the interactive interface, transmit signals to the signal conditioning and acquisition unit through the interactive interface to form a signal conditioning and acquisition path, and dynamically switch the signal conditioning and acquisition path based on different test instructions, acquire the corresponding IO channel under test to output signals, and send the acquisition results to the controller under test for test result determination.

[0039] The signal conditioning and acquisition unit includes a signal conditioning circuit and an ADC (analog-to-digital converter) acquisition circuit. The signal conditioning circuit includes one or more of the following: a voltage divider circuit, a filter circuit, an overvoltage protection circuit, and an inverting circuit. The signal conditioning and acquisition unit is used to condition and then acquire the output signal of the I / O channel under test.

[0040] For digital high-side output testing, the signal conditioning circuit in the signal conditioning and acquisition unit is as follows: Figure 4As shown, the system includes: an operational amplifier U403A (model RS222XK), an RC filter network, a power supply filter capacitor C401, and a bidirectional diode D402 (model BAV99). The non-inverting input of the operational amplifier U403A receives the input signal DO_H1 after being divided by a single resistor R407 and filtered by the RC filter network. The output of the operational amplifier U403A outputs DO_V1, and simultaneously feeds DO_V1 back to the inverting input of the operational amplifier U403A, forming a closed-loop control. The RC filter network is connected in parallel between the voltage divider resistor R407 and the non-inverting input of the operational amplifier U403A, and is used to suppress high-frequency noise of the input signal through the series resistor R409 and capacitor C404. The power supply filter capacitor C401 is connected between the power supply terminal of the operational amplifier U403A and ground GND, and is used to filter out high-frequency noise on the power line. The bidirectional diode D402 is connected across the power supply terminal of the operational amplifier U403A and ground, and is used to implement overvoltage protection.

[0041] For digital low-side output testing, the signal conditioning circuit in the signal conditioning and acquisition unit is as follows: Figure 5 As shown, this is an inverting switch circuit composed of an NPN transistor Q402 (model L8050HQLTIG). Its core function is to invert the input signal DO_L_S1 received from the test fixture motherboard. When the input is high, the output is low, and when the input is low, the output is high. Specifically, when the controller under test provides the test signal DO_L, the base of transistor Q402 is pulled high, transistor Q402 conducts, and DO_L1 is low. Conversely, if the controller under test does not provide a test signal, transistor Q402 is cut off, and DO_L1 is high.

[0042] (3) During calibration, the microprocessor is configured to: complete the data interaction between the IO channel pair under test and the corresponding set of motherboard IO ports according to the calibration point sequence obtained by parsing, control the calibration control unit to generate calibration correction data for each calibration point and write it into the calibration parameter storage area of ​​the controller under test, and trigger the corresponding channel retest until the retest result meets the error threshold requirement, thus completing the calibration closed loop.

[0043] For input calibration, the calibration correction data is calculated from the difference between the target value and the actual sampled value at each calibration point, including one or more of the following: zero bias correction value, gain correction value, segmented correction table, and digital threshold correction data. The calibration points include zero-point calibration point, full-scale calibration point, and intermediate calibration point. For output calibration, the calibration correction data is generated from the difference between the actual sampled value at each calibration point and the preset high / low level criteria, including one or more of the following: high-level identification threshold, low-level identification threshold, and hysteresis parameter.

[0044] Based on the above description, the input testing and input calibration logic of the device proposed in this application is as follows: Figure 6 As shown. Figure 6 As shown in (a), the controller under test (DUT) sends an input test command or an input calibration command to the test fixture motherboard. After parsing the input test command, the microprocessor first controls the test signal generation unit to generate the test signals required for the current test type and test parameters. For analog voltage input tests and analog current input tests, the DAC conversion module in the test signal generation unit outputs the target voltage signal or the target current signal; for analog resistance input tests, a high-precision resistance box can be configured to output the target resistance signal; for analog frequency input tests, the frequency signal generation circuit outputs the target frequency signal; for digital high-side input tests and digital low-side input tests, the relay switching circuit outputs high-level signals and low-level signals respectively. After the generated test signals are filtered by the signal matching unit, only one test signal corresponding to the current test type is output through a unique pair of interactive interfaces. Then, the IO port matching unit selects and connects it to the currently selected set of motherboard IO ports, and finally outputs it to the corresponding IO channel pair of the DUT, where the DUT samples and compares the signals to obtain the sampled value, error value, and channel status. Figure 6 As shown in (b), during input calibration, the calibration control unit within the test fixture motherboard outputs corresponding test signals at each calibration point. The controller under test (DUT) collects the actual sampled values ​​at each calibration point and sends them back to the calibration control unit. The calibration control unit calculates the zero-bias correction value, gain correction value, or segmented correction table based on the target value and the collected values, and sends them to the DUT to write to the calibration parameter storage area. After writing, a retest is performed. If the retest error is still greater than the threshold, iterative correction continues; otherwise, the iteration ends, completing the input calibration closed loop.

[0045] The output testing and output calibration logic of the device proposed in this application is as follows: Figure 7 As shown. Figure 7 As shown in (a), in the output test scenario, the controller under test outputs the corresponding high-side output, low-side output, or other output quantities according to the I / O channel under test. The microprocessor in the test fixture motherboard controls the I / O port selection unit to connect the currently selected set of motherboard I / O ports to the interaction interface according to the output test command, and transmits the signal to the signal conditioning and acquisition unit through the interaction interface. The signal conditioning and acquisition unit performs voltage division, filtering, overvoltage protection, or phase inversion processing on the signal under test, and then the ADC acquisition circuit acquires the signal and sends the acquisition result back to the controller under test. The controller under test determines whether the output test is qualified or the output threshold deviation is based on the preset logic and the acquisition result. Figure 7As shown in (b), when the output calibration is performed, the calibration control unit generates calibration correction data such as high-level recognition threshold, low-level recognition threshold or hysteresis parameter based on the difference between the actual acquisition results and the preset high and low level criteria. After the correction data is written into the calibration parameter storage area of ​​the controller under test, the retest is triggered to ensure that the output signal judgment threshold meets the requirements and complete the output calibration closed loop.

[0046] The calibration closed-loop process of the device proposed in this application is as follows: Figure 8 As shown, the process includes receiving calibration commands and locking the channel; executing test signal interaction according to the calibration point sequence; acquiring the actual values ​​of each calibration point; calculating zero bias, gain, or segmented correction data; writing the correction data into the controller parameter area; re-triggering the same channel for retesting; comparing the retest error with the allowable threshold; if the threshold is met, calibration is successful and the calibration version and result are recorded; if the threshold is not met, the calibration correction data is updated and retesting is performed again. Specifically, after receiving the calibration command, the test fixture motherboard completes the data interaction of each calibration point sequentially according to the calibration point sequence; the calibration control unit generates correction data based on the target value and actual sampled value of each calibration point; the controller under test writes the correction data into the calibration parameter storage area after receiving it and sends back a write completion signal. Afterwards, the controller under test performs the corresponding channel retest again. If the retest result meets the error threshold requirement, calibration is complete; otherwise, the next round of correction and retesting continues.

[0047] like Figure 9 As shown, the data interaction between the human-machine interface module, the controller under test (DUT), and the test fixture motherboard of the device proposed in this application includes processes such as sending a start test / calibration command, returning confirmation information, issuing test / calibration commands one by one, transmitting the collected results, issuing calibration correction data, confirming parameter writing, and exporting the results. The human-machine interface module is used to issue the start command and receive the final result; the DUT, as the master control terminal, is used to send test / calibration commands one by one to the test fixture motherboard and is responsible for completing the result judgment and parameter writing; the test fixture motherboard is used to complete the test signal generation, path switching, signal acquisition, and correction data calculation.

[0048] like Figure 10 As shown, the device proposed in this application uses a signal matching unit and an IO port matching unit in conjunction with a unique pair of interactive interfaces to achieve dynamic switching of the test signal output path and the connection path of the IO channel under test; and uses the IO port matching unit in conjunction with the signal conditioning and acquisition unit in conjunction with this unique pair of interactive interfaces to achieve dynamic switching of the signal conditioning and acquisition path. Based on the above-mentioned unified path switching mechanism, various test types can share this unique pair of interactive interfaces and the same port switching architecture. With this architecture, there is no need to redesign dedicated wiring and dedicated interfaces for different controllers or different channels, thereby reducing tooling complexity and shortening production line changeover time.

[0049] like Figure 11 As shown, the calibration parameter writing and retest verification logic of the device proposed in this application is as follows: after receiving the calibration correction data generated by the calibration control unit, the controller under test writes the calibration correction data into the calibration parameter storage area and returns a write completion message; then, the controller under test triggers the corresponding channel retest again to obtain the calibrated sample value or judgment result.

[0050] like Figure 12 As shown, the human-computer interaction module in the device proposed in this application displays the channel number, sampled values ​​before and after calibration, error change, correction coefficient version number, and result status, enabling testers to intuitively see the calibration effect. If archiving is required, the results can be exported to an external storage medium.

[0051] In summary, the device proposed in this application uses the test / calibration commands sent sequentially by the controller under test as the process-driven basis, enabling the test fixture motherboard to dynamically perform tests and calibrations for different controllers, different port mappings, and different test types, thus improving its general adaptability. Furthermore, by providing a single pair of interactive interfaces that can be shared across various test types and a unified port switching architecture, dynamic switching between different signal sources and different port groups can be completed solely based on test commands, eliminating the need for additional hardware links. This effectively reduces the number of dedicated test links, simplifies hardware layout, and significantly improves the reusability of the fixture structure and the versatility of the test system. Moreover, by integrating test signal generation, dynamic switching output based on test commands, signal conditioning and acquisition, and calibration control functions within the test fixture motherboard, signal transmission links are shortened, reducing the number of external devices and helping to reduce noise and error introduction. Finally, by introducing a calibration control unit and a calibration correction data writing mechanism, testing, calibration, parameter writing, and retesting form a closed loop, which not only determines whether a channel is qualified but also automatically corrects channel errors, improving product consistency. In one application example, the device proposed in this application is used for the integrated testing and calibration of multiple analog input and digital output channels of a controller. For the analog input channels, input calibration is performed at three calibration points: 0V, 5V, and 10V. For the digital output channels, output calibration is performed at high-level and low-level thresholds. The test fixture motherboard completes test signal generation, path switching output, signal acquisition, and correction data calculation. The controller under test completes parameter writing and retest verification. The human-machine interface module displays the data throughout the process. Using this scheme, the testing, calibration, parameter writing, and retesting of multiple channels can be completed sequentially in a single power-on process, improving the automation level of controller I / O channel testing and calibration and reducing manual intervention.

[0052] In one embodiment, such as Figure 13As shown, a method for testing and calibrating controller I / O channels based on dynamic port switching is provided. This method is implemented based on the aforementioned device for testing and calibrating controller I / O channels based on dynamic port switching, and includes the following steps: S1. After the device is powered on, the human-machine interface module receives the parameter information of the controller under test input by the user and sends a start test / calibration command to the controller under test. S2. The controller under test returns test confirmation information and sends test / calibration commands to the test fixture motherboard one by one according to the preset logic; S3. The microprocessor in the test fixture motherboard receives and parses each test / calibration command; S4. When performing an input test, the microprocessor first controls the test signal generation unit to generate a test signal according to the current test type and test parameters, and then controls the signal selection unit to select one of the test signals corresponding to the current test type to the interaction interface, forming a test signal output path; at the same time, it controls the IO port selection unit to connect the interaction interface with the currently selected set of motherboard IO ports, forming a connection path for the IO channel pair under test; then, based on different test instructions, it dynamically switches the test signal output path and the connection path for the IO channel pair under test, and outputs the test signal to the corresponding IO channel pair under test to complete the input test; S5. When the output test is performed, the microprocessor controls the IO port selection unit to connect the currently selected set of motherboard IO ports and the interaction interface, and transmits the signal to the signal conditioning and acquisition unit through the interaction interface to form a signal conditioning and acquisition path. The signal conditioning and acquisition path is dynamically switched based on different test commands to acquire the output signal of the corresponding IO channel under test, and the acquisition result is sent to the controller under test for test result judgment. S6. During calibration, the microprocessor completes the data interaction between the I / O channel pair under test and the corresponding set of motherboard I / O ports according to the calibration point sequence obtained by parsing. It controls the calibration control unit to generate calibration correction data for each calibration point and writes it into the calibration parameter storage area of ​​the controller under test. After the controller under test completes the writing of calibration parameters, it triggers the retest of the corresponding channel. If the retest error is not greater than the error threshold, the calibration is determined to be successful. Otherwise, the next round of correction and retest continues. S7. The controller under test feeds back the test, calibration and retest results to the human-computer interaction module for display and export.

[0053] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0054] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A controller IO lane test and calibration device based on dynamic port switching, comprising: The device includes: a test fixture motherboard and a human-machine interface module that interact with the controller under test via a communication bus, and a power supply module that supplies power to the test fixture motherboard. The human-machine interaction module is used to receive the parameter information of the controller under test input by the user after power-on, send the start test / calibration command to the controller under test, and receive and display the test, calibration and retest results returned by the controller under test. The test fixture motherboard includes a microprocessor, a test signal generation unit, a signal matching unit, an IO port matching unit, a signal conditioning and acquisition unit, a calibration control unit, a unique pair of interactive interfaces, and multiple independent motherboard IO ports. It is used to receive and parse the test / calibration instructions sent by the controller under test one by one using the microprocessor, so as to complete the test and calibration of all IO channels under test of the controller under test in sequence. Each test / calibration instruction corresponds to the test / calibration of a pair of IO channels under test with the same test / calibration type, and every two motherboard IO ports form a group and are selectively connected to an IO channel under test. The microprocessor is configured as follows: During input testing, the test signal generation unit first generates a test signal based on the current test type and test parameters. Then, the signal selection unit selects the corresponding test signal for the current test type and sends it to the interactive interface, forming a test signal output path. Simultaneously, the IO port selection unit connects the interactive interface to the currently selected set of motherboard IO ports, forming a connection path for the IO channel pair under test. Furthermore, the test signal output path and the connection path for the IO channel pair under test are dynamically switched based on different test commands, and the test signal is output to the corresponding IO channel pair under test to complete the input test. During output testing, the control IO port selection unit connects the currently selected set of motherboard IO ports to the interaction interface, transmits signals to the signal conditioning and acquisition unit through the interaction interface, forms a signal conditioning and acquisition path, and dynamically switches the signal conditioning and acquisition path based on different test commands to acquire the output signals of the corresponding IO channel under test, and sends the acquisition results to the controller under test for test result determination. During calibration, the data interaction between the I / O channel pair under test and the corresponding set of motherboard I / O ports is completed according to the calibration point sequence obtained by parsing. The calibration control unit is controlled to generate calibration correction data for each calibration point and write it into the calibration parameter storage area of ​​the controller under test. After writing, the corresponding channel is retested until the retest result meets the error threshold requirement, thus completing the calibration closed loop. The device uses a signal matching unit and an IO port matching unit to work together with a unique pair of interactive interfaces to achieve dynamic switching of the test signal output path and the connection path of the IO channel under test; and uses an IO port matching unit to work together with a unique pair of interactive interfaces to achieve dynamic switching of the signal conditioning and acquisition path; relying on a unified path switching mechanism, all types of tests share a unique pair of interactive interfaces and the same set of port switching architecture. After adopting the architecture, there is no need to redesign dedicated wiring and dedicated interfaces for different controllers or different channels, thereby reducing tooling complexity and shortening production line changeover time; The test instructions include a test execution type field, a current test type field, a port mapping field, and a test parameter field. The test execution type field indicates whether an input test or an output test is currently being performed. The test type field indicates any one of the following: analog voltage input, analog current input, analog resistance input, analog frequency input, digital high-side input, digital low-side input, digital high-side output, or digital low-side output. The port mapping field indicates the corresponding connection between the I / O channel pair under test and a set of motherboard I / O ports. For analog input tests, the test parameter field indicates the definition of the I / O channel pair under test and the values ​​of the voltage, current, resistance, and frequency to be tested. For digital input / output tests, the test parameter field only indicates the definition of the I / O channel pair under test. The calibration instruction includes a calibration execution type field, a port mapping field, a calibration point field, and an error threshold field; the calibration execution type field is used to indicate whether input calibration or output calibration is currently being performed; the calibration point field is used to indicate a calibration point sequence, which includes any combination of zero-point calibration points, full-scale calibration points, and one or more intermediate calibration points; the error threshold field is used to indicate the maximum permissible retest error value.

2. The controller IO lane test and calibration device based on dynamic port switching of claim 1, wherein, The test signal generation unit is equipped with a DAC conversion module, a configurable high-precision resistor box, a frequency signal generation circuit, and a relay switching circuit. The DAC conversion module is used to generate the test signals required for analog voltage / current input testing; The configurable high-precision resistance box is used to generate the test signal required for analog resistance input testing. The frequency signal generation circuit is used to generate the test signal required for analog frequency input testing. The relay switching circuit is used to generate the test signal required for digital high-side / low-side input testing.

3. The controller I / O channel testing and calibration device based on dynamic port switching according to claim 1, characterized in that, The signal selection unit includes a multiplexer and a test signal output enable circuit; the multiplexer is used to generate an enable signal that corresponds one-to-one with the current test type based on the selection signal output by the microprocessor; the test signal output enable circuit is used to connect only one test signal output path corresponding to the current test type based on the enable signal that is in an active state.

4. The controller I / O channel testing and calibration device based on dynamic port switching according to claim 3, characterized in that, The test signal output enable circuit consists of an NPN transistor, a relay, and circuit protection components. The base of the NPN transistor receives an enable signal through an external current-limiting resistor, the emitter is grounded, and the collector is connected to the relay coil. This is used to control the conduction state according to the level of the enable signal, thereby controlling the on / off state of the relay coil contacts and realizing the switching control of the signal path connected to the relay. One end of the relay coil is connected to the positive terminal of the power supply, and the other end is connected to the collector of the NPN transistor. It adopts a double-pole double-throw structure. When energized, the relay contacts close, connecting the common terminal with the normally open terminal, so that the test signal input through the common terminal is output through the only pair of interactive interfaces connected to the normally open terminal; otherwise, the relay contacts open, cutting off the control test signal output path. The circuit protection element includes a pull-down resistor connected between the base of the NPN transistor and ground to stabilize the base potential; and a Schottky diode connected in parallel across the relay coil to absorb the reverse induced electromotive force generated when the relay coil is de-energized.

5. The controller I / O channel testing and calibration device based on dynamic port switching according to claim 1, characterized in that, The IO port selection unit includes multiple IO port selection circuits, each corresponding to a set of motherboard IO ports. The microprocessor controls the IO port selection circuits corresponding to the currently selected set of motherboard IO ports to be turned on according to the parsed port mapping field, so as to connect the interaction interface to the currently selected set of motherboard IO ports, thereby outputting the test signal forwarded by the interaction interface to the IO channel pair under test corresponding to the currently selected set of motherboard IO ports to complete the input test.

6. The controller I / O channel testing and calibration device based on dynamic port switching according to claim 5, characterized in that, The optional circuitry for each I / O port includes NPN transistors, relays, and circuit protection components; The base of the NPN transistor receives the I / O port selection signal through an external current-limiting resistor, the emitter is grounded, and the collector is connected to the relay coil. It is used to control the conduction state according to the I / O port selection signal, and then control the on / off state of the relay coil contacts to realize the switching control of the signal path connected to the relay. One end of the relay coil is connected to the positive terminal of the power supply, and the other end is connected to the collector of the NPN transistor. It adopts a double-pole double-throw structure. When energized, the relay contacts close, connecting the common terminal and the normally open terminal. This allows the test signal input through the only pair of interactive interfaces connected to the common terminal to be output through the I / O port of the currently selected test fixture motherboard connected to the normally open terminal. Otherwise, the relay contacts open, cutting off the control test signal output path. The circuit protection element includes a pull-down resistor connected between the base of the NPN transistor and ground to stabilize the base potential; and a Schottky diode connected in parallel across the relay coil to absorb the reverse induced electromotive force generated when the relay coil is de-energized.

7. The controller I / O channel testing and calibration device based on dynamic port switching according to claim 1, characterized in that, The signal conditioning and acquisition unit includes a signal conditioning circuit and an ADC acquisition circuit. The signal conditioning circuit includes one or more of the following: a voltage divider circuit, a filter circuit, an overvoltage protection circuit, and an inverting processing circuit. The signal conditioning and acquisition unit is used to condition the output signal of the IO channel under test before acquisition.

8. The controller I / O channel testing and calibration device based on dynamic port switching according to claim 1, characterized in that, For input calibration, the calibration correction data is calculated from the difference between the target value and the actual sampled value at each calibration point, including one or more of the following: zero bias correction value, gain correction value, segmented correction table and digital threshold correction data. The calibration points include zero calibration point, full scale calibration point and intermediate calibration point. For output calibration, the calibration correction data is generated by the difference between the actual sampled value of each calibration point and the preset high and low level criteria, including one or more of the high level identification threshold, low level identification threshold and hysteresis parameter.

9. A method for testing and calibrating controller I / O channels based on dynamic port switching, characterized in that, The method is implemented based on the controller I / O channel testing and calibration device based on dynamic port switching as described in any one of claims 1-8, and includes the following steps: S1. After the device is powered on, the human-machine interface module receives the parameter information of the controller under test input by the user and sends a start test / calibration command to the controller under test. S2. The controller under test returns test confirmation information and sends test / calibration commands to the test fixture motherboard one by one according to the preset logic; S3. The microprocessor in the test fixture motherboard receives and parses each test / calibration command; S4. When performing an input test, the microprocessor first controls the test signal generation unit to generate a test signal according to the current test type and test parameters, and then controls the signal selection unit to select one of the test signals corresponding to the current test type to the interaction interface, forming a test signal output path; at the same time, it controls the IO port selection unit to connect the interaction interface with the currently selected set of motherboard IO ports, forming a connection path for the IO channel pair under test; then, based on different test instructions, it dynamically switches the test signal output path and the connection path for the IO channel pair under test, and outputs the test signal to the corresponding IO channel pair under test to complete the input test; S5. When the output test is performed, the microprocessor controls the IO port selection unit to connect the currently selected set of motherboard IO ports and the interaction interface, and transmits the signal to the signal conditioning and acquisition unit through the interaction interface to form a signal conditioning and acquisition path. The signal conditioning and acquisition path is dynamically switched based on different test commands to acquire the output signal of the corresponding IO channel under test, and the acquisition result is sent to the controller under test for test result judgment. S6. During calibration, the microprocessor completes the data interaction between the I / O channel pair under test and the corresponding set of motherboard I / O ports according to the calibration point sequence obtained by parsing. It controls the calibration control unit to generate calibration correction data for each calibration point and writes it into the calibration parameter storage area of ​​the controller under test. After the controller under test completes the writing of calibration parameters, it triggers the retest of the corresponding channel. If the retest error is not greater than the error threshold, the calibration is determined to be successful. Otherwise, the next round of correction and retest continues. S7. The controller under test feeds back the test, calibration and retest results to the human-computer interaction module for display and export.

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