A data read-write method, device and program product based on a memory barrier instruction
By checking and adjusting the memory barrier instructions in the user program, the problem of incorrect or missing barrier instructions in multi-core RISC-V CPUs was solved, improving system performance and stability and ensuring the accuracy of memory operations.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2026-04-17
- Publication Date
- 2026-07-14
Smart Images
Figure CN122044663B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of processor technology, and in particular to a data read / write method, device, and program product based on memory barrier instructions. Background Technology
[0002] RISC-V (an open instruction set architecture) allows processors and compilers to reorder memory operations by default (such as out-of-order execution, write buffering, and cache optimization) to improve performance. However, barriers are needed to enforce memory access order in the following scenarios: in multi-core concurrency scenarios, different cores may see inconsistent memory states; in device access scenarios, peripheral registers (Memory-Mapped I / O, MMIO) must be accessed strictly in order. RISC-V does not guarantee that a write operation on one core is immediately visible to other cores (due to cache coherency protocol delays). Memory barriers need to ensure that read operations obtain the latest values (avoiding reading outdated cache). Because memory barrier instructions are not automatically generated by the compiler but must be manually added by CPU (Central Processing Unit) program developers, there are significant risks: if a developer mistakenly adds a memory barrier instruction where it is not needed, it can cause the CPU pipeline to stall, introducing tens or even hundreds of clock delays and greatly reducing the performance of a multi-core RISC-V CPU; if a developer adds too few memory barrier instructions where they are needed, it can lead to multi-core concurrent access errors or device access errors, directly causing functional errors in the multi-core RISC-V CPU.
[0003] Therefore, how to improve the accuracy of the memory barrier function of multi-core RISC-V CPUs, and improve the overall performance of multi-core RISC-V CPUs without affecting their normal function, is a problem to be solved in this field. Summary of the Invention
[0004] The purpose of this invention is to provide a data read / write method based on memory barrier instructions, which can solve the problem of performance degradation or functional errors caused by manually adding memory barrier instructions.
[0005] To address the aforementioned technical problems, in a first aspect, embodiments of the present invention provide a data read / write method based on memory barrier instructions, applied to a multi-core instruction set processor, comprising:
[0006] Identify the initial memory barrier instruction in the currently running user program code; the initial memory barrier instruction is a barrier instruction added by the user.
[0007] The initial memory barrier instruction is checked using preset barrier instruction check conditions to obtain the corresponding check results; the preset barrier instruction check conditions are instruction deletion conditions and instruction addition conditions constructed based on the execution order of multi-core instructions.
[0008] The initial memory barrier instruction is adjusted based on the inspection results, and subsequent data read and write operations are performed based on the adjusted target barrier instruction.
[0009] In some embodiments, determining the initial memory barrier instruction in the currently running user program code includes:
[0010] Read a binary program file from memory;
[0011] Run the user program code in the program file and identify the initial memory barrier instruction in the user program code.
[0012] In some embodiments, the step of checking the initial memory barrier instruction using preset barrier instruction check conditions to obtain corresponding check results includes:
[0013] The initial memory barrier instruction is checked based on the condition of unnecessary deletion of barrier instructions, and the corresponding first check result is obtained.
[0014] The initial memory barrier instruction is checked based on the necessity of the barrier instruction, and the corresponding second check result is obtained.
[0015] Accordingly, adjusting the initial memory barrier instruction based on the inspection results includes:
[0016] The initial memory barrier instruction is adjusted based on the first check result and the second check result; the adjustment operation is a conversion operation, a deletion operation, or an addition operation.
[0017] In some embodiments, if the initial memory barrier instruction is a full barrier instruction, then the initial memory barrier instruction is checked based on the barrier instruction non-essential pruning condition to obtain a corresponding first check result, including:
[0018] Examine the behavior pattern of multiple cores performing read and write operations on the same address before and after the full-barrier instruction;
[0019] If the behavior pattern indicates that each core of the multi-core system performs only read or write operations on the same address, then a first check result is generated indicating that the full barrier instruction is converted into a read barrier instruction or a write barrier instruction; wherein, the read barrier instruction corresponds to a read operation, and the write barrier instruction corresponds to a write operation;
[0020] If the behavior pattern indicates that each core of the multi-core performs a write-then-read operation on the same address, then a first check result is generated indicating that the full barrier instruction is converted into a write-after-read barrier instruction.
[0021] In some embodiments, if the initial memory barrier instruction is a write barrier instruction, then the initial memory barrier instruction is checked based on the barrier instruction non-essential pruning condition to obtain a corresponding first check result, including:
[0022] If the register for the write operation corresponding to the write barrier instruction is a register with a configured order issued by the user, then the behavior mode of the write barrier instruction is determined.
[0023] If the behavior pattern does not indicate that multiple cores perform write operations on the same address before and after the write barrier instruction, a first check result indicating that the write barrier instruction has been deleted is generated.
[0024] In some embodiments, if the initial memory barrier instruction is a read barrier instruction, then the initial memory barrier instruction is checked based on the barrier instruction non-essential pruning condition to obtain a corresponding first check result, including:
[0025] If the register for the read operation corresponding to the read barrier instruction is not a register in the configured order issued by the user, a first check result representing the deletion of the read barrier instruction is generated.
[0026] In some embodiments, if the initial memory barrier instruction is a read-after-write barrier instruction, then the initial memory barrier instruction is checked based on the barrier instruction non-essential pruning condition to obtain a corresponding first check result, including:
[0027] If the destination register of the previous write operation corresponding to the write-after-read barrier instruction is not the source register of the next read operation, a first check result representing the deletion of the write-after-read barrier instruction is generated.
[0028] In some embodiments, the step of checking the initial memory barrier instruction based on the necessity of the barrier instruction to obtain a corresponding second check result includes:
[0029] If the initial memory barrier instruction does not include a full barrier instruction, and the user program code represents each core performing a read or write operation on the same address, then a second check result representing the addition of a full barrier instruction is generated.
[0030] In some embodiments, the step of checking the initial memory barrier instruction based on the necessity of the barrier instruction to obtain a corresponding second check result includes:
[0031] If the initial memory barrier instruction does not include a full barrier instruction, and the user program code represents the sequential read and write operations performed by each core on different addresses, then a second check result representing the addition of a full barrier instruction is generated.
[0032] In some embodiments, the step of checking the initial memory barrier instruction based on the necessity of the barrier instruction to obtain a corresponding second check result includes:
[0033] If the initial memory barrier instruction does not include a write barrier instruction, and the scenario corresponding to the user program code contains a user-issued register with a configured order, then a second check result representing the addition of a write barrier instruction is generated.
[0034] In some embodiments, the step of checking the initial memory barrier instruction based on the necessity of the barrier instruction to obtain a corresponding second check result includes:
[0035] If the initial memory barrier instruction does not include a write barrier instruction, and the user program code represents that each core performs write operations to the same address sequentially, then a second check result representing the addition of a write barrier instruction is generated.
[0036] In some embodiments, the step of checking the initial memory barrier instruction based on the necessity of the barrier instruction to obtain a corresponding second check result includes:
[0037] If the initial memory barrier instruction does not include a read barrier instruction, and the scenario corresponding to the user program code contains a user-issued register with a configured order, then a second check result representing the addition of a read barrier instruction is generated.
[0038] In some embodiments, the step of checking the initial memory barrier instruction based on the necessity of the barrier instruction to obtain a corresponding second check result includes:
[0039] If the initial memory barrier instruction does not include a read-after-write barrier instruction, and there is a scenario in the user program code where the destination register of the previous write operation is the source register of the next read operation, then a second check result representing the addition of a read-after-write barrier instruction is generated.
[0040] In a second aspect, the present invention provides an electronic device, comprising:
[0041] Memory, used to store computer programs;
[0042] A processor for executing the computer program to implement the steps of the data read / write method based on memory barrier instructions as described above.
[0043] Thirdly, the present invention provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the data read / write method based on the memory barrier instruction described above.
[0044] As can be seen from the above technical solution, the technical solution of this application can be applied to multi-core instruction set processors. First, the initial memory barrier instruction in the currently running user program code is determined; the initial memory barrier instruction is a barrier instruction added by the user. Then, the initial memory barrier instruction is checked using preset barrier instruction check conditions to obtain the corresponding check results. The preset barrier instruction check conditions are instruction deletion conditions and instruction addition conditions constructed based on the execution order of multi-core instructions. Afterwards, the initial memory barrier instruction is adjusted according to the check results, and subsequent data read / write operations are performed based on the adjusted target barrier instruction. Therefore, this application combines the conditions pre-constructed based on the execution order of multi-core instructions to control read operations and obtain the latest data value to check the initial memory barrier instruction in the user program code. This avoids the drawbacks of traditional solutions where developers add memory barrier instructions where unnecessary or add memory barrier instructions of unnecessary levels, reducing the impact of barrier instructions on the performance of multi-core instruction set processors. Simultaneously, adjusting the barrier instruction based on the check results before performing read / write operations ensures the accuracy of the memory barrier function and improves the performance, overall security, and stability of multi-core instruction set processors. Attached Figure Description
[0045] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0046] Figure 1 A flowchart of a data read / write method based on memory barrier instructions provided in an embodiment of the present invention;
[0047] Figure 2 This invention provides a schematic diagram of a data read / write system architecture based on memory barrier instructions.
[0048] Figure 3 This is a structural diagram of a barrier instruction non-essential deletion module provided in an embodiment of the present invention;
[0049] Figure 4 A structural diagram of a barrier instruction necessity addition module provided in an embodiment of the present invention;
[0050] Figure 5This is a schematic diagram of a data read / write device based on memory barrier instructions provided in an embodiment of the present invention;
[0051] Figure 6 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation
[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.
[0053] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.
[0054] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0055] like Figure 1 This embodiment discloses a data read / write method based on memory barrier instructions, applied to a multi-core instruction set processor, and may include:
[0056] Step S11: Determine the initial memory barrier instruction in the currently running user program code; the initial memory barrier instruction is a barrier instruction added by the user.
[0057] In scenarios involving multi-core concurrency and device access, users need to add memory barrier instructions during program development to ensure that read operations obtain the latest data values, thus avoiding reading outdated caches. First, the memory barrier instructions in the currently running user program code can be identified and denoted as the initial memory barrier instructions. It should be noted that the multi-core instruction set processor in this technical solution refers to a multi-core RISC-V CPU, a multi-processor design based on the open-source RISC-V instruction set architecture, widely used in embedded systems, high-performance computing, and artificial intelligence acceleration.
[0058] In a specific embodiment, in the process of determining the initial memory barrier instruction in the currently running user program code, a binary program file is first read from memory. It is understood that the program file is a binary file generated by compiling the code after adding the memory barrier instruction, and it is waiting to be executed in memory. Accordingly, the user program code in the program file is executed, and when the corresponding memory barrier instruction is executed, the initial memory barrier instruction in the user program code is determined.
[0059] Step S12: Use the preset barrier instruction check conditions to check the initial memory barrier instruction and obtain the corresponding check results; the preset barrier instruction check conditions are instruction deletion conditions and instruction addition conditions constructed based on the execution order of multi-core instructions.
[0060] In this embodiment, the initial memory barrier instruction in the user program code can be determined through the above steps; then, the initial memory barrier instruction is checked using the pre-built barrier instruction check conditions. It should be noted that RISC-V allows the processor or compiler to reorder the execution order of memory operations (such as out-of-order execution, write buffering, cache optimization, etc.) to avoid reading outdated cache. Based on this, conditions for controlling read operations to obtain the latest value of data can be constructed, that is, the barrier instruction check conditions are obtained.
[0061] In one specific embodiment, during the process of checking the initial memory barrier instruction using preset barrier instruction check conditions to obtain the corresponding check results, the initial memory barrier instruction is first checked based on the barrier instruction unnecessary deletion condition to obtain the corresponding first check result; then, the initial memory barrier instruction is checked based on the barrier instruction necessary addition condition to obtain the corresponding second check result; correspondingly, the process of adjusting the initial memory barrier instruction according to the check results involves adjusting the initial memory barrier instruction based on the first and second check results; the adjustment operation is a conversion operation, a deletion operation, or an addition operation. Specifically, checking the initial memory barrier instruction involves checking for barrier instruction unnecessary deletion and checking for barrier instruction necessary addition, obtaining two corresponding check results; then, the initial memory barrier instruction is adjusted based on the two check results. Understandably, checking for unnecessary removal of barrier instructions and adjusting them based on the results of these checks can reduce the impact of barrier instructions on the performance of multi-core RISC-V CPUs. Checking for necessary addition of barrier instructions and adjusting them based on the results of these checks can ensure the correctness of multi-core RISC-V CPU functions, thereby improving the overall security and stability of RISC-V CPUs.
[0062] Furthermore, the check for unnecessary removal of barrier instructions involves full barrier instructions, write barrier instructions, read barrier instructions, and write-after-read barrier instructions. In a specific embodiment, if the initial memory barrier instruction is a full barrier instruction, the behavior pattern of multiple cores performing read and write operations on the same address before and after the full barrier instruction is checked. This behavior pattern can be divided into two types: for behavior patterns indicating that each core of multiple cores performs only read or write operations on the same address, a first check result is generated indicating that the full barrier instruction is converted into a read barrier instruction or a write barrier instruction; where read barrier instructions correspond to read operations, and write barrier instructions correspond to write operations; and for behavior patterns indicating that each core of multiple cores performs write operations on the same address before reading, a first check result is generated indicating that the full barrier instruction is converted into a write-after-read barrier instruction. It is understood that the above two behavior patterns can be summarized as producer-consumer behavior patterns, while for non-producer-consumer behavior patterns, the existence of read and write operations on the same address can be considered to convert the full barrier instruction into a read barrier instruction or a write barrier instruction.
[0063] In a specific embodiment, when the initial memory barrier instruction is a write barrier instruction, the behavior pattern of the write barrier instruction is determined by considering the user-issued registers with strong configuration order requirements. That is, the registers for the write operation corresponding to the write barrier instruction are registers with a pre-configured order issued by the user. Here, the behavior pattern is that multiple cores before and after the barrier instruction perform write operations on the same address. In this case, a first check result representing the deletion of the write barrier instruction can be generated. It is understandable that if the write barrier instruction does not meet this condition, it can be directly deleted, and an interrupt message can be generated to remind the user to make corrections.
[0064] In a specific embodiment, if the initial memory barrier instruction is a read barrier instruction, and the register corresponding to the read operation of the read barrier instruction is not a register in the user-configured order, then a first check result representing the deletion of the read barrier instruction is generated. It is understood that an interrupt message may be generated simultaneously with the generation of the first check result to remind the user to make corrections. If the register corresponding to the read operation of the read barrier instruction is not a register in the user-configured order, then the barrier instruction remains unchanged.
[0065] In a specific embodiment, if the initial memory barrier instruction is a write-after-read barrier instruction, and the destination register of the previous write operation corresponding to the write-after-read barrier instruction is not the source register of the next read operation, then a first check result representing the deletion of the write-after-read barrier instruction is generated. It is understood that an interrupt message can be generated simultaneously with the generation of the first check result to remind the user to make corrections. Conversely, if the destination register of the previous write operation corresponding to the write-after-read barrier instruction is the source register of the next read operation, then the barrier instruction remains unchanged.
[0066] Furthermore, the check for the necessity of adding barrier instructions involves full barrier instructions, write barrier instructions, read barrier instructions, and write-after-read barrier instructions. In a specific embodiment, if the initial memory barrier instructions do not include full barrier instructions, and the scenario corresponding to the user program code represents multiple cores performing read or write operations on the same address, then a second check result representing the addition of a full barrier instruction is generated. It is understood that read and write operations on the same memory address by multiple cores trigger the addition of a full barrier instruction, thus generating the second check result representing the addition of a full barrier instruction.
[0067] In a specific embodiment, if the initial memory barrier instruction does not include a full barrier instruction, and the scenario corresponding to the user program code represents multiple cores performing sequential read and write operations on different addresses, then a second check result representing the addition of a full barrier instruction is generated. That is, the producer-consumer behavior pattern among the multiple cores also triggers the operation of adding a full barrier instruction, thus generating a second check result representing the addition of a full barrier instruction.
[0068] In a specific embodiment, if the initial memory barrier instruction does not include a write barrier instruction, and the scenario corresponding to the user program code contains a user-issued register with a configured order, then a second check result representing the addition of a write barrier instruction is generated. It is understood that if the user issues a register with a strong requirement for configured order, the write barrier instruction addition operation needs to be triggered, thus generating a second check result representing the addition of a write barrier instruction.
[0069] In a specific embodiment, if the initial memory barrier instruction does not include a write barrier instruction, and the scenario corresponding to the user program code represents multiple cores performing sequential write operations on the same address, then a second check result representing the addition of a write barrier instruction is generated. That is, when multiple cores perform write operations on the same address, it is necessary to trigger the addition of a write barrier instruction, thus generating a second check result representing the addition of a write barrier instruction.
[0070] In a specific embodiment, if the initial memory barrier instruction does not include a read barrier instruction, and the scenario corresponding to the user program code contains a user-issued register with a configured order, then a second check result representing the addition of a read barrier instruction is generated. It is understood that if the barrier instruction detects a user-issued register with a strong read order requirement, and no read barrier instruction exists, then the addition of a read barrier instruction needs to be triggered, i.e., a second check result representing the addition of a read barrier instruction is generated.
[0071] In a specific embodiment, if the initial memory barrier instruction does not include a read-after-write barrier instruction, and the scenario corresponding to the user program code includes a scenario where the destination register of the previous write operation is the source register of the next read operation, then a second check result representing the addition of a read-after-write barrier instruction is generated. It is understood that if the destination register of a write operation is detected to be the source register of an adjacent read operation, and no read-after-write barrier instruction exists, then the addition of a read-after-write barrier instruction needs to be triggered, i.e., a second check result representing the addition of a read-after-write barrier instruction is generated.
[0072] Step S13: Adjust the initial memory barrier instruction according to the inspection results, and perform subsequent data read and write operations based on the adjusted target barrier instruction.
[0073] In this embodiment, the initial memory barrier indicators can be checked through the above steps to obtain corresponding check results. These results may include a first check result obtained from non-essential checks and a second check result obtained from essential checks. Then, the initial memory barrier instructions can be adjusted based on the first and second check results. The barrier instruction adjustment process involves adding full barriers, adding write barriers, adding read barriers, adding post-write read barriers, and removing full barriers, writing barriers, reading barriers, and post-write read barriers. Subsequent data read and write operations are then performed based on the adjusted target barrier instructions. This checking allows for the conversion, removal, or addition of necessary barrier instructions, ensuring the correctness of multi-core RISC-V CPU functions and thus improving the overall security and stability of the RISC-V CPU.
[0074] In a specific embodiment, during the adjustment of the initial memory barrier instruction based on the inspection results, the corresponding first and second inspection results can be analyzed first, and then integrated into a final target inspection result. Subsequently, the adjustment operation of the initial memory barrier instruction is triggered based on this target inspection result. Alternatively, the initial memory barrier instruction can be adjusted directly using the first and second inspection results respectively, resulting in two adjustment results. These two adjustment results are then analyzed and integrated to obtain the final target barrier instruction. It is understood that those skilled in the art can choose any of the above methods to adjust the initial memory barrier instruction according to actual needs.
[0075] Therefore, this application combines the conditions pre-constructed based on the execution order of multi-core instructions to control read operations and obtain the latest data value to check the initial memory barrier instructions in the user program code. This avoids the drawbacks of traditional solutions where developers add memory barrier instructions where they are unnecessary or add memory barrier instructions of unnecessary levels, thus reducing the impact of barrier instructions on the performance of multi-core instruction set processors. At the same time, by adjusting the barrier instructions based on the check results before executing read and write operations, the accuracy of the memory barrier function can be guaranteed, improving the performance of multi-core instruction set processors, as well as overall security and stability.
[0076] like Figure 2 As shown in the diagram, this embodiment discloses a data read / write system architecture based on memory barrier instructions, specifically including:
[0077] As can be seen, this embodiment can add a barrier instruction processing module, which is specifically divided into two modules: a barrier instruction unnecessary removal module and a barrier instruction necessary addition module. The barrier instruction unnecessary removal module performs necessity checks on barrier instructions and converts or deletes them based on the check results to reduce their impact on the performance of the multi-core RISC-V CPU. The barrier instruction necessary addition module checks the necessity of adding barrier instructions to multi-core CPUs and adds necessary barrier instructions based on the check results to ensure the correctness of the multi-core RISC-V CPU's functions, thereby improving the overall security and stability of the RISC-V CPU and promoting its commercial application in high-performance processor scenarios.
[0078] On the one hand, such as Figure 3 The diagram shows the structure of the barrier instruction non-essential reduction module, which contains five sub-modules: full barrier reduction, write barrier reduction, read barrier reduction, post-write read barrier reduction, and barrier conversion. This module performs necessity checks on four types of barrier instructions and converts or deletes them based on the results. Conversion refers to downgrading barrier instructions, such as converting a full barrier instruction to a write barrier instruction; deletion directly removes the corresponding barrier instruction. The purpose of these operations is to reduce the impact of barrier instructions on the performance of multi-core RISC-V CPUs. The barrier instruction levels are defined according to their impact on multi-core RISC-V CPU performance (performance overhead) or the instruction pipeline; specifically, there are two levels: Level 1 corresponds to full barrier instructions, and Level 2 corresponds to write barrier instructions, read barrier instructions, and post-write read barrier instructions. Table 1 below is a format parsing table for barrier instructions.
[0079] Table 1. Format Analysis of Barrier Commands
[0080]
[0081] Specifically, the full-barrier pruning submodule first reads the instructions to be executed by the RISC-V Core from the cache. Based on the instruction fields shown in Table 1, it analyzes and obtains the full-barrier instruction (the binary code of the full-barrier instruction is 32'b0000_0011_0011_0000_0000_0000_0000_1111). Then, it analyzes the order of instructions before and after the full-barrier instruction. The purpose of this barrier instruction is to prevent the reordering of Load / Store instructions. The Load instruction is a read operation, which loads data from the cache into the RISC-V Core (i.e., the processor core). The Store instruction is a write-back operation, which removes data from the RISC-V Core. The core writes back to the cache. This submodule detects the addresses of Load / Store instructions before and after the full barrier instruction, which can be divided into two behavior patterns, i.e., two scenarios. Scenario 1 is multiple cores performing Load / Store operations on the same address; Scenario 2 is a producer-consumer pattern, where data is written first, and then a flag is set. For Scenario 1: First, it checks the behavior pattern of multiple RISC-V cores performing Load / Store operations on the same address before and after the full barrier instruction; for example, Core0 writes to load address A, then stores at address A, and Core1 loads at address A, then stores at address A. In this case, it is necessary to ensure that the Load and Store operations of Core0 are completed before the Load and Store operations of Core1 are performed, and the full barrier instruction can remain unchanged. However, if multiple cores only perform Load operations on the same address without Store operations, i.e., Core0 loads at address B, Core1 loads at address B, then the full barrier instruction needs to be converted into a read barrier instruction fence,r,r, i.e., the binary instruction code of the full barrier instruction is replaced with the binary instruction code of the read barrier instruction. If multiple cores only perform Store operations on the same address without Load operations, i.e., Core0 stores at address C, Core1 ... If the Store address is C, the full barrier instruction needs to be converted to a write barrier instruction `fence,w,w`, that is, the binary code of the full barrier instruction needs to be replaced with the binary code of the write barrier instruction. If multiple cores have write-before-read operations on the same address, i.e., Core0 Store address D, Core1 Load address D, the full barrier instruction needs to be converted to a write-after-read barrier instruction `fence,w,r`, that is, the binary code of the write-after-read barrier instruction needs to be replaced with the binary code of the full barrier instruction. The above conversion process will generate an interrupt message to inform the user, so that the user can further correct the code in subsequent programming and reduce the probability of coding errors. Accordingly, for scenario 2, the concepts of producer: write data first, then write flag bit; consumer: read flag bit first, then read data; a typical scenario is as follows:
[0082] # Producer (Core 0);
[0083] sw a1, (data) # 1. Write data;
[0084] sw a2, (flag) # 2. Set the flag (publish);
[0085] fence rw,rw;
[0086] # Consumer (Core 1);
[0087] lw a3, (flag) # 1. Read the flag bit;
[0088] beqz a3, 1b # Wait for the flag to be set;
[0089] lw a4, (data) # 2. Read data.
[0090] The full-barrier pruning submodule checks if there are different cores before and after the fence rw,rw instructions, and checks the sequential write and read operations on the two addresses. Specifically, it checks if the order of Core0 writing to address A and address B, and Core1 reading from address B and address A, is satisfied. If this relationship is satisfied, it's determined to be a producer-consumer pattern, and the full-barrier instruction is not pruned or converted. If the write and read relationship is not satisfied (e.g., Core0 writes to address A and address B, while Core1 reads from address B and address C), it's determined to be a non-production-line consumer pattern. Then, depending on whether there are reads / writes to the same address, it's converted to a read barrier instruction or a write barrier instruction. In the example above, it will be converted to a write-after-read barrier instruction, meaning the binary instruction code of the full-barrier instruction is replaced with the binary instruction code of the write-after-read barrier instruction.
[0091] The write barrier pruning submodule first reads the instructions to be executed by the RISC-V Core from the cache. Based on the instruction fields shown in Table 1, it analyzes the write barrier instructions to obtain the write barrier instructions (the binary code of the write barrier instruction is 32'b0000_0010_0010_0000_0000_0000_0000_1111). Then, it analyzes the order of instructions before and after the write barrier. The purpose of this barrier instruction is to prevent the reordering of Store→Store instructions. Store instructions are write-back instructions, which write data from the RISC-V Core back to the cache. This includes two scenarios: Scenario 1 is a single-core instruction with strict write order requirements (such as strong requirements for register configuration order); Scenario 2 is a multi-core scenario where multiple cores write data to the same address.
[0092] For scenario 1, a possible implementation is as follows: # Configure the DMA (Direct Memory Access) engine;
[0093] sw a0, (DMA_SRC_ADDR) # Set the source address;
[0094] sw a1, (DMA_DST_ADDR) # Set the target address;
[0095] fence w,w # Ensure address configuration is complete;
[0096] sw a2, (DMA_START) # Start DMA.
[0097] The write barrier deletion submodule requires the user to issue all registers with strong configuration order requirements and performs synchronous detection. If the register in the current sw instruction (i.e., write register operation) is a register with strong configuration order requirements issued by the user, the fence w,w instruction remains unchanged. Otherwise, scenario 2 is detected. For scenario 2, the behavior pattern of multiple RISC-V cores performing store operations on the same address before and after the write barrier instruction is checked. If multiple cores perform store operations on the same address, such as Core0 storing address A and Core1 storing address A, the fence w,w instruction remains unchanged. If neither scenario 1 nor scenario 2 is satisfied before and after the fence w,w instruction, fence w,w is deleted. That is, the binary 32'b0000_0010_0010_0000_0000_0000_1111 of the write barrier instruction is deleted from the instruction, and an interrupt message is generated to inform the user so that the user can further correct the error in subsequent programming and reduce the probability of coding errors.
[0098] The read barrier pruning submodule first reads the instructions that are about to be executed by the RISC-V Core from the cache. Based on the instruction fields shown in Table 1 above, it analyzes and obtains the write-after-read barrier instruction (the binary code of the write-after-read barrier instruction is 32'b0000_0001_0001_0000_0000_0000_0000_1111). Then, it analyzes the sequential correlation of the instructions before and after the write-after-read barrier. The purpose of this barrier instruction is to prevent the reordering of Load→Load instructions. The Load instruction is a read-back instruction, which reads data from the cache back to the RISC-V Core. A possible implementation is as follows: lw t0, (a0) # Read data;
[0099] fence r, r # Ensures that the next read operation is not reordered before the previous read;
[0100] lw t1, (a1) # Read the flag bit.
[0101] This read barrier deletion submodule requires the user to provide all registers that require a strong read order. If the register in the current lw instruction (i.e., the register load operation) is a register that requires a strong read order, the fence r,r instruction remains unchanged; otherwise, fence r,r is deleted, which means the binary representation of the read barrier instruction, 32'b0000_0001_0001_0000_0000_0000_0000_1111, is deleted. An interrupt message is generated to inform the user so that they can make further corrections in subsequent programming and reduce the probability of coding errors.
[0102] The write-after-read barrier pruning submodule first reads the instructions that are about to be executed by the RISC-V Core from the cache. Based on the instruction fields shown in Table 1, it analyzes and obtains the read barrier instruction (the binary code of the read barrier instruction is 32'b0000_0010_0001_0000_0000_0000_0000_1111). Then, it analyzes the sequential relationship between the instructions before and after the write-after-read barrier. The purpose of this barrier instruction is to prevent the reordering of the Store→Load instructions. The Load instruction is a load instruction, which loads data from the cache into the RISC-V Core, and the Store instruction is a write-back instruction, which writes data from the RISC-V Core back to the cache. A possible implementation is as follows: sw x1, (x0) # Write x1;
[0103] fence w, r # Ensure that the write is correct and subsequent reads are visible;
[0104] lw x2, (x1) # Read x1.
[0105] The function of this write-after-read barrier deletion submodule is to monitor whether the destination register of the Store instruction before the fence w,r instruction is the source register of the Load instruction after fence w,r. If so, fence w,r is kept unchanged. Otherwise, fence w,r is deleted. Specifically, the binary representation of the read barrier instruction, 32'b0000_0010_0001_0000_0000_0000_0000_1111, is deleted, and an interrupt message is generated to inform the user, allowing the user to further correct the code in subsequent programming and reduce the probability of coding errors.
[0106] On the other hand, such as Figure 4The diagram shows the structure of the barrier instruction necessity addition module, which contains five sub-modules: full barrier addition sub-module, write barrier addition sub-module, read barrier addition sub-module, post-write read barrier addition sub-module, and barrier addition trigger sub-module. The function of this module is to check the necessity of barrier instructions to prevent users from failing to add barrier instructions where they should, which could lead to malfunctions in the multi-core RISC-V CPU and consequently, a decrease in security and stability. The barrier addition trigger sub-module monitors the trigger conditions of the full barrier addition sub-module, write barrier addition sub-module, and read-after-write barrier addition sub-module. Only when the corresponding trigger conditions are met will the corresponding sub-module function be triggered; otherwise, the corresponding function will not be activated, thereby reducing RISC-V CPU power consumption. Table 2 below shows the corresponding trigger conditions for the barrier instruction addition sub-module.
[0107] Table 2. Table of Trigger Conditions for Adding Submodules to Barrier Commands
[0108]
[0109] Specifically, the full-barrier addition submodule function, when triggered by the barrier addition trigger submodule, enables the corresponding function and adds the binary full-barrier instruction (32'b0000_0011_0011_0000_0000_0000_0000_1111) to the corresponding position in the instruction. When this submodule is not triggered, it is in a low-power state to save RISC-V CPU power. The write-barrier addition submodule function, when triggered by the barrier addition trigger submodule, enables the corresponding function and adds the binary write-barrier instruction (32'b0000_0010_0010_0000_0000_0000_0000_1111) to the corresponding position in the instruction. When this submodule is not triggered, this function is disabled, and the submodule is in a low-power state to save RISC-V CPU power. The function of the read barrier adding submodule is to enable the corresponding function after being triggered by the barrier adding trigger submodule, and add the binary read barrier instruction (32'b0000_0001_0001_0000_0000_0000_0000_1111) to the corresponding position in the instruction. When the submodule is not triggered, the function is disabled, and the submodule remains in a low-power state to save power for the RISC-V CPU.
[0110] Therefore, this technical solution can add a barrier instruction processing module, specifically divided into a barrier instruction unnecessary removal module and a barrier instruction necessary addition module. This modular approach enables the monitoring, conversion, and deletion of barrier instructions. Based on the monitoring results, barrier instructions are downgraded or deleted, avoiding the drawbacks of traditional solutions where developers add memory barrier instructions where unnecessary or at unnecessary levels. This reduces the impact of barrier instructions on the performance of multi-core RISC-V CPUs, significantly improving their performance. Furthermore, a trigger condition table for the barrier instruction addition submodule is disclosed. Adding barrier instructions based on triggers avoids the problem of developers failing to add memory barrier instructions where necessary, improving the overall security and stability of the RISC-V CPU. Simultaneously, the corresponding submodule function is only enabled when the corresponding memory barrier addition function is detected, greatly reducing the power consumption of the RISC-V CPU.
[0111] like Figure 5 As shown, this embodiment discloses a data read / write method based on memory barrier instructions, applied to a multi-core instruction set processor, including:
[0112] Instruction determination module 11 is used to determine the initial memory barrier instruction in the currently running user program code; the initial memory barrier instruction is a barrier instruction added by the user.
[0113] The instruction checking module 12 is used to check the initial memory barrier instruction using preset barrier instruction checking conditions and obtain the corresponding check results; the preset barrier instruction checking conditions are conditions constructed based on the execution order of multi-core instructions to control the read operation and obtain the latest value of the data.
[0114] The data read / write module 13 is used to adjust the initial memory barrier instruction according to the inspection results, and to perform subsequent data read / write operations based on the adjusted target barrier instruction.
[0115] Therefore, this application combines the conditions pre-constructed based on the execution order of multi-core instructions to control read operations and obtain the latest data value to check the initial memory barrier instructions in the user program code. This avoids the drawbacks of traditional solutions where developers add memory barrier instructions where they are unnecessary or add memory barrier instructions of unnecessary levels, thus reducing the impact of barrier instructions on the performance of multi-core instruction set processors. At the same time, by adjusting the barrier instructions based on the check results before executing read and write operations, the accuracy of the memory barrier function can be guaranteed, improving the performance of multi-core instruction set processors, as well as overall security and stability.
[0116] Furthermore, embodiments of this application also disclose an electronic device, Figure 6 This is a structural diagram of an electronic device according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application. Specifically, the electronic device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the data read / write method based on memory barrier instructions disclosed in any of the foregoing embodiments. Furthermore, the electronic device in this embodiment may specifically be an electronic computer.
[0117] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.
[0118] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.
[0119] The operating system 221 is used to manage and control the various hardware devices on the electronic device and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the data read / write method based on memory barrier instructions executed by the electronic device as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.
[0120] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned data read / write method based on memory barrier instructions. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.
[0121] Furthermore, this application also discloses a computer program product, including a computer program / instruction, which, when executed by a processor, implements the aforementioned data read / write method based on memory barrier instructions.
[0122] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0123] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0124] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0125] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0126] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A data read / write method based on memory barrier instructions, characterized in that, Applied to multi-core instruction set processors, including: Identify the initial memory barrier instruction in the currently running user program code; the initial memory barrier instruction is a barrier instruction added by the user. The initial memory barrier instruction is checked using preset barrier instruction check conditions to obtain the corresponding check results; the preset barrier instruction check conditions are instruction deletion conditions and instruction addition conditions constructed based on the execution order of multi-core instructions. The initial memory barrier instruction is adjusted based on the inspection results, and subsequent data read and write operations are performed based on the adjusted target barrier instruction.
2. The data read / write method based on memory barrier instructions according to claim 1, characterized in that, The step of determining the initial memory barrier instruction in the currently running user program code includes: Read a binary program file from memory; Run the user program code in the program file and identify the initial memory barrier instruction in the user program code.
3. The data read / write method based on memory barrier instructions according to claim 1 or 2, characterized in that, The initial memory barrier instruction is checked using preset barrier instruction check conditions to obtain corresponding check results, including: The initial memory barrier instruction is checked based on the condition of unnecessary deletion of barrier instructions, and the corresponding first check result is obtained. The initial memory barrier instruction is checked based on the necessity of the barrier instruction, and the corresponding second check result is obtained. Accordingly, adjusting the initial memory barrier instruction based on the inspection results includes: The initial memory barrier instruction is adjusted based on the first check result and the second check result; the adjustment operation is a conversion operation, a deletion operation, or an addition operation.
4. The data read / write method based on memory barrier instructions according to claim 3, characterized in that, If the initial memory barrier instruction is a full barrier instruction, then the initial memory barrier instruction is checked based on the barrier instruction non-essential pruning condition to obtain the corresponding first check result, including: Examine the behavior pattern of multiple cores performing read and write operations on the same address before and after the full-barrier instruction; If the behavior pattern indicates that each core of the multi-core system performs only read or write operations on the same address, then a first check result is generated indicating that the full barrier instruction is converted into a read barrier instruction or a write barrier instruction; wherein, the read barrier instruction corresponds to a read operation, and the write barrier instruction corresponds to a write operation; If the behavior pattern indicates that each core of the multi-core performs a write-then-read operation on the same address, then a first check result is generated indicating that the full barrier instruction is converted into a write-after-read barrier instruction.
5. The data read / write method based on memory barrier instructions according to claim 3, characterized in that, If the initial memory barrier instruction is a write barrier instruction, then the initial memory barrier instruction is checked based on the barrier instruction non-essential pruning condition to obtain the corresponding first check result, including: If the register for the write operation corresponding to the write barrier instruction is a register with a configured order issued by the user, then the behavior mode of the write barrier instruction is determined. If the behavior pattern does not indicate that multiple cores perform write operations on the same address before and after the write barrier instruction, a first check result indicating that the write barrier instruction has been deleted is generated.
6. The data read / write method based on memory barrier instructions according to claim 3, characterized in that, If the initial memory barrier instruction is a read barrier instruction, then the initial memory barrier instruction is checked based on the barrier instruction non-essential pruning condition to obtain the corresponding first check result, including: If the register for the read operation corresponding to the read barrier instruction is not a register in the configured order issued by the user, a first check result representing the deletion of the read barrier instruction is generated.
7. The data read / write method based on memory barrier instructions according to claim 3, characterized in that, If the initial memory barrier instruction is a write-after-read barrier instruction, then the initial memory barrier instruction is checked based on the barrier instruction non-essential pruning condition to obtain the corresponding first check result, including: If the destination register of the previous write operation corresponding to the write-after-read barrier instruction is not the source register of the next read operation, a first check result representing the deletion of the write-after-read barrier instruction is generated.
8. The data read / write method based on memory barrier instructions according to claim 3, characterized in that, The condition for adding a barrier instruction based on its necessity is used to check the initial memory barrier instruction, resulting in a corresponding second check result, including: If the initial memory barrier instruction does not include a full barrier instruction, and the user program code represents each core performing a read or write operation on the same address, then a second check result representing the addition of a full barrier instruction is generated.
9. The data read / write method based on memory barrier instructions according to claim 3, characterized in that, The condition for adding a barrier instruction based on its necessity is used to check the initial memory barrier instruction, resulting in a corresponding second check result, including: If the initial memory barrier instruction does not include a full barrier instruction, and the user program code represents the sequential read and write operations performed by each core on different addresses, then a second check result representing the addition of a full barrier instruction is generated.
10. The data read / write method based on memory barrier instructions according to claim 3, characterized in that, The condition for adding a barrier instruction based on its necessity is used to check the initial memory barrier instruction, resulting in a corresponding second check result, including: If the initial memory barrier instruction does not include a write barrier instruction, and the scenario corresponding to the user program code contains a user-issued register with a configured order, then a second check result representing the addition of a write barrier instruction is generated.
11. The data read / write method based on memory barrier instructions according to claim 3, characterized in that, The condition for adding a barrier instruction based on its necessity is used to check the initial memory barrier instruction, resulting in a corresponding second check result, including: If the initial memory barrier instruction does not include a write barrier instruction, and the user program code represents that each core performs write operations to the same address sequentially, then a second check result representing the addition of a write barrier instruction is generated.
12. The data read / write method based on memory barrier instructions according to claim 3, characterized in that, The condition for adding a barrier instruction based on its necessity is used to check the initial memory barrier instruction, resulting in a corresponding second check result, including: If the initial memory barrier instruction does not include a read barrier instruction, and the scenario corresponding to the user program code contains a user-issued register with a configured order, then a second check result representing the addition of a read barrier instruction is generated.
13. The data read / write method based on memory barrier instructions according to claim 3, characterized in that, The condition for adding a barrier instruction based on its necessity is used to check the initial memory barrier instruction, resulting in a corresponding second check result, including: If the initial memory barrier instruction does not include a read-after-write barrier instruction, and there is a scenario in the user program code where the destination register of the previous write operation is the source register of the next read operation, then a second check result representing the addition of a read-after-write barrier instruction is generated.
14. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the data read / write method based on memory barrier instructions as described in any one of claims 1 to 13.
15. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, it implements the steps of the data read / write method based on memory barrier instructions as described in any one of claims 1 to 13.