Edge device computing task partitioning method, apparatus, and non-transitory storage medium

Abstract

This application discloses a method, apparatus, and non-volatile storage medium for partitioning computing tasks on edge devices, relating to the field of electronic digital data processing. The method includes: decomposing a target matrix into multiple target blocks based on the local memory size of the graphics processor in the edge device, wherein the target matrix includes a complex conjugate symmetric matrix; decomposing the target blocks into diagonal blocks and off-diagonal blocks based on their diagonals, wherein diagonal blocks are blocks located on the target diagonal of the target matrix, and off-diagonal blocks are blocks not located on the target diagonal; multiplying the diagonal blocks and off-diagonal blocks with vector blocks using thread groups respectively; and accumulating the multiplication results to obtain the final calculation result. This application solves the technical problem of low efficiency in edge computing devices performing matrix-vector multiplication calculations on specific types of matrices due to the incompatibility between matrix-vector multiplication optimization methods in related technologies and edge computing devices.

Description

Technical Field

[0001] This application relates to the field of electronic digital data processing, and more specifically, to a method, apparatus, and non-volatile storage medium for dividing computing tasks on edge devices. Background Technology

[0002] Most optimization libraries for matrix-vector multiplication in related technologies are designed for central processing units (CPUs) or graphics processing units (GPUs) with specific architectures such as CUDA. Although there are some optimization methods for matrix-vector multiplication in OpenCL, these methods are not suitable for edge computing devices, especially when performing matrix-vector multiplication of complex conjugate symmetric matrices such as Hermitian matrices, where computational efficiency is low.

[0003] There is currently no effective solution to the above problems. Summary of the Invention

[0004] This application provides a method, apparatus, and non-volatile storage medium for partitioning computing tasks on edge devices, in order to at least solve the technical problem that edge computing devices are inefficient when performing matrix-vector multiplication calculations on specific types of matrices due to the incompatibility between matrix-vector multiplication optimization methods in related technologies and edge computing devices.

[0005] According to one aspect of the embodiments of this application, a method for partitioning computing tasks on an edge device is provided, comprising: decomposing a target matrix into multiple target blocks based on the local memory size of the graphics processor in the edge device, wherein the target matrix includes a complex conjugate symmetric matrix; decomposing the target blocks into diagonal blocks and off-diagonal blocks based on the diagonal of the target blocks, wherein the diagonal blocks are blocks on the target diagonal of the target block, and the off-diagonal blocks are blocks not on the target diagonal; multiplying the diagonal blocks and off-diagonal blocks with vector blocks by thread groups respectively; accumulating the multiplication results to obtain a final calculation result, and writing the final calculation result into global memory according to the thread arrangement when reading the vector blocks.

[0006] Optionally, the multiplication result includes a first multiplication result corresponding to the diagonal block and a second multiplication result corresponding to the off-diagonal block; retrieving the diagonal block and off-diagonal block and multiplying them with the vector block by the thread group includes: loading the vector block from global memory into local memory; determining the first type of elements corresponding to each diagonal block and the second type of elements corresponding to each off-diagonal block in the vector block; performing a multiplication operation on the diagonal block and the first type of elements to obtain the first multiplication result, and performing a multiplication operation on the off-diagonal block and the second type of elements to obtain the second multiplication result.

[0007] Optionally, the diagonal blocks include a first diagonal block and a second diagonal block, and the off-diagonal blocks include a first off-diagonal block and a second off-diagonal block, wherein the first diagonal block and the second diagonal block are both conjugate symmetric matrices, and the elements in the first off-diagonal block and the elements in the second off-diagonal block are conjugate symmetric.

[0008] Optionally, the second type of elements includes elements located in the first preset position range and the second preset position range within the vector block; multiplying the off-diagonal block and the second type of elements to obtain the second multiplication result includes: multiplying the first off-diagonal block and the elements in the first preset position range, and transposing the second off-diagonal block by changing the index of the off-diagonal block, and multiplying the transposed second off-diagonal block and the elements in the second preset position range.

[0009] Optionally, decomposing the target matrix into multiple target blocks based on the local memory size of the graphics processor in the edge device includes: copying the target matrix from the host memory of the edge device into the global memory; determining the preset size of the target blocks based on the size of the local memory, and decomposing the target matrix according to the preset size to obtain multiple target blocks with the preset size.

[0010] Optionally, the edge device includes multiple thread groups, and each thread group corresponds to a target block. The thread groups run on the computing cluster of the edge device and are scheduled by the graphics processor in the edge device.

[0011] Optionally, the edge device computing task partitioning method also includes: allocating a corresponding temporary storage space for each thread group in global memory, and storing the multiplication result in the temporary storage space.

[0012] According to another aspect of the embodiments of this application, an edge device computing task partitioning apparatus is also provided, comprising: a first processing module, configured to decompose a target matrix into multiple target blocks based on the local memory size of the graphics processor in the edge device, wherein the target matrix includes a complex conjugate symmetric matrix; a second processing module, configured to decompose the target blocks into diagonal blocks and off-diagonal blocks based on the diagonal of the target blocks, wherein the diagonal blocks are blocks on the target diagonal of the target blocks, and the off-diagonal blocks are blocks not on the target diagonal; a third processing module, configured to retrieve the diagonal blocks and off-diagonal blocks respectively through thread groups and multiply them with vector blocks; and a fourth processing module, configured to accumulate the multiplication results to obtain a final calculation result, and write the final calculation result into global memory according to the thread arrangement when reading the vector blocks.

[0013] According to another aspect of the embodiments of this application, a non-volatile storage medium is also provided, wherein a program is stored in the non-volatile storage medium, and the program controls the device where the non-volatile storage medium is located to execute an edge device computing task partitioning method when it runs.

[0014] According to another aspect of the embodiments of this application, an electronic device is also provided, including: a memory and a processor, the processor being configured to run a program stored in the memory, wherein the program executes an edge device computing task partitioning method during runtime.

[0015] According to another aspect of the embodiments of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements a method for partitioning computing tasks on an edge device.

[0016] In this embodiment, the target matrix is ​​decomposed into multiple target blocks based on the local memory size of the graphics processor in the edge device. The target matrix includes a complex conjugate symmetric matrix. The target blocks are further decomposed into diagonal blocks and off-diagonal blocks based on their diagonals. Diagonal blocks are those located on the target diagonal, and off-diagonal blocks are those not located on the target diagonal. Threads retrieve the diagonal and off-diagonal blocks and multiply them with the vector blocks. The multiplication results are accumulated to obtain the final calculation result, which is then written into global memory according to the thread arrangement used when reading the vector blocks. This method utilizes the matrix type characteristics of the target matrix and the local memory size of the graphics processor in the edge device. The local memory size of the shape processor decomposes the target matrix and stores it in local memory. The edge device then retrieves the diagonal and off-diagonal blocks obtained from the decomposition through a thread group and performs matrix-vector multiplication calculations. This achieves the goal of optimizing the matrix-vector multiplication calculation method executed by the edge computing device based on the matrix type characteristics and the hardware information of the edge computing device. This improves the global memory access efficiency and computational efficiency of the edge computing device when performing matrix-vector multiplication calculations on complex conjugate symmetric matrices. Furthermore, it solves the technical problem of low efficiency of the edge computing device when performing matrix-vector multiplication calculations on specific types of matrices due to the incompatibility between the matrix-vector multiplication optimization methods in related technologies and the edge computing device. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 This is a schematic diagram of the structure of an edge device according to an embodiment of this application;

[0019] Figure 2 This is a flowchart illustrating a method for partitioning computing tasks on an edge device according to an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of a target block decomposition method provided according to an embodiment of this application;

[0021] Figure 4 This is a flowchart illustrating a complex conjugate symmetric matrix-vector multiplication calculation process according to an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of a transpose structure for edge device computing task partitioning provided in an embodiment of this application. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] To better understand the embodiments of this application, the technical terms involved in the embodiments of this application are explained below:

[0026] Complex conjugate symmetric matrices: A complex conjugate symmetric matrix (Hermitian matrix) is a special type of complex matrix whose conjugate transpose is equal to itself. These matrices have wide applications in many practical fields, such as Fourier transforms and electromagnetic field calculations.

[0027] Edge devices, also known as edge computing devices, refer to devices that perform computing and data processing at the network edge. These devices shift computing power from centralized data centers or the cloud to locations closer to the data generation source, reducing data transmission latency, improving response speed, and saving network bandwidth. In recent years, the computing power of edge computing devices has significantly improved. Modern edge computing devices are generally equipped with high-performance multi-core processors. With the development of Graphics Processing Unit (GPU) technology, utilizing GPUs for efficient parallel computing has become a trend, and many edge computing devices are equipped with high-performance GPUs or Network Processing Units (NPUs). GPUs have massively parallel processing capabilities, demonstrating significant performance advantages in numerical calculations such as matrix computations. By equipping edge computing devices with high-performance processors and GPUs, their computing power is greatly enhanced, enabling them to handle complex computational and data analysis tasks more efficiently.

[0028] The OpenCL programming model: The Open Computing Language (OpenCL) provides an abstract description of hardware, including the host and multiple connected computing devices. Computing devices run OpenCL kernel programs and are typically divided into Compute Units and a memory system. Each Compute Unit contains multiple Compute Clusters, and each Compute Cluster contains multiple Compute Cores. The memory system includes the host and device memory. Device memory mainly includes: Global Memory, Constant Memory, Local Memory, and Private Memory. Global Memory stores data read from host memory, Constant Memory stores data that remains unchanged during kernel program execution, Local Memory stores data shared within the Compute Cluster, and Private Memory stores data private to the Compute Cores. The speed of each memory type, from highest to lowest, is: Private Memory, Local Memory, Constant Memory, and Global Memory.

[0029] Matrix-vector multiplication is a fundamental and widely used computational operation in scientific computing and engineering applications. It plays a particularly important role in fields such as signal processing, image processing, and numerical analysis. Among related technologies, the following optimized libraries for matrix-vector multiplication are available:

[0030] CPU-optimized libraries: On edge device CPU hardware, commonly used matrix-vector multiplication algorithms include the GEMV (General Matrix Vector Multiplication) function from the BLAS (Basic Linear Algebra Subprograms) library. This algorithm performs element-wise multiplication and addition operations on matrices and vectors through nested loops. Commonly used BLAS libraries on CPUs include OpenBLAS (for ARM architecture), MKL (for x86 architecture), and ATLAS (Automatic Architecture Tuning). These BLAS libraries are widely used on CPU architectures in scientific computing, engineering simulation, and machine learning, providing efficient matrix and vector operations.

[0031] Optimization Libraries for CUDA: Compute Unified Device Architecture (CUDA) is a programming model introduced by NVIDIA for NVIDIA GPU hardware platforms. Many researchers utilize CUDA to optimize matrix multiplication by partitioning matrices, using shared memory and registers to optimize data access, and reducing global memory access latency. NVIDIA provides the cuBLAS library for efficient matrix-vector multiplication. cuBLAS provides dedicated Hermitian matrix-vector multiplication functions for single-precision and double-precision complex number calculations.

[0032] Optimized libraries for OpenCL: Open Computing Language (OpenCL) is a programming framework for writing programs that perform parallel computations on heterogeneous platforms. OpenCL's clBLAST is an optimized linear algebra library that supports Hermitian matrix-vector multiplication. By determining the access position of data elements, it reduces access to symmetric elements (which account for half of all matrix accesses), significantly improving computational efficiency.

[0033] It can be seen that current technologies offer various methods for optimizing matrix-vector multiplication. However, these methods still have the following problems in specific application scenarios, such as processing Hermitian matrices using edge devices:

[0034] On the CPU hardware side, although BLAS libraries (such as OpenBLAS, MKL, and ATLAS) provide optimized functions for Hermitian matrices, their computational efficiency remains a bottleneck when processing large-scale Hermitian matrices due to the limited parallel computing capabilities of the CPU. Even highly optimized libraries struggle to fully utilize the CPU's multi-core and SIMD capabilities, resulting in computational speeds that cannot meet the demands of high-performance computing.

[0035] While cuBLAS can significantly improve computational efficiency on NVIDIA GPU hardware by leveraging the GPU's parallel computing capabilities, its closed-source nature and applicability only to CUDA-compatible hardware limit its application and optimization on other edge hardware platforms.

[0036] The OpenCL programming model provides cross-platform support for parallel computing. While clBLAST, based on OpenCL, can run on various edge devices, its optimization for Hermitian matrices remains insufficient. For the special structure of Hermitian matrices, existing implementations do not fully utilize their conjugate symmetry, resulting in redundant operations during computation. clBLAST also does not fully utilize the merged memory access capabilities of GPU hardware; accessing symmetric elements via indexes leads to discontinuous global memory access, thus failing to fully utilize bandwidth.

[0037] To address the aforementioned issues, this application provides relevant solutions, which are detailed below.

[0038] According to an embodiment of this application, a method embodiment for edge device computing task partitioning is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0039] The methods and embodiments provided in this application can be executed on mobile terminals, computer terminals, or similar computing devices. Figure 1 A hardware block diagram of an edge device for implementing an edge device computing task partitioning method is shown. For example... Figure 1 As shown, the edge device 10 may include one or more (shown as 102a, 102b, ..., 102n in the figure) processors 102 (processors 102 may include, but are not limited to, microprocessors such as MCUs or programmable logic devices such as FPGAs), a memory 104 for storing data, and a transmission device 106 for communication functions. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of a BUS bus), a network interface, a power supply, and / or a camera. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the aforementioned electronic device. For example, the edge device 10 may also include components that are more advanced than those described above. Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0040] It should be noted that the aforementioned one or more processors 102 and / or other data processing circuitry are generally referred to herein as "data processing circuitry". This data processing circuitry may be embodied, in whole or in part, in software, hardware, firmware, or any other combination thereof. Furthermore, the data processing circuitry may be a single, independent processing module, or may be integrated, in whole or in part, into any other element within the edge device 10. As involved in the embodiments of this application, this data processing circuitry serves as a processor control mechanism (e.g., selection of a variable resistor termination path connected to an interface).

[0041] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the edge device computing task partitioning method in this embodiment. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, thereby realizing the edge device computing task partitioning method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the edge device 10 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0042] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the communication provider of the edge device 10. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0043] The display can be, for example, a touchscreen liquid crystal display (LCD) that allows the user to interact with the user interface of the edge device 10 (or mobile device).

[0044] It should also be noted that the aforementioned one or more processors 102 include a central processing unit (CPU) and a graphics processing unit (GPU).

[0045] Under the aforementioned operating environment, this application provides a method for partitioning computing tasks on edge devices, applicable to edge devices, such as... Figure 2 As shown, the method includes the following steps:

[0046] Step S202: Based on the local memory size of the graphics processor in the edge device, the target matrix is ​​decomposed into multiple target blocks, wherein the target matrix includes a complex conjugate symmetric matrix;

[0047] In the technical solution provided in step S202, the step of decomposing the target matrix into multiple target blocks according to the local memory size of the graphics processor in the edge device includes: copying the target matrix from the host memory of the edge device into the global memory; determining the preset size of the target blocks according to the size of the local memory, and decomposing the target matrix according to the preset size to obtain multiple target blocks with the preset size.

[0048] Specifically, in actual storage, due to its symmetry, a Hermitian matrix typically only stores half of its elements; assuming that only the lower triangular portion is stored in the host memory, the Hermitian matrix is ​​first copied from host memory to global memory in the device memory. Then, the Hermitian matrix is ​​divided into several... The target block size. The size of the target block is determined by the local memory size of the GPU on the edge device. The target block size must be less than the maximum usable local memory size divided by 3, and must be a multiple of 2. Let the target block size be... The number of bytes for each element in the target block is The maximum local memory size is ,but Each thread group is responsible for calculating one target block. The thread groups run on a computing cluster and are scheduled by the GPU.

[0049] In some embodiments of this application, the target matrix may be a complex conjugate symmetric matrix established based on the actual simulation scenario and related simulation data, such as a simulation matrix established based on multi-specification package data, or a simulation matrix based on data from multiple robotic arms simulating a robotic arm in a collaborative gripping and flipping scenario.

[0050] Step S204: Decompose the target block into diagonal blocks and off-diagonal blocks according to the diagonal of the target block. The diagonal blocks are the blocks on the target diagonal of the target block, and the off-diagonal blocks are the blocks that are not on the target diagonal.

[0051] In the technical solution provided in step S204, within each thread group, it can be done according to the following... Figure 3 The method shown further decomposes the target block into diagonal blocks and off-diagonal blocks. Diagonal blocks refer to those located on the diagonal of the target block and having a size of [missing information]. A block; a non-diagonal block refers to a block that is not on the diagonal of the target and has a size of [missing information]. There are two blocks, two diagonal blocks and two off-diagonal blocks. The target diagonal can be the diagonal line from the top-left vertex to the bottom-right vertex. The blocks on the target diagonal belong to a conjugate symmetric matrix. The diagonal blocks load the lower triangular elements from global memory into local memory and copy the elements to the upper triangular element. The elements in the two off-diagonal blocks are conjugate symmetric. The off-diagonal blocks will copy the elements from global memory... The lower triangular element of the block is loaded into local memory. At this point, the local memory contains two off-diagonal blocks and one off-diagonal block, with a size of [size missing]. The threads within the thread group are arranged row-wise. Threads 0, 1, 2, 3... sequentially read elements at positions 0, 1, 2, 3... in the row direction of the block. The number of elements in the thread block is... ,in The maximum number of threads that can be set per thread group is determined by the GPU's limitations; let the maximum number of threads be [value missing]. ,but satisfy .exist Figure 3 In the decomposition example shown, such as Figure 3 As shown on the right, there are 8 threads in the y-direction (vertical direction) and 32 threads in the x-direction (horizontal direction). Figure 3 The arrow on the right indicates the direction of thread block processing.

[0052] It should be noted that edge devices typically have limited storage resources (smaller memory and cache), necessitating optimized memory usage and reduced unnecessary data consumption during operator design. Existing methods fail to fully utilize the conjugate symmetry of Hermitian matrices, leading to redundant operations during computation. This application's embodiment fully leverages the symmetry of Hermitian matrices, decomposing the matrix into multiple target blocks, and further decomposing them into diagonal and off-diagonal blocks. This reduces unnecessary computation and memory consumption, fully utilizes the memory merging feature of global memory, and further improves memory access and computation efficiency.

[0053] In some embodiments of this application, the diagonal block includes a first diagonal block and a second diagonal block, and the off-diagonal block includes a first off-diagonal block and a second off-diagonal block, wherein the first diagonal block and the second diagonal block are both conjugate symmetric matrices, and the elements in the first off-diagonal block and the elements in the second off-diagonal block are conjugate symmetric.

[0054] Step S206: The diagonal block and off-diagonal block are retrieved and multiplied with the vector block by the thread group respectively;

[0055] In the technical solution provided in step S206, the edge device includes multiple thread groups, and each thread group corresponds to a target block. The thread groups run on the computing cluster of the edge device and are scheduled by the graphics processor in the edge device.

[0056] Specifically, edge devices typically have fewer CPU cores (usually 4-8) compared to servers, resulting in limited parallel computing capabilities when processing large-scale Hermitian matrices. Furthermore, edge device CPUs typically employ low-power, high-efficiency architectures, focusing more on general-purpose tasks rather than large-scale parallel computing. To address the limited parallel computing capabilities of edge device CPUs when processing large-scale Hermitian matrices, this application proposes a GPU-based matrix-vector multiplication optimization method that fully utilizes the massively parallel computing capabilities of GPUs, significantly improving computational efficiency.

[0057] As an optional implementation, the multiplication result includes a first multiplication result corresponding to the diagonal block and a second multiplication result corresponding to the off-diagonal block. The step of retrieving the diagonal block and off-diagonal block and multiplying them with the vector block by the thread group includes: loading the vector block from global memory into local memory; determining the first type of elements corresponding to each diagonal block and the second type of elements corresponding to the off-diagonal block in the vector block; performing a multiplication operation on the diagonal block and the first type of elements to obtain the first multiplication result, and performing a multiplication operation on the off-diagonal block and the second type of elements to obtain the second multiplication result.

[0058] As an optional implementation, the second type of elements includes elements located in a first preset position range and elements in a second preset position range within the vector block; the step of multiplying the off-diagonal block and the second type of elements to obtain a second multiplication result includes: multiplying the first off-diagonal block and the elements in the first preset position range, transposing the second off-diagonal block by changing the index of the off-diagonal block, and multiplying the transposed second off-diagonal block and the elements in the second preset position range.

[0059] Specifically, during computation, the thread group loads the corresponding vector blocks from global memory into local memory. In the previous step, the thread group decomposed the cube into diagonal and off-diagonal blocks. Now, the corresponding diagonal and off-diagonal blocks are multiplied by the vector blocks loaded into local memory. Specifically, the first diagonal block is multiplied by the first... The elements, the second diagonal block multiplied by the vector block, are then... The elements, the off-diagonal block multiplied by the first element in the vector block. Elements, after transposing off-diagonal blocks, multiplied by the vector blocks. The elements (the transpose here does not need to be transposed in local memory; the corresponding elements are accessed by changing the index), and n is the total number of elements in the vector block.

[0060] Step S208: The multiplication results are accumulated to obtain the final calculation result, and the final calculation result is written into the global memory according to the thread arrangement when reading the vector blocks.

[0061] In some embodiments of this application, a corresponding temporary storage space can be allocated for each thread group in global memory, and the multiplication result can be stored in the temporary storage space.

[0062] Specifically, a temporary buffer of size can be allocated in global memory for each thread group. The result of the previous calculation is written to a temporary buffer. After the thread group executes, a synchronization operation is performed to accumulate the data in the temporary buffer to obtain the final result. The result is then written back to global memory according to the thread arrangement of reading vector blocks, completing the calculation.

[0063] The complete execution flow of the edge device computing task partitioning method provided in this application embodiment is as follows: Figure 4 As shown, where Figure 4 This describes the calculation process when n is 64. Figure 4 In this context, "partial result" refers to the result that needs to be written to the temporary buffer after computation, "WGSX" and "WGSY" represent the thread group size, and "sx_blk" represents the vector block size. Figure 4 The lower left corner shows the calculation process for target blocks such as A00, A10, and A20.

[0064] By utilizing the local memory size of the graphics processor in the edge device, the target matrix is ​​decomposed into multiple target blocks, where the target matrix includes a complex conjugate symmetric matrix. The target blocks are further decomposed into diagonal blocks and off-diagonal blocks based on their diagonals. Diagonal blocks are those located on the target diagonal, and off-diagonal blocks are those not located on the target diagonal. A thread group retrieves the diagonal and off-diagonal blocks and multiplies them with the vector blocks respectively. The multiplication results are accumulated to obtain the final calculation result, which is then written into global memory according to the thread arrangement used when reading the vector blocks. This method leverages the matrix type characteristics of the target matrix and the graphics processing unit in the edge device. The local memory size of the device decomposes the target matrix and stores it in local memory. The edge device then retrieves the diagonal and off-diagonal blocks obtained from the decomposition through a thread group and performs matrix-vector multiplication. This achieves the goal of optimizing the matrix-vector multiplication calculation method executed by the edge computing device based on the matrix type characteristics and the hardware information of the edge computing device. This improves the global memory access efficiency and computational efficiency of the edge computing device when performing matrix-vector multiplication calculations on complex conjugate symmetric matrices. Furthermore, it solves the technical problem of low efficiency of the edge computing device when performing matrix-vector multiplication calculations on specific types of matrices due to the incompatibility between the matrix-vector multiplication optimization methods in related technologies and the edge computing device.

[0065] Furthermore, the edge device computing task partitioning method provided in this application addresses the issue of the diverse types of edge devices by offering an adaptive matrix-vector multiplication calculation method that selects appropriate execution parameters based on the GPU specifications of the edge device. This fully utilizes the computing power and memory resources of the GPU hardware on the edge device. Moreover, this method is developed based on the OpenCL programming model, enabling the optimized implementation to be cross-platform and run efficiently on different edge devices.

[0066] To address the issue of limited storage resources and bandwidth on edge devices, the method provided in this application utilizes the conjugate symmetry of the Hermitian matrix to process elements of diagonal and off-diagonal blocks separately, reducing the overhead of reading data from global memory and improving overall computational performance. By utilizing the conjugate symmetry of diagonal blocks and the transpose conjugate of off-diagonal blocks, the copying overhead of local memory is reduced, effectively utilizing local memory and further improving efficiency.

[0067] The OpenCL-based clBLAST library suffers from discontinuous memory access and low bandwidth utilization when processing Hermitian matrices. The edge device computing task partitioning method provided in this application optimizes the memory access mode. Compared with the traditional implementation method, it avoids discontinuous global memory access, makes full use of the GPU's global memory merging access capability, reduces memory access latency, and improves memory bandwidth utilization.

[0068] This application provides an edge device computing task partitioning apparatus. Figure 5 This is a schematic diagram of the device. From Figure 5 As can be seen from the diagram, the device includes: a first processing module 50, used to decompose a target matrix into multiple target blocks based on the local memory size of the graphics processor in the edge device, wherein the target matrix includes a complex conjugate symmetric matrix; a second processing module 52, used to decompose the target blocks into diagonal blocks and off-diagonal blocks based on the diagonal of the target blocks, wherein the diagonal blocks are blocks on the target diagonal of the target block, and the off-diagonal blocks are blocks not on the target diagonal; a third processing module 54, used to retrieve the diagonal blocks and off-diagonal blocks respectively through a thread group and multiply them with the vector blocks; and a fourth processing module 56, used to accumulate the multiplication results to obtain the final calculation result, and write the final calculation result into global memory according to the thread arrangement when reading the vector blocks.

[0069] In some embodiments of this application, the step of the first processing module 50 decomposing the target matrix into multiple target blocks based on the local memory size of the graphics processor in the edge device includes: copying the target matrix from the host memory of the edge device into the global memory; determining the preset size of the target blocks based on the size of the local memory; and decomposing the target matrix according to the preset size to obtain multiple target blocks with the preset size.

[0070] In some embodiments of this application, the edge device includes multiple thread groups, and each thread group corresponds to a target block. The thread groups run on the computing cluster of the edge device and are scheduled by the graphics processor in the edge device.

[0071] In some embodiments of this application, the multiplication result includes a first multiplication result corresponding to the diagonal block and a second multiplication result corresponding to the off-diagonal block; the third processing module 54 retrieves the diagonal block and off-diagonal block and multiplies them with the vector block through the thread group, respectively, including: loading the vector block from global memory into local memory; determining the first type of elements corresponding to each diagonal block and the second type of elements corresponding to the off-diagonal block in the vector block; performing a multiplication operation on the diagonal block and the first type of elements to obtain the first multiplication result, and performing a multiplication operation on the off-diagonal block and the second type of elements to obtain the second multiplication result.

[0072] In some embodiments of this application, the diagonal block includes a first diagonal block and a second diagonal block, and the off-diagonal block includes a first off-diagonal block and a second off-diagonal block, wherein the first diagonal block and the second diagonal block are both conjugate symmetric matrices, and the elements in the first off-diagonal block and the elements in the second off-diagonal block are conjugate symmetric.

[0073] In some embodiments of this application, the second type of elements includes elements located in a first preset position range and elements in a second preset position range within the vector block; the third processing module 54 performs a multiplication operation on the off-diagonal block and the second type of elements to obtain a second multiplication result, including: performing a multiplication operation on the first off-diagonal block and the elements in the first preset position range, and transposing the second off-diagonal block by changing the index of the off-diagonal block, and performing a multiplication operation on the transposed second off-diagonal block and the elements in the second preset position range.

[0074] In some embodiments of this application, the edge device computing task partitioning method further includes: allocating a corresponding temporary storage space for each thread group in global memory, and storing the multiplication result in the temporary storage space.

[0075] It should be noted that each module in the aforementioned edge device computing task partitioning device can be a program module (e.g., a set of program instructions to implement a specific function) or a hardware module. For the latter, it can take the following forms, but is not limited to them: each of the above modules is represented by a processor, or the functions of each of the above modules are implemented by a processor.

[0076] According to an embodiment of this application, a non-volatile storage medium is provided, which stores a program. When the program runs, it controls the device where the non-volatile storage medium resides to execute the following edge device computing task partitioning method: Based on the local memory size of the graphics processor in the edge device, a target matrix is ​​decomposed into multiple target blocks, wherein the target matrix includes a complex conjugate symmetric matrix; based on the diagonal of the target blocks, the target blocks are decomposed into diagonal blocks and off-diagonal blocks, wherein diagonal blocks are blocks on the target diagonal of the target block, and off-diagonal blocks are blocks not on the target diagonal; the diagonal blocks and off-diagonal blocks are retrieved by thread groups and multiplied with vector blocks respectively; the multiplication results are accumulated to obtain the final calculation result, and the final calculation result is written into global memory according to the thread arrangement when reading vector blocks.

[0077] According to an embodiment of this application, an electronic device is provided, including a memory and a processor. The processor is used to run a program stored in the memory. During program execution, the following edge device computing task partitioning method is performed: Based on the local memory size of the graphics processor in the edge device, a target matrix is ​​decomposed into multiple target blocks, wherein the target matrix includes a complex conjugate symmetric matrix; the target blocks are decomposed into diagonal blocks and off-diagonal blocks based on their diagonals, wherein diagonal blocks are blocks located on the target diagonal of the target block, and off-diagonal blocks are blocks not located on the target diagonal; the diagonal blocks and off-diagonal blocks are retrieved and multiplied with vector blocks using thread groups respectively; the multiplication results are accumulated to obtain the final calculation result, and the final calculation result is written into global memory according to the thread arrangement when reading vector blocks.

[0078] According to an embodiment of this application, a computer program product is provided, including a computer program that, when executed by a processor, implements the following edge device computing task partitioning method: Based on the local memory size of the graphics processor in the edge device, a target matrix is ​​decomposed into multiple target blocks, wherein the target matrix includes a complex conjugate symmetric matrix; the target blocks are decomposed into diagonal blocks and off-diagonal blocks based on their diagonals, wherein diagonal blocks are blocks located on the target diagonal of the target block, and off-diagonal blocks are blocks not located on the target diagonal; the diagonal blocks and off-diagonal blocks are retrieved and multiplied with vector blocks using thread groups respectively; the multiplication results are accumulated to obtain the final calculation result, and the final calculation result is written into global memory according to the thread arrangement when reading vector blocks.

[0079] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0080] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0081] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0082] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0083] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to related technologies, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0084] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. An edge device computing task partitioning method, characterized by, include: Based on the local memory size of the graphics processor in the edge device, the target matrix is ​​decomposed into multiple target blocks, wherein the target matrix includes a complex conjugate symmetric matrix, the local memory is memory used to store shared data within the computing cluster, and the thread group runs on the computing cluster; The target block is decomposed into diagonal blocks and off-diagonal blocks based on its diagonal. The diagonal blocks are the blocks on the target diagonal of the target block, and the off-diagonal blocks are the blocks not on the target diagonal. The thread group retrieves the diagonal block and the off-diagonal block respectively and multiplies them with the vector block, wherein the vector block is a vector used to perform matrix-vector multiplication with the diagonal block and the off-diagonal block; The multiplication results are accumulated to obtain the final calculation result, and the final calculation result is written into the global memory according to the thread arrangement when reading the vector blocks. The global memory is responsible for storing the data read from the host memory.

2. The edge device computing task partitioning method according to claim 1, characterized in that, The multiplication result includes a first multiplication result corresponding to the diagonal block and a second multiplication result corresponding to the off-diagonal block; multiplying the diagonal block and the off-diagonal block with the vector block by calling the thread group respectively includes: The vector is loaded from the global memory into the local memory in blocks; Determine the first type of elements corresponding to each of the diagonal blocks and the second type of elements corresponding to the off-diagonal blocks in the vector block; The diagonal block is multiplied by the first type of element to obtain a first multiplication result, and the off-diagonal block is multiplied by the second type of element to obtain a second multiplication result.

3. The edge device computing task partitioning method according to claim 2, characterized in that, The diagonal blocks include a first diagonal block and a second diagonal block, and the off-diagonal blocks include a first off-diagonal block and a second off-diagonal block. The first diagonal block and the second diagonal block are both conjugate symmetric matrices, and the elements in the first off-diagonal block and the elements in the second off-diagonal block are conjugate symmetric.

4. The edge device computing task partitioning method according to claim 3, characterized in that, The second type of elements includes elements located in a first preset position range and elements located in a second preset position range within the vector block; Multiplying the off-diagonal block and the second type of element yields the following second multiplication result: The first off-diagonal block and the elements of the first preset position range are multiplied together, and the second off-diagonal block is transposed by changing the index of the off-diagonal block, and the transposed second off-diagonal block and the elements of the second preset position range are multiplied together.

5. The edge device computing task partitioning method according to claim 1, characterized in that, Based on the local memory size of the graphics processor in the edge device, decomposing the target matrix into multiple target blocks includes: The target matrix is ​​copied from the host memory of the edge device to the global memory; The preset size of the target block is determined based on the size of the local memory, and the target matrix is ​​decomposed based on the preset size to obtain multiple target blocks with the preset size.

6. The edge device computing task partitioning method according to claim 1, characterized in that, The edge device includes multiple thread groups, and each thread group corresponds to a target block. The thread groups run on the computing cluster of the edge device and are scheduled by the graphics processor in the edge device.

7. The edge device computing task partitioning method according to claim 1, characterized in that, The edge device computing task partitioning method also includes: In the global memory, a corresponding temporary storage space is allocated for each thread group, and the multiplication result is stored in the temporary storage space.

8. An edge device computing task partitioning apparatus, characterized in that, include: The first processing module is used to decompose the target matrix into multiple target blocks based on the local memory size of the graphics processor in the edge device. The target matrix includes a complex conjugate symmetric matrix, and the local memory is memory used to store shared data within the computing cluster. The thread group runs on the computing cluster. The second processing module is used to decompose the target block into diagonal blocks and off-diagonal blocks based on the diagonal of the target block, wherein the diagonal blocks are blocks on the target diagonal of the target block, and the off-diagonal blocks are blocks not on the target diagonal. The third processing module is used to retrieve the diagonal block and the off-diagonal block and multiply them with the vector block through the thread group respectively, wherein the vector block is a vector used to perform matrix-vector multiplication operation with the diagonal block and the off-diagonal block; The fourth processing module is used to accumulate the multiplication results to obtain the final calculation result, and write the final calculation result into the global memory according to the thread arrangement when reading the vector blocks. The global memory is responsible for storing the data read from the host memory.

9. A non-volatile storage medium, characterized in that, The non-volatile storage medium stores a program, wherein when the program runs, it controls the device where the non-volatile storage medium is located to execute the edge device computing task partitioning method according to any one of claims 1 to 7.

10. An electronic device, characterized in that, include: A memory and a processor, the processor being configured to run a program stored in the memory, wherein the program, when running, executes the edge device computing task partitioning method according to any one of claims 1 to 7.

11. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the edge device computing task partitioning method according to any one of claims 1 to 7.

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