An efficient on-chip repair circuit and method based on multi-directional shifting interconnects
By arranging redundant interconnects at the diagonal positions of the interconnect array and designing multi-directional shift repair units, the problems of low repair rate, dependence on external equipment, and long repair time in the prior art are solved, realizing efficient and autonomous chip fault repair, which is suitable for high-performance computing and chip-integrated systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG UNIV
- Filing Date
- 2026-04-10
- Publication Date
- 2026-07-21
AI Technical Summary
Existing interconnect redundancy repair technologies suffer from limited repair rates, reliance on external devices, complex repair architecture leading to routing congestion, and high repair time costs, making it difficult to effectively improve chip yield while controlling costs.
A high-efficiency on-chip automatic repair circuit based on multi-directional shifting is adopted. By arranging redundant interconnects at the diagonal position of the interconnect array and combining the multi-directional shifting mechanism, a repair unit and priority mechanism are designed to realize autonomous repair path selection and switching, reduce dependence on external devices, and improve repair success rate and efficiency.
It achieves high repair rate and low cost autonomous repair, adapts to various fault distributions, reduces signal delay and wiring congestion, and is suitable for online fault repair during chip manufacturing and operation, especially for high-performance computing and chip-integrated systems.
Smart Images
Figure CN122044964B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of fault-tolerant design technology for very large-scale integrated circuits, and particularly relates to an efficient on-chip automatic repair circuit and method based on multi-directional shifting interconnection. Background Technology
[0002] As integrated circuit manufacturing processes approach their physical limits, integrated chip technology has emerged as a new path to improve chip performance and integration. Through chip-to-chip interconnect (CTI) technology, integrated chips achieve functional integration of individual chips, overcoming the yield and cost limitations of existing chip manufacturing while simultaneously increasing system integration and performance optimization potential. However, the CTI interconnect interfaces used in integrated chip packaging are characterized by their large number, high space density, and complex manufacturing processes, posing a key challenge to improving integrated chip yield.
[0003] During the bonding process of chip interconnects, random electrical faults may occur due to differences in process technology and operating environment, leading to interconnect communication failure. To improve the reliability of chip interconnect communication and increase chip manufacturing yield, researchers have proposed a variety of fault-tolerant design techniques at various levels, including: fault-tolerant coding techniques at the data link layer; digital clock calibration techniques at the physical link layer; and the interconnect redundancy repair techniques at the electrical layer studied in this patent.
[0004] Interconnect redundancy repair technology in chip technology is an important method to improve chip yield and reliability. Its core idea is to pre-embed spare redundant interconnect units in the chip during manufacturing. During chip testing, if a manufacturing defect is found in an original unit or it fails later in use, the system can actively switch the signal path to the spare redundant interconnect through internal fuses, software configuration, or hardware rerouting, thereby bypassing the faulty node and allowing the defective chip to function normally. This greatly relaxes the stringent requirements on the manufacturing yield of individual chips and is a key technological guarantee for improving the yield of large-scale, high-performance chip-integrated systems. However, traditional interconnect redundancy repair designs still have significant shortcomings. Some solutions have low repair capabilities and cannot meet chip requirements, while others design complex repair paths to ensure repair capabilities, but this leads to problems such as hardware wiring congestion and excessively long repair paths. Furthermore, there is the burden of repair time costs due to dependence on external computing devices.
[0005] Therefore, how to efficiently repair chip interconnects while controlling costs and striving for a higher chip repair rate is a key issue that urgently needs to be addressed.
[0006] Currently, research on interconnect redundancy repair technology mainly focuses on two core aspects: the design of redundancy repair routing schemes and the development of repair data generation algorithms. To improve the repair success rate and the utilization efficiency of redundant resources, a flexible repair routing architecture needs to be designed. Furthermore, due to the uncertainty of the location of faulty interconnects, each chip has a unique fault distribution. Industrial production typically requires the use of a matching repair data generation algorithm to perform calculations externally to write the repair information into the chip.
[0007] Early proposed linear shift-based repair routing schemes have simple structures and are easy to expand the number of redundant interconnects. They perform well under the assumption of randomly distributed interconnect faults and have become a typical method [1]. However, interconnect faults in actual cores often exhibit clustered distribution characteristics, that is, the fault locations tend to be close to each other in space, which poses a challenge to the traditional uniform repair strategy. To deal with the fault clustering effect, researchers have proposed a routing scheme based on group selectors, which divides the interconnects into several groups and configures selectors in each group to support fault repair within and across groups. Although this scheme significantly improves the repair rate, cross-group repair paths are prone to causing wiring congestion, and the extension of the wiring path will lead to an increase in signal delay and affect signal quality. Most of the current mainstream repair schemes adopt a net-like or spider-like routing structure based on multi-level displacement. Fault interconnects can switch paths between grid nodes, taking into account both high repair rate and wiring controllability. However, such schemes rely on complex repair algorithms and require external computing resources, thus introducing significant repair time overhead.
[0008] Various repair routing schemes typically employ dedicated generation algorithms, most of which are based on the maximum flow algorithm. Considering the algorithm computation time, fault information reading time, and repair data writing time, the overall time cost of redundant repair is high. Furthermore, since the repair data is not reusable, each faulty chip needs to perform independent calculations. To address this, some research has proposed on-chip self-repair architectures that achieve autonomous repair through digital logic, offering high efficiency. However, these architectures often employ simplified linear shift routing structures, making them primarily suitable for simple, small-scale faults, and their ability to repair clustered faults remains limited.
[0009] Existing interconnect redundancy technologies still have the following shortcomings:
[0010] Dependence on external devices: Most current solutions rely on off-chip computing resources to generate repair configuration data. This process involves multiple steps, including fault information reading, algorithm calculation, and repair data writing, which not only significantly increases repair time and costs but also limits system-in-package (SiP) or chiplets to repair only at specific stages.
[0011] Limited repair rate: When faced with the clustering effect of faults, the existing redundant structure often suffers from a decrease in the success rate of repair due to uneven distribution of backup resources or insufficient flexibility in path selection mechanism.
[0012] Complex repair architecture leads to routing congestion: In order to improve repair flexibility, some solutions have expanded the diversity of repair paths, but introduced a large number of multiplexers and cross-connects, which occupy cabling resources, increase signal transmission delay and power consumption, and thus affect the overall system performance. Summary of the Invention
[0013] The purpose of this invention is to provide an efficient on-chip automatic repair circuit and method based on multi-directional shifting interconnection to solve the above-mentioned technical problems.
[0014] To address the aforementioned technical problems, this invention proposes a high-efficiency on-chip automatic repair circuit based on multi-directional shifting. This circuit expands the repair path selection and introduces an automatic defect repair mechanism to reduce the cost of redundant repair of chip interconnects and dependence on external devices, thereby improving chip yield. The specific technical solution is as follows:
[0015] A high-efficiency on-chip automatic repair circuit based on multi-directional shifting interconnection, comprising:
[0016] The interconnect repair array consists of functional interconnects and redundant interconnects arranged according to a predetermined topology.
[0017] The redundant interconnects are arranged at the diagonal position of the array, and the functional interconnects are moved along the diagonal direction from both sides of the array toward the center in order of priority to form a multi-directional repair path;
[0018] Each interconnect node corresponds to a repair unit, the repair unit comprising:
[0019] The repair unit input module is used to receive the original interconnect input and multiple multiplexed interconnect inputs, as well as the corresponding repair request signal;
[0020] The signal switching module switches signals based on repair requests and preset repair priorities through combinational logic.
[0021] The fault status storage module is used to store the fault status of the current interconnected nodes;
[0022] The repair unit output module is used to output repair request signals and repair status feedback signals to coordinate multi-level repairs.
[0023] Furthermore, the functional interconnection repair unit includes N1 multiplexed interconnection inputs and corresponding N1 repair request inputs, where N1 ranges from 1 to 4.
[0024] The redundant interconnect repair unit contains N2 multiplexed interconnect inputs, where N2 is greater than N1.
[0025] Furthermore, the fault status of the fault status storage module is written by an external testing device, or dynamically written by an internal self-test program or hardware monitoring circuit.
[0026] Furthermore, the number of repair status feedback signals output by the repair unit output module is N1-1, which is used to feed back the current node's occupancy status to adjacent interconnections with lower priority.
[0027] This invention also discloses a high-efficiency on-chip automatic repair method for interconnects based on multi-directional shifting, applied to the aforementioned circuit, comprising the following steps:
[0028] S1: Starting from one side of the array, initiate repair requests level by level from the node furthest from the redundant interconnect to the node closest to the redundant interconnect;
[0029] S2: Each repair unit makes signal switching decisions based on its own fault status and the received repair requests, according to the preset repair priority;
[0030] S3: After completing the first round of repair, proceed to adjacent areas in sequence to form a hierarchical iterative repair;
[0031] S4: Repeat the above steps from the other side of the array to achieve bidirectional repair until the repair path of all faulty nodes finally reaches the redundant interconnect node.
[0032] Furthermore, the repair priority setting includes:
[0033] When the repair unit receives multiple repair requests at the same time, only the repair path with the highest priority is enabled;
[0034] The faulty node sends a repair request to the adjacent unoccupied nodes on the output side in order of priority from low to high.
[0035] After a node fails or is repaired, it reports its occupancy status to other adjacent nodes on the input side to avoid duplicate requests.
[0036] Furthermore, the repair priority is set along the array direction as follows:
[0037] Based on the diagonal of the redundant interconnect, the farther away the node is, the higher the priority for repair;
[0038] For each column of nodes parallel to the redundant interconnect, the repair priority direction is consistent, from the long side to the short side;
[0039] The priority settings on both sides of the diagonal are symmetrically distributed.
[0040] Furthermore, the repair process employs a pipeline approach to process repair operations in multiple areas in parallel, without interference between them.
[0041] Furthermore, the priority settings for the repair path include:
[0042] Prioritize the shortest repair path to reduce signal delay;
[0043] The next priority is to choose a slightly longer path to deal with clustered faults.
[0044] The present invention provides a high-efficiency on-chip automatic repair circuit and method based on multi-directional shifting interconnection, which has the following advantages:
[0045] 1. High Repair Rate and Adaptability: By arranging redundant interconnects diagonally across the interconnect array and combining them with a multi-directional shift mechanism, effective repair of clustered faults is achieved. Even in cases where faults are concentrated, high-success-rate repairs can still be achieved through flexible path selection, significantly improving chip yield and reliability.
[0046] 2. Fully On-Chip Automated Repair: This invention does not rely on external computing devices or complex repair algorithms. It utilizes a fault state storage module and combinational logic circuits to achieve autonomous decision-making and switching of repair paths, supporting dynamic repair during chip testing and operation phases, and significantly reducing repair time and costs.
[0047] 3. Flexible and controllable repair path: The repair unit supports multiple multiplexed interconnection inputs, combined with a priority setting mechanism (such as shortest path priority and second-best path backup), effectively dealing with various fault distribution scenarios while ensuring signal quality, and avoiding wiring congestion and signal delay problems caused by long lines.
[0048] 4. Streamlined Parallel Repair: The repair process adopts a bidirectional, step-by-step, and pipelined parallel processing method, allowing repair operations in different areas to be performed simultaneously without interference, significantly improving repair efficiency and shortening the overall repair time.
[0049] 5. High hardware resource utilization: Through reasonable redundant interconnect layout and priority setting, it maximizes the use of limited redundant resources, avoids resource waste, and maintains low hardware overhead, making it suitable for large-scale integrated chips and chip systems.
[0050] 6. High adaptability and wide range of applications: This invention is not only applicable to improving yield in the chip manufacturing stage, but also supports online fault repair during chip operation. It has broad application prospects and is particularly suitable for fields such as high-performance computing, chip integration, and system-in-package.
[0051] In summary, this invention has significant advantages in terms of repair capability, repair speed, signal quality, hardware overhead, and automation, providing an efficient and low-cost on-chip self-repair solution for solving the reliability problem of chip interconnects. Attached Figure Description
[0052] Figure 1 This is a schematic diagram of the interconnect repair array structure of the present invention;
[0053] Figure 2(a) is a schematic diagram of the functional interconnection repair unit structure of the present invention;
[0054] Figure 2(b) is a schematic diagram of the redundant interconnection repair unit structure of the present invention;
[0055] Figure 3 This is a schematic diagram illustrating the interconnect array repair priority of the present invention;
[0056] Figure 4(a) is a schematic diagram of the repair response priority setting in an embodiment of the present invention;
[0057] Figure 4(b) is a schematic diagram of the priority setting for processing repair requests according to an embodiment of the present invention;
[0058] Figure 5 This is a schematic diagram illustrating a fault repair example of the present invention. Detailed Implementation
[0059] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides an efficient on-chip automatic repair circuit and method based on multi-directional shifting.
[0060] To improve the success rate of fault repair, repair nodes need to have the ability to switch between multiple interconnect signals, thereby constructing a repair architecture network that supports multiple selectable paths. However, existing mesh repair structures typically place redundant interconnects at the array edges or corners, resulting in a complex distribution of potential repair paths, which is not conducive to achieving efficient on-chip autonomous repair control.
[0061] Therefore, this invention proposes a high-efficiency on-chip automatic repair circuit based on multi-directional shifting, comprising an interconnect repair array, wherein the interconnect repair array includes functional interconnects and redundant interconnects arranged according to a predetermined topology; such as Figure 1 As shown in the diagram. In this layout, redundant interconnects are arranged along a diagonal of the array, while functional interconnects are progressively shifted diagonally along the repair direction from both sides of the array toward the center, forming repair paths in an order from far to near.
[0062] To implement the above-mentioned repair mechanism, this invention designs a dedicated repair unit. The functionally interconnected repair unit is shown in Figure 2(a) and includes the following four parts.
[0063] Repair Unit Input Module: Each functional interconnection's corresponding repair unit contains N1+1 input signals, namely 1 original interconnection input and N1 switchable multiplexed interconnection inputs. It also includes N1 repair request inputs, each corresponding to one of the N1 multiplexed interconnection inputs. Depending on different failure rates and repair rate requirements, N1 can be arbitrarily selected between 1 and 4; the larger N1 is, the stronger the repair capability.
[0064] Signal switching module: This module switches signals according to the repair priority based on the input repair request to complete the interconnection repair. The switching decision is made in real time by combinational logic, without relying on clock control, thus ensuring low latency in the repair process.
[0065] Fault status storage module: Stores the fault status of the current interconnect node. The fault status value can be written in two ways: one is by external test equipment through a dedicated interface during the chip testing phase; the other is by internal self-test program or hardware monitoring circuit automatically during the chip operation phase, realizing dynamic fault detection and repair.
[0066] Repair Unit Output Module: If the current interconnect fails or a signal switch occurs, the repair unit will output a repair request signal to the next-level unit for the next round of repair. In addition, this module will output N1-1 repair status signals to feed back the current node's occupancy status to adjacent interconnects with lower priority. Taking a four-input unit with N1=4 as an example, repair statuses 2, 3, and 4 will be fed back to adjacent interconnects with priorities of second, third, and fourth, respectively, to coordinate multi-level repair decisions. Adjacent interconnects with the highest priority do not need to consider preemption issues caused by higher-priority interconnects; therefore, they can directly make decisions based on the node fault status stored in the current fault status storage module.
[0067] The structure of the repair unit corresponding to the redundant interconnect is shown in Figure 2(b). The functional modules of the repair unit of the redundant interconnect are the same as those of the functional interconnect repair unit. Since the redundant interconnect only undertakes the repair function, the input of the repair unit of the redundant interconnect is less than that of the original interconnect, but it has more interconnect input ports and repair status feedback signals to enhance the flexibility of path selection. Each repair unit corresponding to the redundant interconnect contains N2 input signals, where N2 is generally larger than N1, thereby improving the utilization rate of redundant resources and the overall repair success rate.
[0068] To balance area and repair efficiency, this invention does not employ a state machine-based control method. Instead, it directly implements a fully automated repair process through fault status registers and combinational logic. By guiding faulty nodes to switch along a preset repair path, the expected step-by-step automatic repair can be achieved. Therefore, this invention establishes an interconnection repair priority mechanism, with the following specific rules:
[0069] (1) When the repair unit receives multiple repair requests at the same time, it will only enable the repair path of the node with the highest priority of interconnect repair, and other requests will be temporarily blocked and wait for subsequent repair cycles to process.
[0070] (2) When an interconnection node fails, repair requests will be sent to adjacent unoccupied nodes on the output side in order of interconnection repair priority from low to high. That is, priority will be given to repairing nodes with lower priority, and if that fails, a request will be sent to nodes with higher priority.
[0071] (3) When a node fails or completes a repair (i.e., the node is used to carry signals from other failed nodes), it will send an occupancy status signal back to the remaining adjacent interconnects on the input side to inform these nodes that the resource has been occupied, thus avoiding duplicate requests.
[0072] Figure 3 The overall repair priority settings for the rectangular array are shown, with repair priorities decreasing from high to low as indicated by the arrows. The specific settings are as follows:
[0073] As shown by the red solid arrow, with the diagonal line of the redundant interconnect as the baseline, interconnect nodes farther away from the redundant interconnect have a higher repair priority. This setting allows faults to propagate step by step from the array edge to the central redundant resources, forming an orderly repair flow.
[0074] As shown by the black dashed arrow, each column of interconnect nodes parallel to the redundant interconnect has the same repair priority direction, that is, from the long side of the trapezoid to the short side, ensuring the consistency of the repair path within the same column.
[0075] Priority settings are perfectly symmetrical on both sides of the redundant interconnect diagonal. This setting is more adaptable to the clustering effect of interconnect failures, and can effectively guide the faults to redundant resources regardless of which side of the array is concentrated.
[0076] Based on the above priority mechanism, the automatic repair process of this invention can be described as follows:
[0077] Step 1: Starting from the upper right corner of the array, repair requests are initiated tier by tier from nodes furthest from the redundant interconnects to nodes closest to the redundant interconnects. Each node makes a signal switching decision based on its own fault status and the received repair requests, according to priority rules.
[0078] Step 2: After completing the first round of repairs, proceed sequentially to the left and downwards, forming a pyramid-like hierarchical iteration. Within each level, switching and judgment are performed in order from left to right to ensure the repair process proceeds in an orderly manner.
[0079] Step 3: Starting from the lower left corner of the array, repeat the above logic to repair redundant interconnects from the other side towards the diagonal direction.
[0080] Step 4: The entire repair process is completed efficiently in a pipeline manner. Repair operations in different areas can be carried out in parallel without interference, until the repair paths of all faulty nodes finally reach the redundant interconnection nodes.
[0081] The advantages of this bidirectional repair strategy are: on the one hand, it makes full use of the repair paths on both sides of the array, improving the utilization rate of redundant resources; on the other hand, it avoids the path congestion problem that may be caused by unidirectional repair.
[0082] Repair example:
[0083] We will use an 8x8 interconnect array with N1=4 interconnect repair units as an example to demonstrate the specific repair implementation process. It should be noted that the size of the array and the parameters of the repair units used can be adjusted according to the actual situation and are not strictly limited.
[0084] Since each repair unit contains four multiplexed interconnect signal inputs, it can support interconnect signal switching in up to four directions (corresponding to the four arrows in Figure 4(a) and Figure 4(b)). According to the aforementioned repair priority rules, the fault node can be guided to perform step-by-step repair along the preset priority path.
[0085] Specifically, for the interconnect located in the upper right corner of the array diagonal, if we select four nodes in its upper right region (purple region) for repair, the repair response priority setting should be as shown in Figure 4(a), where,
[0086] Arrows 1 and 2 indicate the preferred adjacent shortest repair path, which can reduce the additional delay introduced by the repair and reduce the impact on the timing of interconnect array signals.
[0087] Arrows 3 and 4 indicate slightly longer repair paths, used to address clustered faults and improve the ability to repair complex fault distributions. These two paths have lower priority than arrows 1 and 2 and are related to the signal trace length.
[0088] For the interconnects located in the lower left diagonal of the array, the priority of repair requests for the nodes in its lower left region (green) is shown in Figure 4(b). This priority setting is symmetrical to the upper right region, thus forming a coordinated redundancy repair trend throughout the array.
[0089] by Figure 5 The following example illustrates the automatic repair result under a typical fault scenario. Each arrow in the diagram represents a signal switching operation, and the boxes at the beginning and end represent the interconnecting nodes performing the signal switching:
[0090] The first step is to start repairing from the top right interconnect node 1 of the array. Based on the fault condition and the repair priority set in section B, switch from 1 to 9.
[0091] The second step is to start repairing interconnect node 2 and switch it from 2 to 4, and then start repairing interconnect node 3 and switch it from 3 to 6.
[0092] The third step is to repair interconnected nodes 4, 5, and 6 in sequence, and then switch them to 4->7, 5->8, and 6->10.
[0093] The fourth step is to repair interconnected nodes 7, 8, 9, and 10 in sequence.
[0094] This process continues until the switching endpoint reaches the redundant interconnect node.
[0095] This example demonstrates that the entire repair process requires no external intervention and is completed automatically by the on-chip logic; the repair path length is controlled within 2-3 hops, effectively controlling signal delay; and multiple fault nodes can be processed in parallel, resulting in high repair efficiency.
[0096] The automatic interconnect repair method proposed in this invention exhibits significant advantages in both circuit design and method design.
[0097] In terms of circuit design, this invention innovatively uses a multi-directional displacement redundant repair circuit, which can effectively improve the flexibility of the repair channel, ensure a high repair rate and a short repair path, while avoiding layout congestion caused by long-distance routing.
[0098] In terms of method design, this invention specifically optimizes the repair algorithm, achieving fully automated on-chip repair. This strategy significantly shortens repair time, providing a faster repair solution for chips. Compared to solutions limited to production processes, this invention has a wider range of applicability.
[0099] In summary, this invention has significant advantages over existing solutions in terms of repair capability, repair speed, signal quality, and external testing equipment requirements, and can better meet the stringent requirements of high-performance chips for the reliability of chip interconnects.
[0100] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.
Claims
1. A high-efficiency on-chip automatic repair circuit based on multi-directional shifting interconnection, characterized in that, include: The interconnect repair array consists of functional interconnects and redundant interconnects arranged according to a predetermined topology. The redundant interconnects are arranged on one diagonal of the array, and the functional interconnects are moved diagonally in a repair direction from both sides of the array toward the center, forming a repair path in order from far to near. With the diagonal of the redundant interconnect as the baseline, the interconnect nodes farther away from the redundant interconnect have a higher repair priority. Each column of interconnect nodes parallel to the redundant interconnect has the same repair priority direction, that is, from the long side of the trapezoid to the short side. The multi-directional repair path starts from one side of the array and initiates repair requests step by step from the node furthest from the redundant interconnect to the node closest to the redundant interconnect. Each interconnect node corresponds to a repair unit, the repair unit comprising: The repair unit input module is used to receive the original interconnect input and multiple multiplexed interconnect inputs, as well as the corresponding repair request signal; The signal switching module switches signals based on repair requests and preset repair priorities through combinational logic. The fault status storage module is used to store the fault status of the current interconnected nodes; The repair unit output module is used to output repair request signals and repair status feedback signals to coordinate multi-level repairs.
2. The high-efficiency on-chip automatic repair circuit based on multi-directional shifting according to claim 1, characterized in that, The functional interconnection repair unit includes N1 multiplexed interconnection inputs and corresponding N1 repair request inputs, where the value of N1 ranges from 1 to 4. The redundant interconnect repair unit contains N2 multiplexed interconnect inputs, where N2 is greater than N1.
3. The high-efficiency on-chip automatic repair circuit based on multi-directional shifting interconnection according to claim 1, characterized in that, The fault status of the fault status storage module is written by an external testing device or dynamically by an internal self-test program or hardware monitoring circuit.
4. The high-efficiency on-chip automatic repair circuit based on multi-directional shifting according to claim 1, characterized in that, The repair unit output module outputs a repair status feedback signal of N1-1, which is used to provide feedback on the current node's occupancy status to adjacent interconnections with lower priority.
5. A high-efficiency on-chip automatic repair method for interconnects based on multi-directional shifting, applied to the circuit described in any one of claims 1 to 4, characterized in that, Includes the following steps: S1: Starting from one side of the array, initiate repair requests level by level from the node furthest from the redundant interconnect to the node closest to the redundant interconnect; S2: Each repair unit makes signal switching decisions based on its own fault status and the received repair requests, according to the preset repair priority; S3: After completing the first round of repair, proceed to adjacent areas in sequence to form a hierarchical iterative repair; S4: Repeat the above steps from the other side of the array to achieve bidirectional repair until the repair path of all faulty nodes finally reaches the redundant interconnect node.
6. The high-efficiency on-chip automatic repair method based on multi-directional shifting for interconnects according to claim 5, characterized in that, The repair priority setting includes: When the repair unit receives multiple repair requests at the same time, only the repair path with the highest priority is enabled; The faulty node sends a repair request to the adjacent unoccupied nodes on the output side in order of priority from low to high. After a node fails or is repaired, it reports its occupancy status to other adjacent nodes on the input side to avoid duplicate requests.
7. The high-efficiency on-chip automatic repair method based on multi-directional shifting for interconnects according to claim 6, characterized in that, The repair priority is set along the array direction as follows: Based on the diagonal of the redundant interconnect, the farther away the node is, the higher the priority for repair; For each column of nodes parallel to the redundant interconnect, the repair priority direction is consistent, from the long side to the short side; The priority settings on both sides of the diagonal are symmetrically distributed.
8. The high-efficiency on-chip automatic repair method based on multi-directional shifting for interconnects according to claim 5, characterized in that, The repair process employs a pipeline approach to handle repair operations in multiple areas in parallel, without interference between them.
9. The high-efficiency on-chip automatic repair method based on multi-directional shifting for interconnects according to claim 5, characterized in that, The priority settings for the repair paths include: Prioritize the shortest repair path to reduce signal delay; The next priority is to choose a slightly longer path to deal with clustered faults.