A self-adaptive mapping flash memory control method and a flash memory control system

Abstract

This application relates to the field of flash memory technology and discloses an adaptive mapping flash memory control method and a flash memory control system. The method first receives a data write instruction and parses it to obtain the logical address sequence corresponding to the data to be written. If the logical address sequence is a continuous sequence of logical addresses and the number of consecutive logical addresses reaches a preset threshold, a segmented mapping mode is triggered. In segmented mapping mode, a single segmented mapping entry is created in the L2P mapping table for a continuous logical page address region. Based on the segmented mapping entry, the data to be written is written to the physical page address allocated starting from the starting physical address. When a data read instruction for the continuous logical page address region is received, the L2P mapping table is searched according to the target logical address to locate the segmented mapping entry containing the target logical address. Based on the starting logical address and starting physical address in the located segmented mapping entry, the target physical address corresponding to the target logical address is calculated, and a data read operation is performed.

Description

Technical Field

[0001] This invention relates to the field of flash memory technology, and more specifically to an adaptive mapping flash memory control method and a flash memory control system. Background Technology

[0002] Flash memory, due to its advantages such as high read / write speed, low power consumption, and strong shock resistance, has been widely used in various flash memory control systems. Common flash memory control systems include embedded multimedia cards (eMMC), universal flash storage (UFS), and solid-state drives (SSDs). In these flash memory control systems, the Flash Translation Layer (FTL) is a core functional module. Its core responsibility is to maintain the mapping relationship between logical addresses (LBAs) and physical addresses (PBAs), i.e., the L2P (Logical to Physical) mapping table. Through this mapping table, the logical address of the host side is converted to the physical address of the flash memory chip, ensuring the correct writing and reading of data.

[0003] Currently, mainstream FTL mapping schemes generally adopt a page-level mapping mechanism, which means that for each logical page of a fixed size (usually 4KB, also known as a sector), an independent mapping record is configured in the L2P mapping table. This page-level mapping mechanism has the characteristics of high address translation accuracy and flexible data updates, and can well adapt to the address mapping requirements in random read and write scenarios. Therefore, it has been widely used in various flash memory control systems.

[0004] However, in real-world applications, host-initiated data write operations are not entirely random; instead, there are numerous scenarios involving the writing of contiguous logical address blocks, such as batch writing of large files, operating system image updates, and batch database storage. In these contiguous write scenarios, the shortcomings of existing page-level mapping mechanisms become increasingly apparent: because each logical page corresponds to an independent L2P mapping entry, when writing contiguous logical address blocks, even if the logical addresses corresponding to the data to be written are contiguous and numerous, the FTL still needs to create or update the corresponding L2P mapping entry for each logical page one by one, resulting in a significant increase in the number of L2P mapping table update operations. These frequent L2P mapping update operations consume a large amount of system bus bandwidth and FTL processing resources, reducing the overall efficiency of data writing, especially when the amount of data being written continuously is large, this efficiency loss is even more pronounced. Summary of the Invention

[0005] The main objective of this invention is to provide an adaptive mapping flash memory control method and flash memory control system, which aims to solve the technical problem that frequent L2P mapping update operations in the prior art lead to a decrease in the overall efficiency of data writing.

[0006] To achieve the above objectives, in a first aspect, this application provides an adaptive mapping flash memory control method, the method comprising:

[0007] Receive a data write instruction and parse the data write instruction to obtain the logical address sequence corresponding to the data to be written;

[0008] When the logical address sequence is a continuous logical address and the number of consecutive addresses reaches a preset threshold, the segmented mapping mode is triggered.

[0009] In the segmented mapping mode, a single segmented mapping entry is created in the L2P mapping table for consecutive logical page address regions to complete the mapping relationship of the consecutive logical page address regions. The segmented mapping entry includes at least the starting logical address, the starting physical address, the length value of the consecutive logical pages, and the mode flag bit.

[0010] According to the segment mapping entry, the data to be written is written to the physical page address allocated starting from the starting physical address;

[0011] When a data read instruction for the continuous logical page address region is received, the L2P mapping table is searched according to the target logical address to locate the segment mapping entry containing the target logical address;

[0012] Based on the starting logical address and starting physical address in the located segment mapping entry, the target physical address corresponding to the target logical address is calculated using the offset, and a data reading operation is performed based on the target physical address.

[0013] In one possible implementation, the method further includes:

[0014] Real-time monitoring of the flash memory controller's CPU utilization, physical page allocation time, and mapping table update bandwidth;

[0015] If the CPU utilization rate is higher than the first preset load threshold, the physical page allocation time exceeds the preset duration threshold, or the mapping table update bandwidth reaches the upper limit, then the preset threshold is reduced to reduce the difficulty of triggering the segmented mapping mode.

[0016] If the CPU utilization rate is lower than the second preset load threshold, the physical page allocation time is less than the preset duration threshold, and there is redundancy in the mapping table update bandwidth, then the preset threshold is increased to increase the difficulty of triggering the segmented mapping mode.

[0017] In one possible implementation, prior to the trigger segment mapping pattern, the following is also included:

[0018] Maintain an allocation state diagram of a physically contiguous space pool in the system region of flash memory;

[0019] When the segmented mapping mode is triggered, free blocks with matching lengths and contiguous physical addresses are preferentially allocated from the physical contiguous space pool for the segmented mapping entry;

[0020] If the continuous length requirement cannot be met in the physical contiguous space pool, the data to be written is split into multiple sub-segments, and the maximum possible continuous physical space is allocated to each sub-segment in the physical contiguous space pool. An independent segment mapping entry is created for each sub-segment, and all entries are logically marked as belonging to the same logical segment sequence.

[0021] In one possible implementation, creating a single segmented mapping entry for contiguous logical page address regions in the L2P mapping table includes:

[0022] Obtain the historical wear parameters of the free physical pages corresponding to the candidate starting physical address;

[0023] Based on the historical wear parameters, determine whether the continuous physical page allocation scheme starting from the candidate starting physical address meets the preset wear leveling conditions;

[0024] If the conditions are met, the segmented mapping entry is created using the candidate starting physical address as the starting physical address.

[0025] If it does not meet the requirements, a new candidate starting physical address is selected as the starting physical address, and the above acquisition and judgment steps are repeated until a physical address allocation scheme that meets the wear leveling conditions is found.

[0026] In one possible implementation, the preset wear leveling conditions include:

[0027] There is no consecutive preset number of physical page addresses whose wear levels are all greater than or equal to the first wear level threshold; and / or,

[0028] The average wear value corresponding to consecutive physical page addresses is less than or equal to the second wear threshold.

[0029] In one possible implementation, when performing a data read operation based on the segmented mapping entry, the method further includes:

[0030] If the amount of data to be read exceeds one logical page, the pre-read range is determined based on the length information in the segmented mapping entry and the current free space in the cache, and the subsequent consecutive physical page data, including the target physical address, is pre-read into the cache.

[0031] The pre-read range does not exceed the total length of the continuous physical pages corresponding to the segmented mapping entries, and the storage occupancy of the pre-read data does not exceed a preset proportion of the cache free space.

[0032] In one possible implementation, determining the pre-read range based on the length information in the segmented mapping entry and the current cache free space includes:

[0033] Based on the number of remaining consecutive physical pages corresponding to the segmented mapping entry, determine the maximum upper limit of the pre-read range;

[0034] If the free space ratio of the cache is higher than the preset cache threshold, a full pre-read will be performed at the maximum limit, reading all remaining consecutive physical page data into the cache at once to maximize the response speed of subsequent consecutive reads;

[0035] If the proportion of free space in the cache is lower than the preset cache threshold, segmented pre-reading is performed according to the preset step size, and continuous physical page data is written to the cache segment by segment to balance pre-reading efficiency and cache resource consumption.

[0036] In one possible implementation, the method further includes:

[0037] Monitor whether subsequent write operations target contiguous logical address regions of already established segmented mapping entries;

[0038] If subsequent write operations only cover a portion of the logical addresses within the region, the original segmented mapping entry is split into at least two new mapping entries based on the position of the covered region within the original contiguous logical address region. These new entries correspond to the unupdated contiguous logical address sub-region and the updated logical address region, respectively.

[0039] In one possible implementation, after splitting the original segmental mapping entry into at least two new mapping entries, the method further includes:

[0040] The length of the unupdated contiguous logical address sub-region is determined. If the length of the sub-region is less than a preset length threshold, it is converted from segment mapping mode to page mapping mode; if the length of the sub-region is not less than the preset length threshold, the segment mapping mode is maintained.

[0041] For the updated logical address region, based on the logical address continuity corresponding to subsequent write operations, the segment mapping mode or page mapping mode is adaptively selected to establish the corresponding mapping entries.

[0042] The original segmented mapping entries are marked as invalid, and the L2P mapping table is updated synchronously to complete the update of the mapping relationship after splitting.

[0043] In one possible implementation, the method further includes:

[0044] In the L2P mapping table, a heat counter is associated with each segmented mapping entry;

[0045] When a read or write access occurs to the logical address range covered by the segmented mapping entry, increment its corresponding hot counter.

[0046] The segmented mapping entries are periodically sorted according to the heat counter. The top N segmented mapping entries with the highest heat and all the physical page data they map are migrated as a whole to a flash memory medium area with better read and write performance or lower latency, and the mapping entries are updated after migration.

[0047] Secondly, embodiments of this application also provide a flash memory control system, including:

[0048] Memory, the memory being used to store program code; and

[0049] A processor, the processor being configured to invoke the program code to execute the method as described in the first aspect.

[0050] Unlike existing technologies, the adaptive mapping flash memory control method provided in this application first receives a data write instruction and parses it to obtain the logical address sequence corresponding to the data to be written. If the logical address sequence is a continuous logical address and the number of consecutive logical addresses reaches a preset threshold, a segment mapping mode is triggered. In segment mapping mode, a single segment mapping entry is created in the L2P mapping table for a continuous logical page address region. The segment mapping entry includes at least a starting logical address, a starting physical address, the length value of the continuous logical page, and a mode flag. Based on the segment mapping entry, the data to be written is written to the physical page address allocated starting from the starting physical address, and only the single segment mapping entry in the L2P mapping table is updated to complete the mapping relationship of the continuous logical page address region. When a data read instruction for the continuous logical page address region is received, the L2P mapping table is searched according to the target logical address to locate the segment mapping entry containing the target logical address. Based on the starting logical address and starting physical address in the located segment mapping entry, the target physical address corresponding to the target logical address is calculated using an offset, and a data read operation is performed according to the target physical address.

[0051] Thus, this application adopts an adaptive triggering segmented mapping mode for scenarios involving writing contiguous logical address data. By covering the entire contiguous logical page area with a single mapping entry, it replaces the traditional method of creating mapping entries page by page, significantly reducing the number of entries and update frequency of the L2P mapping table, and lowering the storage space occupied by the mapping table and the mapping update overhead during data writing. At the same time, the target physical address is quickly located through offset calculation during the reading phase, eliminating the need for page-by-page traversal and improving data reading efficiency. This adaptive mapping strategy balances the efficiency of contiguous address scenarios with the compatibility of non-contiguous address scenarios, effectively optimizing the read and write performance, storage resource utilization, and energy consumption of flash storage. It avoids the entry redundancy, cumbersome operation, and performance bottleneck problems of traditional mapping methods in continuous data processing, and adapts to the application requirements of high-throughput, large-capacity flash storage. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0053] Figure 1 This is a flowchart illustrating the adaptive mapping flash memory control method in some embodiments of this application;

[0054] Figure 2 This is a schematic diagram of a partial mapping process in some embodiments of this application;

[0055] Figure 3 This is a flowchart illustrating step S300 of the adaptive mapping flash memory control method in some embodiments of this application;

[0056] Figure 4 This is a schematic diagram of the hardware structure of the flash memory control system in some embodiments of this application.

[0057] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0058] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0059] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0060] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the term "and / or" throughout the text includes three solutions; taking A and / or B as an example, it includes technical solution A, technical solution B, and a technical solution that simultaneously satisfies A and B. Furthermore, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of a person skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0061] In flash memory control systems (such as eMMC, UFS, SSD), the FTL (Flash Translation Layer) is responsible for maintaining the mapping relationship between logical addresses (LBA) and physical addresses (PBA), i.e., the L2P (Logical to Physical) mapping table. In current mainstream implementations, each 4KB logical page (or sector) has an independent mapping record in the L2P table. However, in practical applications, a large number of write operations are often consecutive logical address blocks (such as file writing, system updates), which leads to the need to update multiple L2P entries continuously. This update method brings the following problems: (1) Frequent L2P updates and performance degradation: Each 4K data block needs to be written and the L2P table entry needs to be updated, increasing the controller's write latency. (2) High SRAM resource consumption: The L2P table cache (SRAM) needs to store all mapping relationships, occupying a large amount of on-chip memory resources. (3) Heavy read load: When reading consecutive logical pages, the controller needs to access the L2P table multiple times to obtain the physical page address corresponding to each 4K.

[0062] To address the aforementioned technical problems, this application provides an adaptive mapping flash memory control method. The following description uses a flash memory control system executing this adaptive mapping flash memory control method as an example. It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order. Please refer to the appendix. Figure 1 The method includes the following steps S100-S600:

[0063] Step S100: Receive a data write instruction and parse the data write instruction to obtain the logical address sequence corresponding to the data to be written;

[0064] The data write command can originate from a storage request from a host device (such as a server or terminal device). This command carries the data to be written and the corresponding storage control information, and can be received and parsed according to the communication protocol of the flash storage system (such as NVMe protocol or SATA protocol). The logical address sequence is a set of location identifiers of the data to be written in the logical address space. Each logical address corresponds to a data segment (such as logical page data) of the data to be written, and its sequence arrangement directly reflects the address distribution characteristics (continuous or discrete) of the data to be written.

[0065] The receiving of data write commands can be accomplished through the communication interface of the flash memory controller. The parsing process is executed by the command parsing module built into the controller, the core of which is to extract the logical address sequence and auxiliary information such as the length and priority of the data to be written.

[0066] For example, when the host sends a batch file write request, the parsed logical address sequence can be presented as a continuous address segment (such as logical page address 0x0000-0x00FF) or a discrete address set. This sequence will serve as the basis for subsequent determination of whether to trigger the segmented mapping mode, providing basic address data support for the execution of the adaptive mapping strategy, and ensuring the accuracy and rationality of subsequent mapping mode selection and data storage operations.

[0067] Step S200: If the logical address sequence is a continuous logical address and the number of consecutive addresses reaches a preset threshold, trigger the segment mapping mode.

[0068] The preset threshold is a baseline value for the number of consecutive logical addresses used to determine whether to trigger the segmented mapping mode. It can be pre-configured based on the hardware performance of the flash storage system (such as controller processing power and storage medium read / write speed) and application scenario requirements. For example, the initial preset threshold can be set to 2 pages, 3 pages, 4 pages, or N pages (N is a natural number greater than or equal to 2, with 4KB as a logical page); that is, when the number of consecutive logical addresses obtained after parsing is ≥ N pages, the segmented mapping mode is triggered to reduce the operation overhead of page-by-page mapping and improve mapping efficiency.

[0069] It should be noted that the preset threshold can also be adaptively adjusted according to the real-time operating load status of the flash controller and the needs of business scenarios, so as to achieve a dynamic balance between segment mapping mode and page mapping mode, taking into account both flash read and write performance and resource utilization efficiency.

[0070] In one embodiment, the adaptive mapping flash memory control method of this application further includes: real-time monitoring of the CPU utilization rate, physical page allocation time, and mapping table update bandwidth of the flash memory controller; if the CPU utilization rate is higher than a first preset load threshold, the physical page allocation time exceeds a preset duration threshold, or the mapping table update bandwidth reaches its upper limit, then the preset threshold is reduced to decrease the triggering difficulty of the segment mapping mode; if the CPU utilization rate is lower than a second preset load threshold, the physical page allocation time is less than a preset duration threshold, and there is redundancy in the mapping table update bandwidth, then the preset threshold is increased to increase the triggering difficulty of the segment mapping mode.

[0071] It is understood that in this embodiment, when any of the following occurs: the CPU utilization rate of the flash controller is higher than the first preset load threshold (e.g., set to 70%, which can be preset according to the controller hardware specifications), the physical page allocation time exceeds the preset time threshold (e.g., 5ms, adapted to the read and write characteristics of different flash chips), or the mapping table update bandwidth reaches the upper limit, it indicates that the current controller is in a high-load operation state. The fine-grained management brought by the page mapping mode has led to excessive resource consumption. At this time, the preset threshold is reduced (e.g., from 4 consecutive pages to 2 consecutive pages) to reduce the triggering difficulty of the segment mapping mode, making it easier for the controller to enter the segment mapping mode. By reducing the number of mapping table entries through segment-based mapping management, the CPU operation pressure is reduced, the physical page allocation time is shortened, and the mapping table update frequency is reduced, thereby alleviating the high load pressure and ensuring the smoothness of flash read and write. When the following three conditions are met simultaneously: CPU utilization is below the second preset load threshold (e.g., set to 30%, below the first preset load threshold to avoid threshold oscillation), physical page allocation time is less than the preset duration threshold, and mapping table update bandwidth is redundant (e.g., actual bandwidth usage is less than 50% of the maximum bandwidth), it indicates that the current controller resources are sufficient and the conditions for adopting the page mapping mode are met. At this time, the preset threshold is increased (e.g., from 2 consecutive pages to 4 consecutive pages) to increase the triggering difficulty of the segment mapping mode, making the controller more inclined to adopt the page mapping mode. Through fine-grained page-level mapping management, the accuracy of data reading and writing is improved, storage fragmentation that may be caused by segment mapping is reduced, and flash storage utilization is optimized.

[0072] Thus, this embodiment of the application monitors the operating indicators of the flash memory controller in real time and dynamically adjusts the preset threshold based on the load status to achieve adaptive switching between segment mapping and page mapping modes. This can alleviate resource pressure through segment mapping under high load and ensure storage performance through page mapping under low load, effectively balancing the efficiency and accuracy of flash memory control and improving the versatility and adaptability of the adaptive mapping flash memory control method.

[0073] Step S300: In the segmented mapping mode, a single segmented mapping entry is created in the L2P mapping table for a continuous logical page address region to complete the mapping relationship of the continuous logical page address region. The segmented mapping entry includes at least the starting logical address, the starting physical address, the length value of the continuous logical page, and the mode flag bit.

[0074] Segmented mapping is an efficient storage address mapping mode suitable for scenarios requiring batch management of contiguous logical addresses. The L2P mapping table (Logical Address to Physical Address Mapping Table) is a data structure that implements the conversion between logical and physical addresses. A contiguous logical page address region refers to a group of logical pages arranged consecutively in the logical address space, and its range can be flexibly defined according to the address allocation rules of the actual business. A segmented mapping entry serves as the record unit corresponding to the segmented mapping mode in the L2P mapping table. The starting logical address identifies the starting position of the contiguous logical page region, the starting physical address is used to associate it with the starting position of the corresponding physical storage region, the length value of the contiguous logical pages defines the total number of logical pages covered by the mapping segment, and the mode flag explicitly identifies the entry as a segmented mapping type (distinguishing it from other mapping types such as paged mapping).

[0075] For example, a segmented mapping entry is created by selecting 5000 consecutive logical pages from logical addresses LBA1000 to LBA5999. This entry includes the starting logical address LBA1000, the starting physical address PBA5000, the length value 5000, and the flag bit "1" (representing segmented mapping). This provides concise and efficient mapping data support for subsequent address translation, ensuring the execution efficiency and accuracy of address translation operations.

[0076] It is understandable that segmented mapping entries may also include information such as the timestamp of the data writing request.

[0077] Step S400: According to the segment mapping entry, write the data to be written to the physical page address allocated starting from the starting physical address;

[0078] The segmented mapping entry is a mapping record established in the L2P mapping table in step S300. It contains information such as the starting logical address, starting physical address, continuous logical page length value, and mode flag, which clearly defines the logical address range, physical storage start position, and mapping type corresponding to the data to be written, providing a complete address mapping basis for data writing. The data to be written is the business data to be stored in the storage medium, and its corresponding logical address belongs to the coverage range of the aforementioned continuous logical page address area. The physical page address allocated starting from the starting physical address refers to a group of physical page storage locations continuously allocated from the starting physical address in the segmented mapping entry according to the number of physical pages defined by the continuous logical page length value. This physical page area corresponds one-to-one with the continuous logical page address area, ensuring the address continuity and mapping consistency of data writing.

[0079] For example, if a segmented mapping entry contains a starting logical address LBA1000, a starting physical address PBA5000, and a length value of 5000 (corresponding to 5000 consecutive logical pages), then the data to be written will be sequentially written to the 5000 consecutive physical page addresses starting from PBA5000. This achieves a one-to-one correspondence between logical addresses LBA1000~LBA5999 and physical addresses PBA5000~PBA9999, thereby providing continuous and complete storage data support for subsequent address translation and data reading, ensuring the execution efficiency and accuracy of storage operations.

[0080] In a specific application scenario, such as Figure 2 As shown, when the host sends a bulk write request containing consecutive logical addresses LBA1000 to LBAn to the FTL, the FTL first receives the request and the corresponding data, and synchronously completes the following operations:

[0081] Mapping update branch: FTL triggers the "update segmented L2P mapping" process, identifies the number of consecutive LBAs as LBAn - LBA1000 + 1 (satisfying the condition N ≥ 2), and then generates a segmented mapping entry in the L2P mapping table, which includes the starting logical address LBA1000, the starting physical address PBA5000, the length value LBAn - LBA1000 + 1, and the mode flag bit Flag = 1 (identifying it as segmented mapping).

[0082] Data write branch: According to the segmented mapping entry, FTL writes the data to be written sequentially to the consecutive physical page addresses LBAn - LBA1000 + 1 starting from PBA5000, realizing a one-to-one correspondence between logical addresses LBA1000~LBAn and physical addresses PBA5000~PBA5000 + (LBAn - LBA1000).

[0083] Step S500: When a data read instruction for the continuous logical page address region is received, the L2P mapping table is searched according to the target logical address to locate the segment mapping entry containing the target logical address.

[0084] Among them, the data read instruction is an operation instruction issued by the upper-layer application or storage controller to read data at a specified logical address. It carries key information such as the target logical address and the read length.

[0085] For example, when a read instruction is received to read the target logical address LBA1000~LBA1200, the system traverses the L2P mapping table and matches the target segment mapping entry (the segment mapping recorded and established above) with the logical address segment starting at LBA1000 and a segment length of 5000, thus completing the precise location of the target logical address and providing an accurate mapping basis for subsequent physical address conversion and data reading operations.

[0086] Step S600: Based on the starting logical address and starting physical address in the located segment mapping entry, calculate the target physical address corresponding to the target logical address using the offset, and perform a data reading operation according to the target physical address.

[0087] The offset is the difference between the target logical address and the starting logical address of the segment mapping entry, i.e., offset = target logical address - segment starting logical address. It is a key calculation parameter for achieving accurate address translation. The target physical address is the physical unit address of the actual stored data in the storage system. It is calculated by target physical address = segment starting physical address + offset. It is the final addressing basis for data read operations. The data read operation is the execution action of reading the corresponding data from physical storage media such as flash memory and disk based on the target physical address. Its execution efficiency directly affects the overall read and write performance of the storage system.

[0088] For example, if the starting logical address of the located segment mapping entry is LBA1000, the starting physical address is PBA2000, and the target logical address is LBA1050, then the offset is 1050 − 1000 = 50, and the target physical address is PBA2000 + 50 = PBA2050. Based on this, the system performs data reading from the physical storage unit corresponding to PBA2050, thereby achieving efficient conversion from logical address to physical address and accurate data reading, ensuring the reliability and low latency of data access in the storage system.

[0089] Thus, this application adopts an adaptive triggering segmented mapping mode for scenarios involving writing contiguous logical address data. By covering the entire contiguous logical page area with a single mapping entry, it replaces the traditional method of creating mapping entries page by page, significantly reducing the number of entries and update frequency of the L2P mapping table, and lowering the storage space occupied by the mapping table and the mapping update overhead during data writing. At the same time, the target physical address is quickly located through offset calculation during the reading phase, eliminating the need for page-by-page traversal and improving data reading efficiency. This adaptive mapping strategy balances the efficiency of contiguous address scenarios with the compatibility of non-contiguous address scenarios, effectively optimizing the read and write performance, storage resource utilization, and energy consumption of flash storage. It avoids the entry redundancy, cumbersome operation, and performance bottleneck problems of traditional mapping methods in continuous data processing, and adapts to the application requirements of high-throughput, large-capacity flash storage.

[0090] In one embodiment, before triggering the segment mapping mode, the method further includes: maintaining an allocation state diagram of a physical contiguous space pool in the system area of ​​the flash memory; when the segment mapping mode is triggered, preferentially allocating free blocks with matching lengths and contiguous physical addresses from the physical contiguous space pool for the segment mapping entry; if the contiguous length requirement cannot be met in the physical contiguous space pool, the data to be written is split into multiple sub-segments, and the maximum possible contiguous physical space is allocated to each sub-segment in the physical contiguous space pool, an independent segment mapping entry is created for each sub-segment, and all entries are logically marked as belonging to the same logical segment sequence.

[0091] Specifically, in this embodiment, an allocation state diagram of a physically contiguous space pool is first maintained in the system area of ​​the flash memory. This state diagram records information such as the physical address, block length, allocation status, and contiguousness of each free block in the physically contiguous space pool. It can be implemented using bitmaps, linked lists, or index tables, supporting fast querying and updating, and providing real-time and accurate status information for physical space allocation in segmented mapping mode. When segmented mapping mode is triggered, free blocks with matching lengths and contiguous physical addresses are preferentially allocated from the physically contiguous space pool for the segmented mapping entry. That is, based on the logical length of the data to be written, free blocks with contiguous physical addresses and lengths not less than the logical length are retrieved and matched in the allocation state diagram. After allocation, the allocation state diagram is updated, thereby ensuring the contiguousness of the physical space corresponding to the segmented mapping entry and improving the efficiency of subsequent address translation and data read / write. If the physical contiguous space pool cannot meet the continuous length requirement (i.e., there is no continuous free block with matching length), the data to be written is split into multiple sub-segments. The splitting granularity can be flexibly set according to the maximum available continuous block length of the physical contiguous space pool. Then, the maximum possible continuous physical space is allocated to each sub-segment in the physical contiguous space pool. That is, for each sub-segment, the largest continuous free block is searched and allocated in the allocation state diagram to ensure the continuity of the physical space of a single sub-segment as much as possible. Next, an independent segment mapping entry is created for each sub-segment. Each entry records the mapping information such as the starting logical address, segment length, and starting physical address of the corresponding sub-segment. Finally, all entries are logically marked to belong to the same logical segment sequence. For example, by adding a logical segment sequence ID field to the segment mapping entry, multiple sub-segment entries split from the same data to be written are associated to ensure that the mapping relationship of the entire logical segment can be completely restored during subsequent address lookup and data reading.

[0092] Thus, by maintaining the allocation state diagram of the physical contiguous space pool, this embodiment of the application prioritizes the allocation of contiguous physical space. When space is insufficient, it adopts the method of segment splitting and sequence marking, which not only makes full use of the physical contiguous space of flash memory to improve the efficiency of segment mapping, but also ensures the continuity and integrity of data writing when contiguous space is insufficient, thereby optimizing the space utilization and read / write performance of the storage system.

[0093] In one embodiment, such as Figure 3 As shown, step S300: Create a single segmented mapping entry for consecutive logical page address regions in the L2P mapping table, including:

[0094] S310. Obtain the historical wear parameters of the free physical page corresponding to the candidate starting physical address;

[0095] S320. Based on the historical wear parameters, determine whether the continuous physical page allocation scheme starting from the candidate starting physical address meets the preset wear leveling conditions.

[0096] S330. If the conditions are met, the segment mapping entry is created using the candidate starting physical address as the starting physical address.

[0097] S340. If it does not meet the requirements, a new candidate starting physical address is selected as the starting physical address, and the above acquisition and judgment steps are repeated until a physical address allocation scheme that meets the wear leveling conditions is found.

[0098] Specifically, in this embodiment, the historical wear parameters of the free physical pages corresponding to the candidate starting physical address are first obtained. These historical wear parameters may include the number of erases, writes, remaining lifetime percentage, and error bit rate of the physical page, characterizing the wear level and health status of the physical page. They can be collected and recorded in real time by the wear statistics module built into the storage system, providing a quantitative basis for wear leveling judgment. Subsequently, based on the historical wear parameters, it is determined whether the allocation scheme of consecutive physical pages starting from the candidate starting physical address meets preset wear leveling conditions. These wear leveling conditions can be flexibly set according to the wear leveling strategy of the storage system. For example, they may require that the average number of erases of consecutive physical pages does not exceed a preset threshold of the system's global average number of erases, or that the difference in the number of erases of each physical page does not exceed a preset range, or that physical pages with lower wear levels are preferentially selected. By statistically analyzing the historical wear parameters of the candidate consecutive physical pages (such as calculating the average, variance, and extreme values), it is determined whether they meet the wear leveling requirements, thereby avoiding excessive wear of local physical pages and extending the overall lifespan of the flash memory. If the conditions are met, the candidate starting physical address is used as the starting physical address to create the segmented mapping entry. This entry records key mapping information such as the starting logical address, segment length, and candidate starting physical address of the continuous logical page address region, realizing batch mapping from continuous logical addresses to continuous physical addresses and improving address translation efficiency. If the conditions are not met, a new candidate starting physical address is selected as the starting physical address. During the reselection, the free physical page space can be traversed according to the wear leveling strategy (such as prioritizing physical pages with fewer erase cycles and longer remaining lifespans), and the steps of obtaining historical wear parameters and judging wear leveling conditions are repeated until a physical address allocation scheme that meets the wear leveling conditions is found, ensuring that the continuous physical pages corresponding to the segmented mapping entry achieve wear leveling allocation while satisfying address continuity.

[0099] It should be noted that the candidate starting physical address can be a physical address initially selected by the storage system from the free physical page space according to preset rules, which can serve as the starting point for the allocation of consecutive physical pages. The selection method can be flexibly set according to the storage system's space management strategy. For example, priority can be given to selecting the starting address of a free block with consecutive physical addresses and a length not less than the length of the logical segment to be allocated. Alternatively, the free physical page list or bitmap can be traversed according to wear leveling priority (e.g., fewer erase cycles, higher remaining lifetime), and physical addresses that meet the consecutive length requirement can be selected as candidate starting physical addresses in turn. Furthermore, candidate starting physical addresses can also be filtered in conjunction with physical block boundary alignment requirements (e.g., alignment according to flash block or superblock boundaries). The historical wear parameters of the free physical pages corresponding to the candidate starting physical address can refer to the historical wear parameters of a preset number of free physical pages after the candidate starting physical address. The consecutive physical page allocation scheme refers to the actual physical address allocation scheme obtained by starting physical address allocation from the candidate starting physical address.

[0100] In specific application scenarios, the preset wear leveling conditions may include at least one or more combinations of the following. To more clearly illustrate the practical application logic of these conditions, examples are provided below, using flash memory storage as an example:

[0101] First, there is no consecutive preset number of physical pages whose corresponding wear levels are all greater than or equal to the first wear threshold. This is to prevent local consecutive physical pages from forming a "wear concentration zone" due to excessive wear, which would cause the physical pages in that area to fail prematurely. For example, the preset number of consecutive pages is set to 5, and the first wear threshold corresponds to 8000 erase cycles (assuming that the maximum number of erase cycles for a flash physical page is 10000, and more than 8000 cycles are considered a high wear state). If, within a contiguous group of physical pages corresponding to a candidate starting physical address, five consecutive pages have erase counts of 8200, 8300, 8100, 8400, and 8250 respectively, all exceeding the first wear threshold of 8000 erases, then the allocation scheme does not meet this condition, and a new candidate starting physical address must be selected. Conversely, if the distribution of high-wear pages (≥8000 erases) within a contiguous group of physical pages does not meet the "five consecutive pages" condition—for example, if only a single page has 8100 erases while the remaining consecutive pages have fewer than 8000 erases—then this wear leveling requirement is met, and the process can proceed to subsequent verification stages. This condition effectively prevents localized areas of physical pages from rapidly exhausting their lifespan due to concentrated allocation, thus avoiding localized failures in the storage system.

[0102] Secondly, the average wear level of this group of consecutive physical pages is less than or equal to the second wear threshold. By controlling the overall wear level, the allocation scheme is ensured to match the global wear state of the system, avoiding excessive wear differences between a single group of consecutive physical pages and other areas. For example, the second wear threshold is set to correspond to 6000 erase cycles, and the average number of erase cycles for all physical pages in the system is 5500. If the number of erases for the 10 consecutive physical pages corresponding to the candidate starting physical address is 5200, 5800, 6100, 5700, 5900, 6000, 5600, 5850, 5950, and 5750 respectively, the average value is (5200+5800+6100+5700+5900+6000+5600+5850+5950+5750)÷10=5805 times, which is less than the second wear threshold of 6000 times. This indicates that the overall wear level of this group of physical pages is compatible with the global state of the system and meets this condition. If the average number of erases for the other group of 10 consecutive physical pages is 6200 times, which exceeds the threshold of 6000 times, then this scheme does not meet the requirements and needs to be re-selected. This condition ensures that the wear rate of physical pages in each region tends to be consistent, avoiding excessive wear in some areas and idle waste in others, thus maximizing the overall lifespan of the flash memory medium.

[0103] Thus, by introducing historical wear parameters and wear leveling condition judgment when creating segmented mapping entries, this embodiment of the application achieves balanced wear of physical pages while ensuring that continuous logical addresses correspond to continuous physical addresses to improve mapping efficiency. This avoids premature failure of local physical pages, thereby extending the service life of flash memory storage media and improving the reliability and stability of the storage system.

[0104] In one embodiment, when performing a data read operation based on the segmented mapping entry, the method further includes:

[0105] If the amount of data to be read exceeds one logical page, the pre-read range is determined based on the length information in the segmented mapping entry and the current free space in the cache, and the subsequent consecutive physical page data, including the target physical address, is pre-read into the cache.

[0106] The pre-read range does not exceed the total length of the continuous physical pages corresponding to the segmented mapping entries, and the storage occupancy of the pre-read data does not exceed a preset proportion of the cache free space.

[0107] Specifically, in this embodiment, during the data reading operation based on segmented mapping entries, it is first determined whether the amount of data to be read exceeds the size of a logical page. If the amount of data to be read does not exceed one logical page, the data reading can be completed directly according to the normal reading process; if the amount of data to be read exceeds one logical page, a pre-reading process is entered to improve the efficiency of subsequent data access.

[0108] Subsequently, based on the length information recorded in the segment mapping entry (i.e., the total length of the continuous physical pages corresponding to the segment mapping entry) and the actual free space size of the current cache, a reasonable pre-read range is determined. The pre-read range must meet two key constraints: first, the pre-read range cannot exceed the total length of the continuous physical pages corresponding to the segment mapping entry to avoid reading invalid or non-segment mapping physical page data, ensuring the validity and accuracy of data reading; second, the storage space required for the pre-read data cannot exceed a preset proportion of the current cache free space (e.g., the preset proportion can be set to 50%, 80%, etc., and can be flexibly configured according to system performance requirements), to prevent cache overflow, impact on other data read / write operations, or reduced overall cache utilization due to excessive cache space occupied by pre-read data.

[0109] Next, according to the predetermined prefetch range, the subsequent consecutive physical page data, including the target physical address, is prefetched from the storage medium (such as flash memory, disk, etc.) into the cache. Through this prefetch operation, when these consecutive physical page data that have been prefetched into the cache are needed later, they can be read directly from the cache quickly without having to access the underlying storage medium again. This effectively reduces the number of storage I / O operations, lowers data read latency, and improves the overall efficiency of data reading and system response speed.

[0110] In specific application scenarios, a layered and adaptive pre-read strategy can be adopted to further optimize the balance between pre-read efficiency and cache resources. The specific implementation is as follows: First, based on the number of remaining consecutive physical pages corresponding to the segmented mapping entries, determine the maximum upper limit of the current pre-read range (i.e., the storage scale corresponding to the total number of remaining consecutive physical pages); then, determine the relationship between the current cache free space ratio and the preset cache threshold: if the cache free space ratio is higher than the preset cache threshold, it indicates that the cache resources are sufficient. At this time, perform a full pre-read operation according to the above maximum upper limit, read all the remaining consecutive physical page data into the cache at once, and maximize the response speed of subsequent consecutive data access; if the cache free space ratio is lower than the preset cache threshold, in order to avoid cache resource exhaustion, perform a segmented pre-read operation according to a preset step size, write the consecutive physical page data into the cache segment by segment. By loading in batches, while ensuring the pre-read effect, the pre-read efficiency and cache resource consumption are balanced, ensuring the stability of the overall read and write performance of the system.

[0111] Thus, in this embodiment of the application, when performing data reading operations based on segmented mapping entries, the pre-read range is determined by judging whether the data volume exceeds one logical page and combining the segmented mapping entry length information with the cache free space. This enables the pre-reading of subsequent consecutive physical page data, ensuring the effectiveness of the pre-reading operation and the reasonable use of cache space, while also significantly improving data reading efficiency and optimizing system storage access performance.

[0112] In one embodiment, the adaptive mapping flash memory control method of this application further includes: monitoring whether subsequent write operations target a continuous logical address region of an established segmented mapping entry; if the subsequent write operation only covers part of the logical address in the region, according to the position of the covered region in the original continuous logical address region, splitting the original segmented mapping entry into at least two new mapping entries, corresponding to the unupdated continuous logical address sub-region and the updated logical address region, respectively.

[0113] Specifically, in this embodiment, the adaptive mapping flash memory control flow first monitors in real time the logical address range pointed to by subsequent write operations, and determines whether the logical address range falls within the continuous logical address region of the established segment mapping entries. The monitoring process can be completed quickly by traversing the segment mapping table in the flash memory controller and comparing the logical address range of the write operation with the logical address range of each existing segment mapping entry.

[0114] Subsequently, differentiated processing is performed based on the monitoring results: if subsequent write operations cover the entire range of the continuous logical address region, the physical address association corresponding to the original segmented mapping entry is directly updated without splitting the entry; if the write operation only covers part of the logical address within the region (i.e., a partial update scenario), the segmented mapping entry splitting process is initiated based on the specific location of the covered region within the original continuous logical address region. During splitting, the original single continuous segmented mapping entry is split into at least two independent new mapping entries based on the logical address boundary of the covered region, ensuring that the logical address regions corresponding to each entry remain continuous after splitting (if the updated region is a non-continuous single segment, it can be a separate mapping entry; if it is a continuous sub-region, it forms a continuous sub-region mapping entry with the unupdated region).

[0115] Next, the at least two new mapping entries after the split each undertake different association functions: one new mapping entry corresponds to the unupdated contiguous logical address sub-regions in the original region, maintaining the mapping relationship between this sub-region and the original physical address region, ensuring the continuity and accuracy of access to unupdated data; the other new mapping entry corresponds to the logical address region overwritten by the write operation, associating it with the newly allocated physical address region (due to the characteristics of flash memory, the original physical address data is usually not directly overwritten, but the mapping is updated after writing to a new physical block), achieving accurate address association of the updated data. This splitting method avoids the failure of the original contiguous segment mapping due to partial updates, eliminating the need to decompose the entire original entry into finer-grained page-based mappings, thus balancing mapping efficiency and update flexibility.

[0116] In specific application scenarios, the splitting strategy can be optimized by combining logical address distribution characteristics and write data volume to further improve flash memory mapping and read / write performance. The specific implementation is as follows: First, obtain the logical address length, starting offset, and total length of the original segmented mapping entry for the covered area to determine the logical address interval boundaries of each new mapping entry after splitting, ensuring no address overlap or omission. If the covered area is the head or tail of the original continuous logical address area, split the original entry into two new mapping entries, corresponding to the updated head / tail area and the remaining unupdated continuous sub-area, respectively. If the covered area is located in the middle of the original continuous logical address area, split it into three new mapping entries, corresponding to the updated middle area and the unupdated continuous sub-areas on both sides, respectively. Simultaneously, the segmented mapping table is updated synchronously after splitting, the original segmented mapping entry is deleted, and the logical address range, physical address association information, and length parameters of the new mapping entries are entered. This ensures that the flash controller can quickly locate the address through the new entries, maintaining the efficiency of segmented mapping while ensuring some update functions, and avoiding access delays caused by mapping table redundancy.

[0117] Thus, by monitoring the write operation range and splitting segmented mapping entries as needed, this embodiment of the application can adapt to some logical address update scenarios, ensuring the accuracy and continuity of address mapping while avoiding the performance loss caused by full mapping updates or fine-grained mapping, thereby improving the flexibility and overall read / write efficiency of the adaptive mapping flash memory control method.

[0118] In one embodiment, after splitting the original segmented mapping entry into at least two new mapping entries, the method further includes: determining the length of the unupdated continuous logical address sub-regions; if the length of the sub-region is less than a preset length threshold, converting it from segmented mapping mode to page mapping mode; if the length of the sub-region is not less than the preset length threshold, maintaining the segmented mapping mode; for the updated logical address region, adaptively selecting either segmented mapping mode or page mapping mode to establish corresponding mapping entries based on the logical address continuity corresponding to subsequent write operations; marking the original segmented mapping entry as invalid, and synchronously updating the L2P mapping table to complete the update of the mapping relationship after splitting.

[0119] Specifically, after splitting the original segmented mapping entries into new mapping entries corresponding to unupdated sub-regions and updated regions, a length determination operation is first performed on the unupdated contiguous logical address sub-regions. The core purpose is to adapt the optimal mapping mode based on the sub-region length, balancing mapping efficiency and storage resource consumption. The length determination can be achieved by reading the span of the logical address interval corresponding to the split sub-region and comparing it with a preset length threshold. The preset length threshold can be flexibly configured according to the flash memory storage architecture, read / write performance requirements, and mapping table storage capacity (e.g., set to 8 logical page lengths, 16 logical page lengths, etc., to adapt to the mapping granularity requirements in different scenarios).

[0120] Subsequently, based on the judgment result, differentiated processing of the mapping mode is performed: if the length of the unupdated sub-region is less than the preset length threshold, it means that the logical address span of the sub-region is small, and continuing to use the segment mapping mode will not be able to give full play to the efficiency advantage of batch mapping. On the contrary, it may increase the time consumption of mapping table query due to entry redundancy. At this time, it is converted from the segment mapping mode to the page mapping mode, and the mapping relationship between logical address and physical address is established on a single page basis to ensure the accuracy of access to small-granular sub-regions; if the length of the sub-region is not less than the preset length threshold, it means that it still has the advantage of continuous address span. The segment mapping mode is kept unchanged to maintain the efficiency of batch address mapping and avoid the performance loss caused by mode conversion.

[0121] Next, for the updated logical address region, a new mapping entry is established by adaptively selecting a mapping mode based on the logical address continuity corresponding to subsequent write operations. Specifically, if the logical addresses of subsequent write operations are continuously distributed, and the span of the continuous addresses meets the activation conditions of the segment mapping mode (such as not less than the aforementioned preset length threshold), then the segment mapping mode is used to establish the mapping entry, associating the continuously updated region with the newly allocated continuous physical address region, thereby improving subsequent read and write efficiency. If the logical addresses of subsequent write operations are discretely distributed, or the span of the continuous addresses is less than the activation conditions of the segment mapping mode, then the page mapping mode is used, establishing mappings at the single-page granularity to adapt to the flexibility requirements of discrete write scenarios. This adaptive selection process can ensure that the mapping mode accurately matches the actual write scenario by monitoring the logical address sequence of subsequent write operations in real time and analyzing address continuity and span.

[0122] Finally, the original entry invalidation and mapping table update operations are performed: First, the original segmented mapping entries are marked as invalid by setting an invalid flag bit in the mapping table (e.g., setting the entry status bit to "0" to indicate invalid and "1" to indicate valid). This prevents the invalid entry from being mistakenly called during subsequent address mapping queries, ensuring the accuracy of the mapping relationship. Then, the L2P mapping table is updated synchronously, deleting the relevant records of the original segmented mapping entries and entering the information of each new mapping entry after splitting (including logical address range, physical address association, mapping mode type, length parameters, etc.), ensuring that the L2P mapping table is consistent with the current actual mapping relationship. Simultaneously, a mapping table cache refresh operation can be triggered to synchronize the updated mapping relationship to the flash controller's cache, reducing access latency during subsequent address queries and ensuring the stability and efficiency of the entire mapping system.

[0123] In specific application scenarios, mode conversion and mapping table updates can be further optimized to improve performance. For example, when converting an unupdated sub-region from segment mapping to page mapping, page mapping entries for the corresponding logical pages can be generated in batches, avoiding the time-consuming process of creating each page individually. When selecting a mapping mode for the updated region, a threshold for the span of consecutive addresses can be preset. If subsequent writes of consecutive addresses reach this threshold, the system will automatically switch to segment mapping; otherwise, it will maintain page mapping. When updating the L2P mapping table, an incremental update method can be used, modifying only the records corresponding to the original entries and the newly added entries, reducing the resource consumption of a full table update. In addition, original segment mapping entries marked as invalid can be included in the subsequent mapping table garbage collection mechanism and cleaned up during idle periods to free up mapping table storage space.

[0124] Thus, by splitting the data and adapting different mapping modes to different regions, invalidating original entries, and synchronously updating the L2P mapping table, this embodiment of the application not only ensures the accuracy and adaptability of the mapping relationship, but also takes into account the read and write efficiency and resource consumption in different scenarios, further optimizing the overall performance of the adaptive mapping flash memory control method.

[0125] In one embodiment, the adaptive mapping flash memory control method of this application further includes: associating a hotness counter with each segment mapping entry in the L2P mapping table; incrementing the corresponding hotness counter when a read or write access occurs to the logical address range covered by the segment mapping entry; periodically sorting the segment mapping entries according to the hotness counter; migrating the top N segment mapping entries with the highest hotness and all the physical page data mapped by them as a whole to a flash memory medium area with better read / write performance or lower latency; and updating the mapping entries after migration.

[0126] Specifically, in this embodiment, firstly, in the L2P (Logical Address to Physical Address) mapping table, a separate hotspot counter is associated with each established segmented mapping entry. This counter is used to quantify the access frequency of the logical address region covered by the corresponding segmented mapping entry, providing data support for the formulation of subsequent data migration strategies. The hotspot counter can be in integer form, with an initial value set to 0. Its counting information, along with the logical address range and physical address association information of the corresponding segmented mapping entry, is synchronously stored in the L2P mapping table for easy association and updating during access.

[0127] Subsequently, a heat index update mechanism was established: when a read or write operation occurs on the logical address range covered by a certain segmented mapping entry, the corresponding heat index counter is immediately incremented. The increment step can be flexibly configured according to actual needs (e.g., incrementing by 1 for each access, or incrementing by 2 for write operations and by 1 for read operations, to distinguish the weight of different access types). Through real-time incrementing counts, the access heat changes of each segmented mapping region can be accurately captured, ensuring that the heat index data can truly reflect the region access frequency, providing a reliable basis for subsequent sorting and migration.

[0128] Next, periodic sorting and data migration operations are performed: First, a fixed periodic time is set (e.g., 10 seconds, 1 minute, etc., which can be dynamically adjusted according to the performance requirements and access characteristics of the flash memory system). Within each period, based on the heat counter value corresponding to each segment mapping entry, all valid segment mapping entries are sorted in descending order, and the top N segment mapping entries with the highest heat are selected (N is a preset positive integer, which can be configured according to the storage capacity of the better-performing flash memory area and the system read / write load, such as N=5, N=10, etc.). Then, these top N segment mapping entries and all the physical page data they map are migrated as a whole from the current storage area to an area in the flash memory medium with better read / write performance or lower latency (e.g., the SLC level area of ​​flash memory, which has faster read / write speeds and lower latency compared to MLC and TLC level areas; or physical blocks closer to the controller, reducing the data transmission path length). During the migration process, data integrity must be ensured, and a block-level overall migration method is adopted to avoid the efficiency loss caused by page-by-page migration. At the same time, the corresponding segment mapping entries are locked to prevent read / write access conflicts during the migration.

[0129] After data migration is complete, the corresponding segment mapping entries are updated synchronously: in the L2P mapping table, the physical addresses associated with the migrated segment mapping entries are updated to the physical addresses of the new storage areas, maintaining a precise mapping between logical and physical addresses; simultaneously, the corresponding heat counters are reset to their initial value of 0 to restart the next round of heat counting, ensuring the periodicity and accuracy of heat statistics. Furthermore, after migration, the corresponding segment mapping entries are unlocked to restore normal read and write access, ensuring the continuity of system operation.

[0130] In specific application scenarios, sorting and migration strategies can be further optimized to improve system performance. For example, during sorting, if multiple segmented mapping entries have the same heat counter value, the entry with smaller data volume can be prioritized for migration, reducing migration time. For flash memory areas with better performance, a storage capacity limit can be preset. If the total data volume of the top N hottest entries exceeds this limit, entries with a total data volume not exceeding the limit are selected for migration in descending order of heat, avoiding storage overflow in that area. Simultaneously, migration operations can be performed during periods of low system load (such as intervals without a large number of read / write requests), reducing the impact of the migration process on normal system read / write performance. Furthermore, a decay mechanism can be added to the heat counter. If an entry has not been accessed for several consecutive periods, its count is gradually reduced, preventing data from occupying high-performance areas for extended periods due to historical high heat, ensuring dynamic optimization of resource allocation.

[0131] Thus, by associating segmented mapping entries with a heat counter, updating access heat in real time, and periodically migrating high-heat data to a high-performance area, this application embodiment can achieve dynamic optimization allocation of flash storage resources, enabling high-frequency access data to obtain faster read and write responses, significantly improving the read and write performance and operating efficiency of the entire flash system, while also taking into account the rational utilization of storage resources.

[0132] like Figure 4 As shown, Figure 4 The diagram below illustrates the hardware structure of a flash memory control system in some embodiments of this application. The flash memory control system provided in this application includes a memory 1000 and a processor 2000. The memory 1000 is used to store computer-readable instructions, and the processor 2000 is used to call the computer-readable instructions to execute the adaptive mapping flash memory control method as described above.

[0133] The processor 2000 provides computing and control capabilities to control the flash memory control system to perform corresponding tasks. For example, it controls the flash memory control system to perform the adaptive mapping flash memory control method in any of the above method embodiments. The method includes: receiving a data write instruction; parsing the data write instruction to obtain a logical address sequence corresponding to the data to be written; triggering a segmented mapping mode when the logical address sequence is a continuous logical address and the number of consecutive addresses reaches a preset threshold; and in the segmented mapping mode, creating a single segmented mapping entry for a continuous logical page address region in the L2P mapping table to complete the establishment of the mapping relationship of the continuous logical page address regions. The segment mapping entry includes at least a starting logical address, a starting physical address, the length of a contiguous logical page, and a mode flag. Based on the segment mapping entry, the data to be written is written to the physical page address allocated starting from the starting physical address. When a data read instruction for the contiguous logical page address region is received, the L2P mapping table is searched based on the target logical address to locate the segment mapping entry containing the target logical address. Based on the starting logical address and starting physical address in the located segment mapping entry, the target physical address corresponding to the target logical address is calculated using an offset, and a data read operation is performed based on the target physical address.

[0134] The processor 2000 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0135] The memory 1000, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the adaptive mapping flash memory control method in the embodiments of this application. The processor 2000 can implement the adaptive mapping flash memory control method in any of the above method embodiments by running the non-transitory software programs, instructions, and modules stored in the memory 1000.

[0136] Specifically, memory 1000 may include volatile memory (VM), such as random access memory (RAM); memory 1000 may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), or other non-transitory solid-state storage devices; memory 1000 may also include combinations of the above types of memory.

[0137] In summary, the flash memory control system of this application adopts the technical solution of any of the above-described adaptive mapping flash memory control method embodiments. Therefore, it has at least the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated here.

[0138] This application also provides a computer-readable storage medium, such as a memory including program code, which can be executed by a processor to implement the adaptive mapping flash memory control method in the above embodiments. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0139] This application also provides a computer program product comprising one or more lines of program code stored in a computer-readable storage medium. A processor reads the program code from the computer-readable storage medium and executes the program code to complete the steps of the adaptive mapping flash memory control method provided in the above embodiments.

[0140] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program or program code related to hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0141] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0142] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software and a general-purpose hardware platform, or of course, using hardware. Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0143] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A method for adaptive mapping of flash memory, the method comprising: The method includes: Receive a data write instruction and parse the data write instruction to obtain the logical address sequence corresponding to the data to be written; When the logical address sequence is a continuous logical address and the number of consecutive addresses reaches a preset threshold, the segmented mapping mode is triggered. In the segmented mapping mode, a single segmented mapping entry is created in the L2P mapping table for consecutive logical page address regions to complete the mapping relationship of the consecutive logical page address regions. The segmented mapping entry includes at least the starting logical address, the starting physical address, the length value of the consecutive logical pages, and the mode flag bit. According to the segment mapping entry, the data to be written is written to the physical page address allocated starting from the starting physical address; When a data read instruction for the continuous logical page address region is received, the L2P mapping table is searched according to the target logical address to locate the segment mapping entry containing the target logical address; Based on the starting logical address and starting physical address in the located segment mapping entry, the target physical address corresponding to the target logical address is calculated using the offset, and a data reading operation is performed based on the target physical address.

2. The method of adaptive-mapped flash control of claim 1, wherein, The method further includes: Real-time monitoring of the flash memory controller's CPU utilization, physical page allocation time, and mapping table update bandwidth; If the CPU utilization rate is higher than the first preset load threshold, the physical page allocation time exceeds the preset duration threshold, or the mapping table update bandwidth reaches the upper limit, then the preset threshold is reduced to reduce the difficulty of triggering the segmented mapping mode. If the CPU utilization rate is lower than the second preset load threshold, the physical page allocation time is less than the preset duration threshold, and there is redundancy in the mapping table update bandwidth, then the preset threshold is increased to increase the difficulty of triggering the segmented mapping mode.

3. The method of adaptive-mapped flash memory control of claim 1, wherein, Prior to the trigger segment mapping mode, it also includes: Maintain an allocation state diagram of a physically contiguous space pool in the system region of flash memory; When the segmented mapping mode is triggered, free blocks with matching lengths and contiguous physical addresses are preferentially allocated from the physical contiguous space pool for the segmented mapping entry; If the continuous length requirement cannot be met in the physical contiguous space pool, the data to be written is split into multiple sub-segments, and the maximum possible continuous physical space is allocated to each sub-segment in the physical contiguous space pool. An independent segment mapping entry is created for each sub-segment, and all entries are logically marked as belonging to the same logical segment sequence.

4. The method of adaptive-mapped flash memory control of claim 1, wherein, Creating a single segmented mapping entry for contiguous logical page address regions in the L2P mapping table includes: Obtain the historical wear parameters of the free physical pages corresponding to the candidate starting physical address; Based on the historical wear parameters, determine whether the continuous physical page allocation scheme starting from the candidate starting physical address meets the preset wear leveling conditions; If the conditions are met, the segmented mapping entry is created using the candidate starting physical address as the starting physical address. If it does not meet the requirements, a new candidate starting physical address is selected as the starting physical address, and the above acquisition and judgment steps are repeated until a physical address allocation scheme that meets the wear leveling conditions is found.

5. The method of adaptive-mapped flash memory control of claim 4, wherein, The preset wear equalization conditions include: There is no consecutive preset number of physical page addresses whose wear levels are all greater than or equal to the first wear threshold; and / or, The average wear value corresponding to consecutive physical page addresses is less than or equal to the second wear threshold.

6. The method of adaptive-mapped flash memory control of claim 1, wherein, When performing a data read operation based on the segmented mapping entry, the method further includes: If the amount of data to be read exceeds one logical page, the pre-read range is determined based on the length information in the segmented mapping entry and the current free space in the cache, and the subsequent consecutive physical page data, including the target physical address, is pre-read into the cache. The pre-read range does not exceed the total length of the continuous physical pages corresponding to the segmented mapping entries, and the storage occupancy of the pre-read data does not exceed a preset proportion of the cache free space.

7. The method of adaptive-mapped flash memory control of claim 6, wherein, The step of determining the pre-read range based on the length information in the segmented mapping entry and the current free cache space includes: Based on the number of remaining consecutive physical pages corresponding to the segmented mapping entry, determine the maximum upper limit of the pre-read range; If the free space ratio of the cache is higher than the preset cache threshold, a full pre-read will be performed at the maximum limit, reading all remaining consecutive physical page data into the cache at once to maximize the response speed of subsequent consecutive reads; If the proportion of free space in the cache is lower than the preset cache threshold, segmented pre-reading is performed according to the preset step size, and continuous physical page data is written to the cache segment by segment to balance pre-reading efficiency and cache resource consumption.

8. The method of adaptive-mapped flash memory control of claim 1, wherein, The method further includes: Monitor whether subsequent write operations target contiguous logical address regions of already established segmented mapping entries; If subsequent write operations only cover a portion of the logical addresses within the region, the original segmented mapping entry is split into at least two new mapping entries based on the position of the covered region within the original contiguous logical address region. These new entries correspond to the unupdated contiguous logical address sub-region and the updated logical address region, respectively.

9. The method of adaptive mapping of flash memory of claim 8, wherein, After splitting the original segmented mapping entry into at least two new mapping entries, the method further includes: The length of the unupdated contiguous logical address sub-region is determined. If the length of the sub-region is less than a preset length threshold, it is converted from segment mapping mode to page mapping mode; if the length of the sub-region is not less than the preset length threshold, the segment mapping mode is maintained. For the updated logical address region, based on the logical address continuity corresponding to subsequent write operations, the segment mapping mode or page mapping mode is adaptively selected to establish the corresponding mapping entries. The original segmented mapping entries are marked as invalid, and the L2P mapping table is updated synchronously to complete the update of the mapping relationship after splitting.

10. The method of adaptive-mapped flash memory control of claim 1, wherein, The method further includes: In the L2P mapping table, a heat counter is associated with each segmented mapping entry; When a read or write access occurs to the logical address range covered by the segmented mapping entry, increment its corresponding hot counter. The segmented mapping entries are periodically sorted according to the heat counter. The top N segmented mapping entries with the highest heat and all the physical page data they map are migrated as a whole to a flash memory medium area with better read and write performance or lower latency, and the mapping entries are updated after migration.

11. A flash memory control system, comprising: include: The memory is used to store program code; as well as A processor, the processor being configured to invoke the program code to perform the method as described in any one of claims 1 to 10.

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