Cache mapping method, processor chip and electronic device

Abstract

Embodiments of the present application provide a cache mapping method, a processor chip and an electronic device. The method comprises: determining a mode identifier according to a segment number in a first address; determining a first vector in a mode matrix according to the mode identifier; the mode matrix comprises a plurality of vectors, each vector corresponds to one of preset modes, and each element in each vector indicates a mapping relationship between an intra-segment offset and an index in a corresponding path under a corresponding mode; and performing an addition operation based on a specified finite field on the intra-segment offset in the first address and each element in the first vector respectively to obtain indexes of the first address in each path. Embodiments of the present application can reduce the number of bits required by a hash function and the number of bits required by a record mapping position, reduce hardware implementation complexity, and improve cache effective space utilization while reducing conflict misses and optimizing cache hit efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a cache mapping method, a processor chip, and an electronic device. Background Technology

[0002] In the design of computer caching systems, set-associative mapping is a common cache organization method. This method divides the cache into several sets, each containing several ways; cache lines are mapped to a specific set according to an index function and can be stored on any way within that set.

[0003] In set-associative caches, when multiple frequently accessed main memory addresses are mapped to the same set after being calculated by an indexing function, severe location conflicts can occur, leading to missed cache hits and consequently reducing system performance. To mitigate this problem, skew-associative caches have been proposed. By configuring differentiated index hash functions for different paths within the cache, location conflicts concentrated in the same set in traditional set-associative caches are distributed across the entire cache range, thereby reducing missed cache hits and optimizing cache hit efficiency. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a cache mapping method that overcomes or at least partially solves the above problems. While reducing collisions and missing data and optimizing cache hit efficiency, it can reduce the number of bits required to generate the hash function and the number of bits required to record the mapping position, reduce hardware implementation complexity, and improve the effective utilization of cache space.

[0005] Accordingly, embodiments of the present invention also provide a processor chip and an electronic device to ensure the implementation and application of the above methods.

[0006] In a first aspect, embodiments of the present invention disclose a cache mapping method applied to a cache system containing multiple cache lines, the method comprising: The mode identifier is determined based on the segment number in the first address; A first vector is determined in the pattern matrix according to the pattern identifier; the pattern matrix contains multiple vectors, each vector corresponding to one of the preset patterns, and each element in each vector indicates the mapping relationship between the offset and the index in the corresponding road segment under the corresponding pattern. Perform addition operations based on a specified finite field on the segment offset in the first address and each element in the first vector to obtain the index of the first address in each path.

[0007] Secondly, embodiments of the present invention disclose a cache mapping method applied to a cache system containing multiple cache lines, the method comprising: Based on the target road, target index, and target mode identifier corresponding to the second address, the target element is determined in the mode matrix; the mode matrix contains multiple vectors, each vector corresponds to one of the preset modes, and each element in each vector indicates the mapping relationship between the offset and the index in the corresponding road segment under the corresponding mode; Perform an addition operation based on a specified finite field on the target index and the target element to obtain the offset within the target segment; The offset within the target segment and each element in the second vector are added using a specified finite field to obtain the index of the second address in each path; the second vector is the vector corresponding to the target mode identifier in the mode matrix.

[0008] Thirdly, embodiments of the present invention disclose a processor chip, comprising: Multi-way cache lines; The mode determination unit is used to determine a mode identifier based on the segment number in the first address; and to determine a first vector in the mode matrix based on the mode identifier; the mode matrix contains multiple vectors, each vector corresponding to one of the preset modes, and each element of each vector indicates the mapping relationship between the offset and the index in the corresponding road segment under the corresponding mode. The first index calculation unit is used to perform addition operations based on a specified finite field on the segment offset in the first address and each element in the first vector to obtain the index of the first address in each path.

[0009] Fourthly, embodiments of the present invention disclose a processor chip, comprising: Multi-way cache lines; An offset calculation unit is used to determine the target element in a pattern matrix based on the target road, target index, and target pattern identifier corresponding to the second address. The pattern matrix contains multiple vectors, each vector corresponding to one of the preset patterns, and each element in each vector indicates the mapping relationship between the offset and index within the corresponding road segment under the corresponding pattern. An addition operation based on a specified finite field is performed on the target index and the target element to obtain the offset within the target segment. The second index calculation unit is used to perform addition operations based on a specified finite field on the offset within the target segment and each element in the second vector to obtain the index of the second address in each path; the second vector is the vector corresponding to the target mode identifier in the mode matrix.

[0010] Fifthly, embodiments of the present invention disclose an electronic device, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, wherein the executable instruction causes the processor to perform the steps of any of the cache mapping methods described above.

[0011] The embodiments of the present invention have the following advantages: The cache mapping method provided in this invention is an optimized skew-associative mapping method. Memory addresses are divided into segment numbers and intra-segment offsets, and a pattern matrix is ​​pre-constructed. This pattern matrix contains multiple vectors, each corresponding to a preset pattern. Each element in the vector indicates the mapping relationship between the intra-segment offset and the index in the corresponding path under that pattern. For a first address to be accessed, a pattern identifier is first determined based on the segment number in the first address; then, a first vector is determined in the pattern matrix based on the pattern identifier; finally, addition operations based on a specified finite field are performed on the intra-segment offset of the first address and each element in the first vector to obtain the index of the first address in each path. This invention disperses positional conflicts concentrated in the same group in traditional set-associative mapping to the entire cache range, specifically to different positions in different paths, reducing conflict misses and optimizing cache hit efficiency. Furthermore, the embodiments of the present invention only require generating a fewer bit pattern identifier based on the segment number. Compared to the traditional skewed associative mapping method, which requires generating (number of paths w × index bit width n) bits for each path index, the output bit width of the hash function can be reduced, the hardware implementation complexity can be reduced, and the cache performance can be avoided due to hash mapping imbalance when the address range is small. Moreover, the embodiments of the present invention can simplify the mapping record from address to cache location, reduce the storage overhead of address tags, and improve the effective utilization of cache space. Attached Figure Description

[0012] Figure 1 This is a flowchart illustrating the steps of an embodiment of the cache mapping method of the present invention; Figure 2 This is a schematic diagram of cache mapping under different modes according to the present invention; Figure 3 This is a flowchart illustrating the steps of another embodiment of the cache mapping method of the present invention; Figure 4 This is a structural block diagram of an embodiment of the cache mapping device of the present invention; Figure 5 This is a structural block diagram of another embodiment of the cache mapping device of the present invention; Figure 6 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0013] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0014] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, the first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In embodiments of this invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0015] In related technologies, a skewed associative cache mapping method is used to distribute position conflicts that are concentrated in the same group in traditional set-associative caches to the entire cache range, thereby reducing conflict misses and optimizing cache hit efficiency.

[0016] However, the skew-associative mapping method requires designing an independent hash function for each path to calculate the index in each path. Furthermore, to support large-capacity caches, each hash function needs to generate a large number of bits of output. The hardware design and circuit implementation of the functions themselves are quite complex, and when the main memory access address range is small, it is prone to unbalanced mapping distribution, which not only fails to alleviate location conflicts but also further degrades cache performance. In addition, the skew-associative mapping method requires recording a corresponding address tag in each directory entry to mark the mapping relationship between memory addresses and cache locations, significantly increasing cache storage overhead and reducing the effective utilization of cache space.

[0017] Reference Figure 1 The diagram illustrates a flowchart of an embodiment of a cache mapping method according to the present invention. The method is applied to a cache system containing multiple cache lines and may include the following steps: Step 101: Determine the mode identifier based on the segment number in the first address; Step 102: Determine the first vector in the mode matrix according to the mode identifier; the mode matrix contains multiple vectors, each vector corresponds to one of the preset modes, and each element in each vector indicates the mapping relationship between the offset and the index in the corresponding road segment under the corresponding mode. Step 103: Perform addition operations based on a specified finite field on the segment offset in the first address and each element in the first vector to obtain the index of the first address in each path.

[0018] The cache mapping method provided in this embodiment of the invention can be applied to the cache system in a multi-core processor system to determine the mapping relationship between memory addresses and cache storage locations.

[0019] The multi-core processor system refers to a computing system integrating multiple processor cores. Each processor core (referred to as a core) can independently execute instructions and has concurrent access requirements to shared memory. Each core contains a private cache for storing copies of cache lines; a cache line is a data block of fixed size in the system's main memory. Multiple cores are interconnected via an on-chip network and share the system's main memory. The system further includes a consistency catalog subsystem, which maintains the distribution information of the copies of the cache lines in the private cache through the consistency catalog. The multi-core processor system can be a single multi-core chip or a multi-processor system composed of multiple chips, covering computing devices such as servers, personal computers, and embedded devices.

[0020] Each processor core can independently execute program instructions, process data, and includes a private Level 1 cache (L1 cache) and Level 2 cache (L2 cache). The multi-core processor system may further include a shared LLC (Last Level Cache), which is accessed by all cores via an on-chip network.

[0021] It is understood that the capacity, number of paths, and cache line size of the cache can be flexibly configured according to the actual application scenario. For example, the cache can be a core-private first-level cache (L1 cache) or second-level cache (L2 cache), or it can be a shared last-level cache (LLC). The cache mapping method is applicable to all levels of cache structure. Whether it is a private cache or a shared cache, its mapping logic follows the same address-to-storage location conversion rules.

[0022] Furthermore, the cache mapping method can work in conjunction with a consistent directory. Specifically, the cache mapping method determines the indexing method from address to cache location, and this indexing method is also used to locate the corresponding directory entry in the consistent directory, enabling cache access and directory access to be executed in parallel based on the same indexing logic, or to be executed collaboratively based on a deducible relationship.

[0023] The purpose of this invention is to distribute position conflicts concentrated in the same group in traditional set-associative caches across the entire cache range, thereby reducing missing conflicts and optimizing cache hit efficiency. Simultaneously, it reduces the output bit width of the hash function, decreases hardware implementation complexity, and avoids deterioration of cache performance due to hash mapping imbalance when the address range is small. Furthermore, it simplifies the mapping record from address to cache location, reduces tag storage overhead, and improves the effective utilization of cache space.

[0024] The cache mapping method provided in this embodiment of the invention is an optimized skew-associative mapping method. The address space is divided into several consecutive segments according to the capacity of one channel in the cache system, with each segment equal to the capacity of one channel. Correspondingly, the memory address is divided into a segment number and an offset within the segment, where the segment number is the high-order bit of the memory address and the offset within the segment is the low-order bit of the memory address.

[0025] It should be noted that in this embodiment of the invention, the memory address is divided into a segment number and an offset within the segment. The specific method of dividing the segment number and offset within the segment is not limited and can be arbitrary. For example, the segment number can be the high-order bits of the memory address, and the offset within the segment can be the low-order bits of the memory address. Alternatively, the segment number can be the address tag corresponding to the set-associative cache structure, and the offset within the segment can be the index corresponding to the set-associative cache structure.

[0026] In one example, assume the cache path capacity is 4 KiB and the cache line size is 64B. The cache line offset occupies the lowest 6 bits of the memory address (bits 0 to 5), used to locate the target byte within the cache line. Bits 6 to 11 of the memory address are the segment offset, a total of 6 bits, used to index the corresponding cache line within the segment; the size of each segment is equal to the path capacity. Bits 12 and above are the segment number, whose width is determined by subtracting 12 bits from the total memory address width, used to identify the segment to which the memory address belongs.

[0027] The cache mapping method is used when the processor performs a memory access operation. In response to the memory access operation, the corresponding location in the cache is located based on a first address. The first address refers to the memory address to be accessed. The memory access operation includes, but is not limited to, read operations, write operations, cache replacement operations, etc.

[0028] Specifically, in this embodiment of the invention, a memory address (such as a first address) is divided into a segment number and an offset within the segment. The segment number is mapped to a mode identifier of a small number of bits. Then, the mode vector corresponding to the mode identifier is XORed with the offset within the segment using the operational properties of finite fields to generate various indexes.

[0029] In this embodiment of the invention, the defined pattern is a one-to-one mapping from the segment offset to the index for each path. This embodiment of the invention does not limit the total number p of preset patterns. For example, p can be less than 2. nThe value of p is any value, where n is the index bit width. For example, the value of p can be 16 or 32.

[0030] This invention predefines p modes, each determining how memory addresses are mapped to locations in different cache paths. By constructing these predefined modes, two memory addresses mapped to the same location will only be mapped to the same location in other paths if and only if they use the same mode. That is, when two memory addresses use different modes, they may be mapped to the same location in one path, but in any other path, they will be mapped to different locations.

[0031] This invention distributes location conflicts concentrated within the same group in traditional set-associative caches across the entire cache range, specifically to different locations in different paths. That is, memory addresses using different modes, even if they accidentally map to the same location in one path, will be distributed to different locations in other paths. For example, addresses A and B using different modes may both map to location X in path 0, but in path 1, address A maps to location Y, and address B maps to location Z (Y ≠ Z). Therefore, accessing memory addresses using different modes will not generate location conflicts simultaneously in all paths, reducing conflict misses and optimizing cache hit efficiency.

[0032] Furthermore, in this embodiment of the invention, a pattern matrix is ​​pre-constructed. The pattern matrix contains multiple vectors (taking row vectors as an example), each vector corresponding to one of the preset patterns. Each element in each pattern vector indicates the mapping relationship between the offset and the index within the corresponding road segment under the corresponding pattern. For example, for p preset patterns, each preset pattern has a unique pattern identifier, and each pattern identifier corresponds to a vector (also called a pattern vector) in the pattern matrix. The statement that each element in each pattern vector indicates the mapping relationship between the offset and the index within the corresponding road segment under the corresponding pattern means that the number of elements in each pattern vector is the same as the number of roads w, each element corresponds to one of the w roads, and each element indicates the mapping relationship between the offset and the index within the corresponding road segment under the corresponding pattern.

[0033] For the first address to be accessed, after determining the pattern identifier based on the segment number in the first address, a first vector can be determined in the pattern matrix based on the pattern identifier; the first vector is the vector corresponding to the pattern identifier in the pattern matrix.

[0034] In one example, suppose four patterns are predefined, i.e., p=4. The pattern matrix contains four row vectors, each corresponding to one pattern. Let the pattern identifiers be 0, 1, 2, and 3, respectively. For ease of description, we will refer to the four patterns as Pattern 1 (pattern identifier 0), Pattern 2 (pattern identifier 1), Pattern 3 (pattern identifier 2), and Pattern 4 (pattern identifier 3). Assume the pattern matrix is ​​((0,0,0,0)(0,1,2,3)(0,2,3,1)(0,3,1,2)), which contains four row vectors: (0,0,0,0), (0,1,2,3), (0,2,3,1), and (0,3,1,2). Let Pattern 1 correspond to (0,0,0,0), Pattern 2 to (0,1,2,3), Pattern 3 to (0,2,3,1), and Pattern 4 to (0,3,1,2).

[0035] In this example, assuming the mode identifier is determined to be 1 (corresponding to mode 2) based on the segment number in the first address, then the first vector in the mode matrix can be determined as (0,1,2,3) based on this mode identifier. Each element in this first vector indicates the mapping relationship between the offset and index within the corresponding segment in mode 2. For example, assuming there are 4-way caches, the first element 0 in the first vector (0,1,2,3) is used to indicate the mapping relationship between the offset and index within the first segment in mode 2, the second element 1 is used to indicate the mapping relationship between the offset and index within the second segment in mode 2, the third element 2 is used to indicate the mapping relationship between the offset and index within the third segment in mode 2, and the fourth element 3 is used to indicate the mapping relationship between the offset and index within the fourth segment in mode 2.

[0036] Next, by performing addition operations based on a specified finite field on the segment offset in the first address and each element in the first vector, the index of the first address in each path can be obtained.

[0037] For example, in this example, assuming the intra-segment offset in the first address is 1, then this intra-segment offset is added to each element of the first vector (0,1,2,3) based on a specified finite field, resulting in a result vector. Each element in the result vector indicates the index of the first address in each path. For example, in this example, the calculated result vector is (1,0,3,2). In this result vector, the first element 1 indicates that the index of the first address in the first path is 1, the second element 0 indicates that the index of the first address in the second path is 0, the third element 3 indicates that the index of the first address in the third path is 3, and the fourth element 2 indicates that the index of the first address in the fourth path is 2.

[0038] A finite field is a field containing a finite number of elements. A finite field is also called a Galois field, denoted as GF(q), where q is the number of elements in the finite field. The number q of elements in a finite field must be a power of some prime number m, i.e., q = m. n (where m is a prime number and n is a positive integer). For example, GF(2 n ) is a 2-element array. n A finite field.

[0039] Finite field GF(2) n It has the following basic properties: the number of elements is 2. n Each element can be represented as an n-bit binary vector; addition is defined as a bitwise XOR operation.

[0040] With finite field GF(2 2 For example (n=2), GF(2) 2 ) contains 2 2 = 4 elements, each element can be represented as a 2-bit binary number. GF(2 2 Each element in ) is represented as shown in Table 1.

[0041] Table 1

[0042] Addition in a finite field is defined as bitwise XOR, i.e., modulo-2 addition of corresponding bits. For example, in the example above, the elements of the first vector (0,1,2,3) at offset 1 within the segment are respectively subjected to addition based on the specified finite field GF(2). 2 The addition operation is shown in Table 2. The calculation process and results are as follows.

[0043] Table 2

[0044] As shown in Table 2, firstly, the offset within the segment is 1 as operand 1 (integer representation is 1, binary representation is 01), and the first element in (0,1,2,3) is 2 as operand 2 (integer representation is 0, binary representation is 00). The two are added together, resulting in a binary result of 01 and an integer result of 1. Next, the offset within the segment is 1 as operand 1 (integer representation is 1, binary representation is 01), and the second element in (0,1,2,3) is 2 as operand 2 (integer representation is 1, binary representation is 01). The two are added together, resulting in a binary result of 00 and an integer result of 0. This process continues until the integer representation of the result vector is (1,0,3,2).

[0045] In an optional embodiment of the present invention, the specified finite field can be GF(2). n ), containing 2 nThere are 2 elements, and the total number of the preset patterns is p≤2. n , where n is the index width.

[0046] It should be noted that the value of p can be chosen arbitrarily. The larger the value of p, the better the effect of resolving position conflicts, but the benefit decreases as p increases. Experiments show that a value of 16 or 32 is sufficient for most scenarios.

[0047] The value of n determines the number of elements in the finite field, which is related to the index bit width. For example, when n=2, the index bit width is 2, and each path can index 2 elements. 2 =4 positions, corresponding to the finite field GF(2 2 ) contains 2 2 There are 4 elements, each used to map to an index; when n=4, the index width is 4 bits, and each path can index 2. 4 =16 positions, corresponding to the finite field GF(2 4 ) contains 2 4 =16 elements, each element is used to map to an index.

[0048] This invention predefines p modes, each determining how memory addresses are mapped to their positions in different cache paths. By constructing multiple predefined modes, two memory addresses mapped to the same location will only be mapped to the same location in other paths if and only if they use the same mode. Simultaneously, this invention divides the address space into segments the same size as a cache path; correspondingly, memory addresses are divided into segment numbers and offsets within those segments. When accessing a first address, the mode identifier is first determined based on the segment number in the first address, and then the corresponding mode vector (first vector) is determined. Calculations are then performed on the mode vector and the offset within the segment to obtain the index of the first address in each path. Through this invention, when accessing memory addresses of different modes, location conflicts will not occur simultaneously in all paths, reducing collision misses and optimizing cache hit efficiency. Furthermore, the embodiments of the present invention only require generating a fewer bit pattern identifier based on the segment number. Compared to the traditional skewed associative mapping method, which requires generating (number of paths w × index bit width n) bits for each path index, the output bit width of the hash function can be reduced, the hardware implementation complexity can be reduced, and the cache performance can be avoided due to hash mapping imbalance when the address range is small. Moreover, the embodiments of the present invention can simplify the mapping record from address to cache location, reduce the storage overhead of address tags, and improve the effective utilization of cache space.

[0049] In an optional embodiment of the present invention, determining the mode identifier based on the segment number in the first address may include: The segment number is hashed using a preset hash function to generate a pattern identifier; the bit width of the pattern identifier is the logarithm of base 2 p, where p is the total number of preset patterns.

[0050] In this embodiment of the invention, the pattern identifier is used to uniquely determine the pattern vector in the pattern matrix. This embodiment of the invention does not limit the method of generating the pattern identifier based on the segment number. For example, a preset hash function can be used to perform a hash calculation on the segment number to generate the pattern identifier. The preset hash function is not limited in this embodiment of the invention. Alternatively, a preset bit (such as the least significant bit) of the segment number can be directly taken as the pattern identifier.

[0051] In one example, suppose the first address is 0x12345 (binary representation: 0001 0010 0011 01000101). Suppose we extract the 0th and 1st bits of the first address as the segment offset (i.e., 01, integer representation is 1), and extract the 2nd and 3rd bits of the first address as the segment number (i.e., 01, integer representation is 1). Suppose we directly use this segment number as the mode identifier, i.e., the mode identifier is 1 (i.e., mode 2), corresponding to the 2nd row in the above mode matrix.

[0052] It is understood that the segment numbering and intra-segment offset division methods described in the above examples, as well as the method of generating pattern identifiers based on segment numbers, are merely illustrative examples. The embodiments of the present invention do not impose any limitations on the segment numbering and intra-segment offset division methods, nor on the method of generating pattern identifiers based on segment numbers.

[0053] In an optional embodiment of the present invention, the method may further include: A p×w (p rows, w columns) pattern matrix is ​​predefined, where p is the total number of the predefined patterns, w is the total number of cache lines, and element a in the i-th row and j-th column of the pattern matrix is... ij =r i ×c j ; where r i and c j All are elements within the specified finite field.

[0054] Specifically, for a cache with an intra-segment index of n bits and w paths, this embodiment of the invention can construct a p×w pattern matrix, where p is the total number of the preset patterns, and p≤2. n .

[0055] For example, the process of constructing the pattern matrix is ​​as follows: the segment offset in the memory address and the cache index are treated as a finite field GF(2). n Elements in ). Suppose we define a p×w pattern matrix A, and assign a GF(2) to each row and column of this pattern matrix. n The element in ) is denoted as r i and cj , requires r i They are all different, c j Each is different; the element a in the i-th row and j-th column of the pattern matrix is ​​different. ij =r i ×c j .

[0056] In Example 1, assume p=4, w=4, i takes the values ​​0, 1, 2, 3, and j takes the values ​​0, 1, 2, 3. Let r... i =i, c j =j. The element a in the first row and first column of the pattern matrix A. 00 =r0×c0=0×0=0, the element a in the 1st row and 2nd column. 01 =r0×c1=0×1=0, element a in the 1st row and 3rd column 02 =r0×c2=0×2=0, element a in the 1st row and 4th column 03 =r0×c3=0×3=0; the element a in the 2nd row and 1st column. 10 =r1×c0=1×0=0, the element a in the 2nd row and 2nd column. 11 =r1×c1=1×1=1, the element a in the 2nd row and 3rd column. 12 =r1×c2=1×2=2, the element a in the 2nd row and 4th column. 13 =r1×c3=1×3=3; and so on, the pattern matrix A is obtained as ((0,0,0,0)(0,1,2,3)(0,2,3,1)(0,3,1,2)).

[0057] The pattern matrix indicates how intra-segment offsets should be mapped to indices for memory addresses using different patterns. For example, in Example 1, assume the first address is 0x12345, the intra-segment offset is 1, and the pattern identifier is 1. Based on this pattern identifier, the first vector in the pattern matrix A above can be determined as the vector in the second row, i.e., (0,1,2,3). The first element of this first vector is used to map the intra-segment offset 1 to the index of the first path, the second element is used to map the intra-segment offset 1 to the index of the second path, the third element is used to map the intra-segment offset 1 to the index of the third path, and the fourth element is used to map the intra-segment offset 1 to the index of the fourth path. Therefore, performing addition operations based on a specified finite field on the intra-segment offset 1 and each element of the first vector respectively yields the result vector (1,0,3,2), which is the index of address 0x12345 in each path.

[0058] In this embodiment of the invention, for a memory address with a segment offset of y and using pattern x (e.g., x is a pattern identifier), its index in the i-th path is a. xi +y. Using GF(2n The operational properties of the above-mentioned index generation process can be transformed into an XOR operation between the segment offset and the pattern number bits, which is easy to implement in hardware.

[0059] Reference Figure 2 The diagram illustrates a cache mapping method under different modes according to the present invention. Figure 2 The example shown uses p=4, n=2, w=4 to illustrate a schematic diagram of the offsets within different segments and the mapping of memory addresses to different paths under different modes.

[0060] like Figure 2 As shown, the intra-segment offsets include 0, 1, 2, and 3. In Mode 1, intra-segment offset 0 has an index of 0 in path 1 (path 1); an index of 0 in path 2 (path 2); an index of 0 in path 3 (path 3); and an index of 0 in path 4 (path 4). In Mode 1, intra-segment offset 1 has an index of 3 in path 1 (path 1); an index of 3 in path 2 (path 2); an index of 3 in path 3 (path 3); and an index of 3 in path 4 (path 4). In Mode 1, intra-segment offset 2 has an index of 2 in path 1 (path 1); an index of 2 in path 2 (path 2); an index of 2 in path 3 (path 3); and an index of 1 in path 4 (path 4). In Mode 1, intra-segment offset 3 has an index of 1 in path 1 (path 1); an index of 1 in path 2 (path 2); an index of 1 in path 3 (path 3); and an index of 1 in path 4 (path 4).

[0061] In Mode 2, the index of intra-segment offset 0 is 0 in path 1 (path 1); its index is 1 in path 2 (path 2); its index is 2 in path 3 (path 3); and its index is 3 in path 4 (path 4). In Mode 2, the index of intra-segment offset 1 is 3 in path 1 (path 1); its index is 2 in path 2 (path 2); its index is 1 in path 3 (path 3); and its index is 0 in path 4 (path 4). In Mode 2, the index of intra-segment offset 2 is 2 in path 1 (path 1); its index is 3 in path 2 (path 2); its index is 0 in path 3 (path 3); and its index is 1 in path 4 (path 4). In Mode 2, the index of intra-segment offset 3 is 1 in path 1 (path 1); its index is 0 in path 2 (path 2); its index is 3 in path 3 (path 3); and its index is 2 in path 4 (path 4).

[0062] I will not go into details further.

[0063] As can be seen, for the same intra-segment offset, when using different modes, even if it accidentally maps to the same location in one path, it will be scattered to different locations in other paths. Therefore, when accessing memory addresses in different modes, location conflicts will not occur simultaneously in all paths, which can reduce collision misses and optimize cache hit efficiency.

[0064] It should be noted that the values ​​of p=4, n=2, and w=4 mentioned above are merely illustrative examples, and the embodiments of the present invention do not impose restrictions on the values ​​of p, n, and w. For example, n and w can be determined according to the chip size, and the value of p is preferably less than 2. n The value of .

[0065] In an optional embodiment of the present invention, the method may further include: Based on the index of the first address in each path, read the storage item at the corresponding index position. The storage item includes a tag field and a data field.

[0066] After calculating the index of the first address in each path, the storage items at the corresponding index positions can be read in parallel to perform subsequent operations. The storage items may include a tag field and a data field; by comparing the tag field of the first address with the tag fields read from each path, it can be determined whether a cache hit occurs; based on the hit result, the corresponding cache access operation is performed.

[0067] Furthermore, through the embodiments of the present invention, based on the known index position of the second address on a certain path (such as a known target path and target index) and the mode adopted (such as a known target mode identifier), the index of the second address on all paths can be calculated by reverse deduction.

[0068] For example, for a second address (such as address x), address x is unknown, but its index in a certain path is known (e.g., its index in the third path is known to be 3), and its target mode identifier is known, such as the target mode identifier being 1. Based on the cache mapping method of this invention, the indices corresponding to the second address (such as address x) in all paths can be calculated in reverse.

[0069] Taking pattern matrix A as an example, assuming the known target pattern identifier is 1 (corresponding to pattern 2), the corresponding second vector in pattern matrix A can be determined as the vector in the second row, i.e., (0,1,2,3). Since the known target path is the third path, and the third element in the second vector (0,1,2,3) corresponds to the third path, the target element can be determined as the third element in the pattern vector (0,1,2,3), and the value of the target element is 2. Performing an addition operation based on a specified finite field on the target index and the target element can obtain the offset within the target segment. For example, using index 3 and target element 2 in the finite field GF(2 2The elements in the target segment are added together to obtain an offset of 1. Next, addition operations based on a specified finite field are performed on the target segment offset and each element of the second vector to obtain the index of the second address in each path. In this example, the target segment offset 1 is added to each element of the second vector (0,1,2,3) corresponding to target mode identifier 1, resulting in the index of the second address in each path being (1,0,3,2).

[0070] Therefore, by using the cache mapping method of the present invention, when using a consistent directory in the following format, the number of address tags that need to be stored can be reduced, that is, the number of bits required to record the mapping location can be reduced, thereby reducing the hardware implementation complexity and improving the effective utilization of cache space.

[0071] The consistency directory has the following format: multiple directory entries are used to record the distribution information of cache line replicas at the same address, and the address label is recorded only in the first directory entry. For example, for the target cache line corresponding to address A, the address label of address A is recorded only in the first directory entry, and only a few bits are used in the second directory entry to record the target path pointer, which points to the first directory entry where the address label of address A is stored. Thus, the first directory entry can be found through the target path pointer in the second directory entry to obtain the address label.

[0072] By using this consistent directory, for the same address, only one address label needs to be recorded in the first directory entry, and the address labels do not need to be recorded in the remaining second directory entries, thus reducing the number of address labels that need to be stored. Combined with the cache mapping method of this invention, the position on other paths can be calculated by reverse engineering based on the known position and pattern of the second address on a certain path, even without knowing the second address. This process does not require knowing the second address. If any directory entry in these calculated positions records an address label, the address label can be read to deduce the second address. Therefore, using the cache mapping method of this invention, for the same address, it is not necessary to record the address label in every directory entry. For cache lines of the same address, only the address label needs to be recorded in the first directory entry, while the target path pointer and the used pattern identifier need to be recorded in the second directory entries. The pattern identifier requires fewer bits than the address label, thus reducing the number of bits required to record the mapping position.

[0073] It should be noted that the format of the consistency directory described above is only illustrative, and the specific format of the consistency directory is not limited in this embodiment of the invention. It is acceptable as long as the format of the consistency directory meets the requirement of mapping the address corresponding to the directory entry to the location of other paths.

[0074] In summary, the cache mapping method provided by this invention is an optimized skew-associative mapping method that can achieve the same position conflict dispersion effect as the traditional skew-associative mapping method. Furthermore, it can further reduce the number of bits required to generate the hash function and the number of bits required to record the mapping position, thereby reducing hardware implementation complexity and improving the effective utilization of cache space.

[0075] Furthermore, embodiments of the present invention construct a variety of predefined different modes so that two memory addresses mapped to the same location will be mapped to the same location on other paths only if the two memory addresses use the same mode.

[0076] It can be proven that two memory addresses mapped to the same location are mapped to the same location on other paths if and only if these two memory addresses use the same pattern and have the same intra-segment offset, with a probability of 1 / p. For skewed associative structures, this probability is not less than 1 / 2. n Therefore, this solution can use 2 n This mode achieves results comparable to or better than traditional skewed interconnects, or uses fewer than 2... n This invention provides a method that achieves results comparable to traditional skewed associativity. Furthermore, compared to traditional skewed associativity, this invention can further reduce the number of bits required to generate the hash function and the number of bits required to record the mapping position.

[0077] The proof is as follows: Assume memory address X uses mode i with an offset of x within the segment; memory address Y uses mode j with an offset of y within the segment; addresses X and Y are mapped to the same location on the k-th path, i.e., x+a. ik =y+a jk If it also maps to the same position on the l-th path, then we have x+a il =y+a jl After rearranging, we get a. ik -a il -a jk +a jl =0, substitute a ij =r i ×c j And by using the associative law, we obtain (r) i -r j )×(c l -c k ) = 0. Since k != l (different paths), it can only be (r) i =r j Since the same pattern is used, substituting back, we get x=y, meaning the offsets within the segment are the same. The probability that any two memory addresses have the same pattern is 1 / p. Therefore, the probability calculated above is 1 / p.

[0078] Reference Figure 3 The diagram illustrates a flowchart of another embodiment of the cache mapping method of the present invention. The method is applied to a cache system containing multiple cache lines and may include the following steps: Step 301: Based on the target road, target index and target mode identifier corresponding to the second address, determine the target element in the mode matrix; the mode matrix contains multiple vectors, each vector corresponds to one of the preset modes, and each element in each vector indicates the mapping relationship between the offset and the index in the corresponding road segment under the corresponding mode. Step 302: Perform an addition operation based on a specified finite field on the target index and the target element to obtain the offset within the target segment; Step 303: Perform addition operations based on a specified finite field on the offset within the target segment and each element in the second vector to obtain the index of the second address in each path; the second vector is the vector corresponding to the target mode identifier in the mode matrix.

[0079] In Example 2, suppose a new directory entry needs to be created for address y in the consistency directory. Address y maps to position a, and position a is assumed to be the position corresponding to index 3 of the 3rd path. Assume position a already stores directory entry 1, which is the directory entry corresponding to address x (called the second address), and that the pattern identifier recorded in directory entry 1 is 1. The known target path is the 3rd path, the target index is index 3, and the target pattern identifier is 1. Based on the known target path, target index, and target pattern identifier of the second address, the target element can be determined in the pattern matrix. Taking pattern matrix A as an example, the target pattern identifier is 1, and the corresponding second vector in pattern matrix A is the vector in the 2nd row, i.e., (0,1,2,3). Since the target path is the 3rd path, and the 3rd element in the second vector (0,1,2,3) corresponds to the 3rd path, the target element can be determined to be the 3rd element in the pattern vector (0,1,2,3), and the value of the target element is 2. Performing an addition operation based on a specified finite field on the target index and the target element yields the offset within the target segment. For example, using index 3 and target element 2 in the finite field GF(2 2 The offset within the target segment is 1. Next, addition operations based on a specified finite field are performed on the offset within the target segment and each element of the second vector to obtain the index of the second address (address x) in each path. In this example, the offset within the target segment 1 is added to each element of the second vector (0,1,2,3) corresponding to pattern identifier 1, resulting in the index of the second address in each path being (1,0,3,2). This process does not require knowledge of the complete second address.

[0080] Through the embodiments of the present invention, based on the known cache location of the second address in a certain path (such as a known path and index) and the mode used, the index of the second address in all paths can be calculated. Then, operations such as moving, replacing, or invalidating can be performed on the directory entry corresponding to the second address (such as directory entry 1).

[0081] In an optional embodiment of the present invention, the method may further include: Step S11: Based on the index of the second address in each path, read the corresponding directory entry in the consistency directory and determine the first directory entry from it; the first directory entry records the target path pointer; Step S12: Read the address tag from the second directory entry pointed to by the target path pointer, and obtain the second address based on the read address tag; Step S13: Based on the second address, perform a replacement operation on the target directory entry corresponding to the second address in the consistency directory.

[0082] The cache mapping method provided by this invention can be used to determine the index position of a given address in the cache. The consistency directory is used to record the distribution information of each cache line in the private caches of multiple cores. When cache misses, cache replacements, or directory entry conflicts occur, both the cache and the consistency directory need to be accessed collaboratively. The cache mapping method provides index location, and the directory entry provides address labels and sharer information; together, they support the complete execution of the consistency protocol.

[0083] For example, in Example 2, when directory entries conflict, a directory entry replacement operation may be needed, such as replacing directory entry 1 with directory entry 2, or moving directory entry 1 to an empty position and creating directory entry 2 in the original position of directory entry 1. In Example 2, after calculating the index of the second address (e.g., address x) across all paths, the corresponding directory entries in the consistency directory can be read from each path index. This allows the identification of the second directory entry containing the path pointer. Then, the first directory entry pointed to by the path pointer is read, allowing the address label to be read from the first directory entry, and the second address (e.g., address x) to be recovered. Based on the second address (e.g., address x), operations such as moving, replacing, or invalidating directory entry 1 can be performed, and then directory entry 2 corresponding to address y can be created in the original position of directory entry 1.

[0084] It should be noted that when performing the directory entry replacement operation, it is also necessary to read the address tag and sharer information stored in the target directory entry to be replaced (such as directory entry 1), send an invalidation message to each processor core holding the corresponding cache line copy according to the sharer information, and clear or overwrite the target directory entry after receiving the confirmation.

[0085] Furthermore, if directory entry 1 does not record an address label, meaning directory entry 1 is the second directory entry, then after calculating the index of the second address across all roads, directory entries at index positions in other roads can be read, and thus the address label can be read from the first directory entry at a certain position. Furthermore, the complete second address can be calculated based on the read address label, providing a basis for subsequent directory entry replacement operations.

[0086] The cache mapping method provided in this invention, for a directory entry already existing in the cache (corresponding to a second address), only needs to record its mode identifier, totaling log2(p) bits. Based on the location of the directory entry (e.g., known target path and target index) and the mode identifier, the index of the second address mapped to all other paths can be calculated. Log2(p) is significantly reduced compared to the w×n bit index per path, greatly decreasing the required number of bits. The cache mapping method provided by this invention achieves the same position conflict dispersion effect as the traditional skew-associative mapping method, and further reduces the bits required for hash function generation and recording mapping positions, lowering hardware implementation complexity and improving the effective utilization of cache space.

[0087] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0088] Reference Figure 4 The diagram illustrates a structural block diagram of an embodiment of a cache mapping apparatus according to the present invention. The apparatus is applied to a cache system containing multiple cache lines and may include: The mode determination module 401 is used to determine the mode identifier based on the segment number in the first address; The first vector determination module 402 is used to determine a first vector in the mode matrix according to the mode identifier; the mode matrix contains multiple vectors, each vector corresponds to one of the preset modes, and each element in each vector indicates the mapping relationship between the offset and the index in the corresponding road segment under the corresponding mode. The first index calculation module 403 is used to perform addition operations based on a specified finite field on the segment offset in the first address and each element in the first vector to obtain the index of the first address in each path.

[0089] Optionally, the pattern determination module is specifically used for: The segment number is hashed using a preset hash function to generate a pattern identifier; the bit width of the pattern identifier is the logarithm of base 2 p, where p is the total number of preset patterns.

[0090] Optionally, the pattern matrix is ​​p rows and w columns, where p is the total number of preset patterns, w is the total number of cache lines, and the element a in the i-th row and j-th column of the pattern matrix is... ij =r i ×c j ; where r i and c j All are elements within the specified finite field.

[0091] Optionally, the specified finite field includes 2 n There are 2 elements, and the total number of the preset patterns is less than or equal to 2. n , where n is the index width.

[0092] Optionally, the cache mapping device further includes: The content reading module is used to read the storage item at the corresponding index position according to the index of the first address in each path. The storage item includes a tag field and a data field.

[0093] Optionally, the cache mapping device further includes: The address partitioning module is used to divide the address space into several consecutive segments according to the capacity of one channel in the cache system, with each segment being equal to the capacity of one channel. Correspondingly, the memory address is divided into a segment number and an offset within the segment, where the segment number is the high-order bit of the memory address and the offset within the segment is the low-order bit of the memory address.

[0094] Reference Figure 5 The diagram illustrates a structural block diagram of another embodiment of the cache mapping apparatus of the present invention. The apparatus is applied to a cache system containing multiple cache lines and may include: The element determination module 501 is used to determine the target element in the pattern matrix based on the target road, target index and target pattern identifier corresponding to the second address; the pattern matrix contains multiple vectors, each vector corresponds to one of the preset patterns, and each element in each vector indicates the mapping relationship between the offset and the index in the corresponding road segment under the corresponding pattern. Offset calculation module 502 is used to perform an addition operation based on a specified finite field on the target index and the target element to obtain the offset within the target segment; The second index calculation module 503 is used to perform addition operations based on a specified finite field on the offset within the target segment and each element in the second vector to obtain the index of the second address in each path; the second vector is the vector corresponding to the target mode identifier in the mode matrix.

[0095] Optionally, the device further includes: The directory entry reading module is used to read the corresponding directory entry in the consistency directory based on the index of the second address in each path, and determine the first directory entry from it; the first directory entry records the target path pointer; The address restoration module is used to read address tags from the second directory entry pointed to by the target path pointer, and obtain the second address based on the read address tags; The operation execution module is used to perform a replacement operation on the target directory entry corresponding to the second address in the consistency directory based on the second address.

[0096] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0097] Reference Figure 6 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Figure 6 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store at least one executable instruction, which causes the processor to execute the steps of the cache mapping method of the aforementioned embodiment.

[0098] This invention provides a processor chip, the processor chip comprising: Multi-way cache lines; The mode determination unit is used to determine a mode identifier based on the segment number in the first address; and to determine a first vector in the mode matrix based on the mode identifier; the mode matrix contains multiple vectors, each vector corresponding to one of the preset modes, and each element of each vector indicates the mapping relationship between the offset and the index in the corresponding road segment under the corresponding mode. The first index calculation unit is used to perform addition operations based on a specified finite field on the segment offset in the first address and each element in the first vector to obtain the index of the first address in each path.

[0099] Furthermore, the pattern determination unit is specifically used for: The segment number is hashed using a preset hash function to generate a pattern identifier; the bit width of the pattern identifier is the logarithm of base 2 p, where p is the total number of preset patterns.

[0100] Furthermore, the pattern matrix is ​​p rows and w columns, where p is the total number of preset patterns, w is the total number of cache lines, and the element a in the i-th row and j-th column of the pattern matrix is... ij =r i×c j ; where r i and c j All are elements within the specified finite field.

[0101] This invention provides another processor chip, the processor chip comprising: Multi-way cache lines; An offset calculation unit is used to determine the target element in a pattern matrix based on the target road, target index, and target pattern identifier corresponding to the second address. The pattern matrix contains multiple vectors, each vector corresponding to one of the preset patterns, and each element in each vector indicates the mapping relationship between the offset and index within the corresponding road segment under the corresponding pattern. An addition operation based on a specified finite field is performed on the target index and the target element to obtain the offset within the target segment. The second index calculation unit is used to perform addition operations based on a specified finite field on the offset within the target segment and each element in the second vector to obtain the index of the second address in each path; the second vector is the vector corresponding to the target mode identifier in the mode matrix.

[0102] Furthermore, the processor chip also includes: The directory access unit is used to read the corresponding directory entry in the consistency directory based on the index of the second address in each path, and determine the first directory entry therefrom; the first directory entry records the target path pointer; read the address tag from the second directory entry pointed to by the target path pointer, and obtain the second address based on the read address tag; and perform a replacement operation on the target directory entry corresponding to the second address in the consistency directory based on the second address.

[0103] This invention provides a non-transitory computer-readable storage medium that, when the instructions in the storage medium are executed by a terminal's program or processor, enables the terminal to perform the steps of the cache mapping method described in the foregoing embodiments. The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0104] Those skilled in the art will understand that embodiments of the present invention can be provided as a cache mapping method, apparatus, electronic device, or computer program product. Therefore, embodiments of the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0105] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0106] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0107] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0108] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0109] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A cache mapping method, characterized in that, Applied to a caching system containing multiple cache lines, the method includes: The mode identifier is determined based on the segment number in the first address; different modes determine how the memory address is mapped to the location in each cache path; The first vector is determined in the mode matrix according to the mode identifier; the mode matrix contains multiple vectors, each vector corresponds to one of the preset modes, each vector contains the same number of elements as the number of paths w, each element corresponds to one of the paths w, and each element indicates the mapping relationship between the offset and the index in the middle segment of the corresponding path under the corresponding mode. Perform addition operations based on a specified finite field on the segment offset in the first address and each element in the first vector to obtain the index of the first address in each path; The step of determining the mode identifier based on the segment number in the first address includes: The segment number is hashed using a preset hash function to generate a pattern identifier; the bit width of the pattern identifier is the logarithm of base 2 p, where p is the total number of preset patterns.

2. The method according to claim 1, characterized in that, The pattern matrix has p rows and w columns, where p is the total number of preset patterns, w is the total number of cache lines, and element a in the i-th row and j-th column of the pattern matrix. ij =r i ×c j ; where r i and c j All are elements within the specified finite field.

3. The method according to claim 1, characterized in that, The specified finite field contains 2 n There are 2 elements, and the total number of the preset patterns is less than or equal to 2. n , where n is the index width.

4. The method according to claim 1, characterized in that, The method further includes: Based on the index of the first address in each path, read the storage item at the corresponding index position. The storage item includes a tag field and a data field.

5. The method according to claim 1, characterized in that, The method further includes: The address space is divided into several consecutive segments according to the capacity of one channel in the cache system, and the size of each segment is equal to the capacity of one channel; accordingly, the memory address is divided into a segment number and an offset within the segment, where the segment number is the high-order bit of the memory address and the offset within the segment is the low-order bit of the memory address.

6. A cache mapping method, characterized in that, Applied to a caching system containing multiple cache lines, the method includes: Based on the known target road, target index, and target mode identifier of the second address, the target element is determined in the mode matrix; the mode matrix contains multiple vectors, each vector corresponds to one of the preset modes, the number of elements in each vector is the same as the number of roads w, each element corresponds to one of the w roads, and each element indicates the mapping relationship between the offset and the index in the middle segment of the corresponding road under the corresponding mode. Perform an addition operation based on a specified finite field on the target index and the target element to obtain the offset within the target segment; The offset within the target segment and each element of the second vector are added using a specified finite field to obtain the index of the second address in each path; the second vector is the vector corresponding to the target mode identifier in the mode matrix; The step of determining the target element in the pattern matrix based on the known target road, target index, and target pattern identifier of the second address includes: The target element is determined from the target path by determining the corresponding second vector in the pattern matrix based on the target pattern identifier.

7. The method according to claim 6, characterized in that, The method further includes: Based on the index of the second address in each path, the corresponding directory entry in the consistency directory is read, and the first directory entry is determined from it; the first directory entry records the target path pointer; Read the address tag from the second directory entry pointed to by the target path pointer, and obtain the second address based on the read address tag; Based on the second address, a replacement operation is performed on the target directory entry corresponding to the second address in the consistency directory.

8. A processor chip, characterized in that, The processor chip includes: Multi-way cache lines; A mode determination unit is used to determine a mode identifier based on the segment number in the first address; and to determine a first vector in the mode matrix based on the mode identifier; the mode matrix contains multiple vectors, each vector corresponding to one of the preset modes, each vector containing the same number of elements as the number of paths w, each element corresponding to one of the paths w, and each element indicating the mapping relationship between the offset and the index in the corresponding path under the corresponding mode; wherein, different modes determine the mapping method from the memory address to the position in each cache path; The first index calculation unit is used to perform addition operations based on a specified finite field on the segment offset in the first address and each element in the first vector to obtain the index of the first address in each path; The mode determination unit is specifically used for: The segment number is hashed using a preset hash function to generate a pattern identifier; the bit width of the pattern identifier is the logarithm of base 2 p, where p is the total number of preset patterns.

9. The processor chip according to claim 8, characterized in that, The pattern matrix has p rows and w columns, where p is the total number of preset patterns, w is the total number of cache lines, and element a in the i-th row and j-th column of the pattern matrix. ij =r i ×c j ; where r i and c j All are elements within the specified finite field.

10. A processor chip, characterized in that, The processor chip includes: Multi-way cache lines; An offset calculation unit is used to determine a target element in a pattern matrix based on the target road, target index, and target pattern identifier known from the second address. The pattern matrix contains multiple vectors, each vector corresponding to one of the preset patterns. The number of elements in each vector is the same as the number of roads w. Each element corresponds to one of the w roads, and each element indicates the mapping relationship between the offset and the index within the corresponding road segment under the corresponding pattern. An addition operation based on a specified finite field is performed on the target index and the target element to obtain the offset within the target segment. The determination of the target element in the pattern matrix based on the target road, target index, and target pattern identifier known from the second address includes: determining the corresponding second vector in the pattern matrix according to the target pattern identifier, and determining the target element from the second vector according to the target road. The second index calculation unit is used to perform addition operations based on a specified finite field on the offset within the target segment and each element in the second vector to obtain the index of the second address in each path; the second vector is the vector corresponding to the target mode identifier in the mode matrix.

11. The processor chip according to claim 10, characterized in that, The processor chip also includes: The directory access unit is used to read the corresponding directory entry in the consistency directory based on the index of the second address in each path, and determine the first directory entry therefrom; the first directory entry records the target path pointer; read the address tag from the second directory entry pointed to by the target path pointer, and obtain the second address based on the read address tag; and perform a replacement operation on the target directory entry corresponding to the second address in the consistency directory based on the second address.

12. An electronic device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform the steps of the cache mapping method as described in any one of claims 1 to 7.

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