Classification method, system, medium, program and electronic terminal for integrated circuit layout

Abstract

This application provides a method, system, medium, program, and electronic terminal for classifying integrated circuit layouts. By identifying graphic units within the layout to be classified and extracting contour features to obtain key coordinate points, it achieves significant dimensionality reduction while preserving key geometric features, thereby significantly reducing computational complexity and improving processing efficiency. Furthermore, it maps and aligns the key coordinate points to grid points according to a preset grid step size, constructing a physical tolerance mechanism and effectively eliminating coordinate jitter introduced by precision limitations or process errors. This method enables the accurate classification of graphics with the same topology but minor differences in coordinates, significantly improving the algorithm's robustness to process deviations, avoiding fragmentation of classification results, and achieving good classification performance.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and in particular to a method, system, medium, program, and electronic terminal for classifying integrated circuit layouts. Background Technology

[0002] With the continuous evolution of integrated circuit manufacturing processes, the scale and complexity of chip design are growing exponentially. In critical stages such as design rule checking, optical proximity correction, and lithography mask data processing, it is often necessary to identify and extract representative pattern (layout) from massive amounts of graphic units for subsequent targeted optimization or analysis. However, facing hundreds of millions of layouts, without an effective screening mechanism, computing resources will be overwhelmed. Therefore, how to efficiently and accurately classify layouts is a core problem that urgently needs to be solved in the field of electronic design automation.

[0003] Current layout classification methods primarily rely on rigorous geometric comparison techniques, which determine whether graphics are identical by calculating the coordinate consistency of their vertices or using Boolean operations (such as XOR operations). However, this approach faces two significant challenges in practical applications. Firstly, it is overly sensitive to minute perturbations in layout data, lacking necessary tolerance mechanisms. Due to limitations in floating-point precision, format conversions of process data, or optical corrections and fine-tuning of layouts, even graphics of the same type often exhibit slight jitter or deviations in their vertex coordinates. Traditional rigorous comparison methods may misclassify these essentially identical graphics with only minor coordinate differences as different categories, leading to severely fragmented classification results that fail to meet the engineering requirements for normalized classification of topologically similar graphics. Secondly, the data processing efficiency of existing technologies struggles to handle massive layout scales. To describe complex graphic contours or meet lithographic smoothness requirements, layout data typically contains a large number of redundant vertices that contribute very little to classification features. Directly performing geometric calculations or feature extraction based on these full original coordinate points incurs enormous computational overhead.

[0004] In addition, some classification methods use pixel-based image matching technology. Although this method has a certain fuzzy matching capability, it requires rasterizing vector data, which not only makes feature extraction slow but also occupies a huge amount of storage space, making it difficult to meet the timeliness requirements of real-time processing of large-scale map data. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method, system, medium, program and electronic terminal for classifying integrated circuit layouts to solve the aforementioned problems.

[0006] To achieve the above and other related objectives, a first aspect of this application provides a method for classifying integrated circuit layouts, characterized by comprising: identifying each graphic unit within the layout to be classified; extracting contour features from the initial coordinate points constituting the contours of each graphic unit to obtain key coordinate points characterizing the contour structure features; mapping each key coordinate point to a corresponding grid point within its grid according to a preset grid step size to obtain aligned grid point coordinates; and determining the classification result of the layout to be classified based on the grid point coordinates.

[0007] In one embodiment of the first aspect of this application, the step of extracting contour features from the initial coordinate points constituting the contours of each graphic unit specifically includes: based on the Douglas-Puk algorithm, according to a preset distance threshold, performing iterative simplification processing on the initial coordinate points corresponding to the contours of each graphic unit to obtain the key coordinate points retained after simplification of each graphic unit.

[0008] In one embodiment of the first aspect of this application, the initial coordinate point is a relative coordinate point obtained by normalizing the original coordinates of the graphic unit with reference to a specific vertex of the map to be classified.

[0009] In one embodiment of the first aspect of this application, determining the classification result of the map to be classified based on the grid coordinates of each grid point specifically includes: converting the grid coordinates of each graphic unit into coordinate strings; encoding each coordinate string based on the BKDRHash algorithm to obtain the graphic hash value corresponding to each graphic unit; and determining the classification result of the map to be classified based on the combination of all graphic hash values ​​in the map to be classified.

[0010] In one embodiment of the first aspect of this application, the corresponding grid point is: a grid point located at a fixed position within the grid, or a grid point closest to the key coordinate point.

[0011] In one embodiment of the first aspect of this application, the type of the graphic unit is: a closed polygon and / or a non-closed graphic path.

[0012] In one embodiment of the first aspect of this application, the distance threshold is dynamically determined based on the length of the grid step.

[0013] To achieve the above and other related objectives, a second aspect of this application provides a classification system for integrated circuit layouts, comprising: a feature extraction module for identifying each graphic unit within the layout to be classified, and extracting contour features from the initial coordinate points constituting the contours of each graphic unit to obtain key coordinate points characterizing the contour structure features; a grid alignment module for mapping each key coordinate point to a corresponding grid point within its grid according to a preset grid step size to obtain aligned grid point coordinates; and a category classification module for determining the classification result of the layout to be classified based on the grid point coordinates.

[0014] To achieve the above and other related objectives, a third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in any of the preceding claims.

[0015] To achieve the above and other related objectives, a fourth aspect of this application provides a computer program product comprising computer program code that, when executed on a computer, causes the computer to perform the method described in any of the preceding claims.

[0016] To achieve the above and other related objectives, a fifth aspect of this application provides an electronic terminal, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the method described in any of the preceding claims.

[0017] As described above, this application has the following beneficial effects:

[0018] This disclosure identifies each graphic unit within the layout to be classified and extracts contour features from the initial coordinate points constituting the contour of each graphic unit to obtain key coordinate points characterizing the contour structure. This significantly reduces the dimensionality of the overall layout data while ensuring that the key geometric features of the graphic units are not lost, thus significantly reducing the computational complexity of subsequent encoding, classification, and comparison processes, and thereby greatly improving the algorithm's processing efficiency.

[0019] Furthermore, this disclosure maps each key coordinate point to its corresponding grid point within its own grid according to a preset grid step size to obtain aligned grid point coordinates. This discretized alignment process is equivalent to constructing a physical tolerance mechanism, which can effectively eliminate minor coordinate jitter introduced by floating-point precision limitations, process data conversion errors, or lithography correction fine-tuning. This allows graphic units that are essentially the same in topology but have slight differences in coordinates to be accurately classified into the same category, significantly improving the robustness of the classification algorithm to process deviations, avoiding excessive fragmentation of classification results, and achieving good classification performance. Attached Figure Description

[0020] Figure 1 The diagram shown is a flowchart illustrating a method for classifying integrated circuit layouts according to an embodiment of this application.

[0021] Figure 2 This diagram illustrates the process of extracting contour features from the initial coordinates of each graphic unit contour using the Douglas-Pokal algorithm in one embodiment of this application. Figure 1 .

[0022] Figure 3 This diagram illustrates the process of extracting contour features from the initial coordinates of each graphic unit contour using the Douglas-Pokal algorithm in one embodiment of this application. Figure 2 .

[0023] Figure 4 This diagram illustrates the process of extracting contour features from the initial coordinates of each graphic unit contour using the Douglas-Pokal algorithm in one embodiment of this application. Figure 3 .

[0024] Figure 5 This diagram illustrates the process of extracting contour features from the initial coordinates of each graphic unit contour using the Douglas-Pokal algorithm in one embodiment of this application. Figure 4 .

[0025] Figure 6 The diagram shown is a structural schematic of the layout to be classified and the graphic unit in one embodiment of this application.

[0026] Figure 7 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of this application. Detailed Implementation

[0027] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0028] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, "first XX" and "second XX" are merely used to distinguish different XXs and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply that they are different.

[0029] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0030] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0031] The first aspect of this application provides a method for classifying integrated circuit layouts, characterized in that it includes:

[0032] S1: Identify each graphic unit within the map to be classified, and extract the contour features of the initial coordinate points that constitute the contour of each graphic unit to obtain the key coordinate points that characterize the contour structure features.

[0033] In this application, a pattern to be classified (hereinafter referred to as "pattern") is a physical pattern or structural array with a specific shape and size formed on a substrate in an integrated circuit. A pattern unit refers to a basic element or an independent pattern feature that constitutes the entire pattern to be classified.

[0034] In one embodiment of the first aspect of this application, the type of the graphic unit is: a closed polygon and / or a non-closed graphic path. It should be understood that the graphic unit includes three cases: one such as... Figure 6The first method refers only to the closed polygons 102 within the area 101 to be classified. Key coordinate points are obtained by filtering the initial coordinate points of the outlines of all closed polygons 102 within the area 101 to be classified. Grid coordinate points are then obtained based on these key coordinate points, and the classification result of the area 101 is determined based on these grid coordinate points. The second method refers to both closed polygons and non-closed graphic paths (not shown) within the area to be classified; that is, any graphic lines falling within the area are included, contributing to the classification result. The third method refers only to non-closed graphic paths (not shown) within the area to be classified. The classification result of the area is determined based on all non-closed graphic paths within the area.

[0035] An outline refers to the precise geometric boundary of a graphic unit. For a closed polygon (such as a rectangle or a complex polygon), its outline is a closed loop connecting its ends; for a non-closed graphic path (such as a wire or a polyline), its outline is the open trajectory of that path. It should be understood that in computers, an outline is digitally represented by a series of sequentially connected points.

[0036] The initial coordinate points are the raw digital representation of the aforementioned contour, typically exported directly from design files or obtained through high-precision image measurement. These points contain a large number of redundant points (e.g., multiple midpoints describing a straight line segment). The high density of these points, when sequentially connected, can faithfully reconstruct the original shape. Due to the high precision requirements of layout design tools or the influence of optical proximity correction, the directly read initial coordinate points are often very dense and may contain minute coordinate fluctuations caused by process fine-tuning. While this redundant data describes microscopic details, it is often superfluous for characterizing the macroscopic topological structure of the graphic, increasing computational burden and potentially introducing noise, thus hindering direct feature comparison and classification. Therefore, it is necessary to extract key coordinate points that can characterize the contour's structural features through feature extraction.

[0037] In one embodiment of the first aspect of this application, the step of extracting contour features from the initial coordinate points constituting the contours of each graphic unit specifically includes: based on the Douglas-Puk algorithm, according to a preset distance threshold, performing iterative simplification processing on the initial coordinate points corresponding to the contours of each graphic unit to obtain the key coordinate points retained after simplification of each graphic unit.

[0038] In this embodiment, the Douglas-Pock algorithm is used to extract contour features from the initial coordinate points that constitute the contours of each graphic unit. The Douglas-Pock algorithm aims to significantly reduce the amount of data while preserving shape features by approximating complex curves as a series of simplified key points. Its core processing logic is as follows: First, a straight line is drawn connecting the beginning and end points of each curve segment to be processed. The vertical distance from all intermediate points on the curve segment to this straight line is calculated, and the maximum distance value (denoted as disMax) is found. Then, this maximum distance value is compared with a preset distance threshold (T). If disMax is less than the distance threshold T, it indicates that all intermediate points on the curve segment are redundant details for representing the contour structure and are all discarded. If disMax is greater than or equal to the distance threshold T, the point corresponding to the maximum distance is retained (and other points on the curve segment are to be determined). The original curve is divided into two sub-curves with this point as the boundary. The above iterative operation of "connecting-measuring-comparing-discarding" is repeated on these two sub-curves until all points on the sub-curve segments meet the accuracy requirements.

[0039] by Figure 2-5 Taking the graphic outline shown, which contains 8 initial coordinate points (labeled sequentially as point 1 to point 8), as an example, the specific execution process of the algorithm is as follows:

[0040] S11: First, as Figure 2 As shown, a straight line is drawn between the two points at the beginning and end of the curve (point 1 and point 8). The distance from each intermediate point (point 2 to point 7) to the straight line is calculated. It is assumed that the distance from point 4 to the straight line is the largest (this distance is denoted as disMax) and is greater than the preset distance threshold. Therefore, point 4 is retained (and points 2-3 and 5-7 on this curve segment are to be determined).

[0041] S12: Next, as Figure 3 As shown, the curve is divided into two parts, "point 1 to point 4" and "point 4 to point 8", with point 4 as the boundary. They are processed separately: In the "point 1 to point 4" segment, it is found that the maximum distance from the middle point (point 2 and point 3) to the line connecting the beginning and end is less than the distance threshold, so points 2 and 3 are discarded. In the "point 4 to point 8" segment, the distance from each middle point to the line connecting points 4 and 8 is recalculated. It is found that the distance of point 6 is the largest and exceeds the distance threshold, so point 6 is retained (and points 5 and 7 are pending).

[0042] S13: Subsequently, as Figure 4 As shown, the algorithm continues to iterate on the new sub-segment segmented by point 6. In the segment from point 6 to point 8, point 7 is identified as having a distance greater than the distance threshold and is retained, while point 5 in the segment from point 4 to point 6 is discarded due to insufficient distance.

[0043] S14: Finally, as Figure 5 As shown, after multiple rounds of iterative simplification, the original sequence of 8 coordinate points was reduced to a sequence of key coordinate points consisting of points 1, 4, 6, 7, and 8, thus completing the feature extraction of the outline of the graphic unit.

[0044] In integrated circuit layout classification tasks, graphic units typically exhibit Manhattan geometry with strict right angles or specific angles. Layout classification is essentially based on matching their topological structure, and the core carriers of this topology are the various inflection points. The Douglas-Pock algorithm, based on recursive filtering using maximum vertical distance, possesses inherent inflection point sensitivity. Regardless of how uneven the distribution of inflection points is, as long as a point constitutes a significant turning point in the graphic, the Douglas-Pock algorithm ensures its preservation. Therefore, for layout classification, the Douglas-Pock algorithm can generate the most representative "skeleton," which is the geometric foundation for accurate classification. Furthermore, the challenge of integrated circuit layout classification lies in retaining minute features (such as intentionally designed tiny grooves or polarity marks) while ignoring the effects of process noise (e.g., minor jitter caused by lithography corrections and mesh adhesion errors). The Douglas-Pock algorithm sets a distance threshold linked to process precision. Fluctuations smaller than the threshold are considered noise and ignored, while protrusions larger than the threshold are considered structural features and strictly preserved. This allows it to eliminate process error interference while accurately capturing subtle structural differences that determine the classification result. Furthermore, the Douglas-Pock algorithm is globally (or piecewise globally) optimal; its simplification result depends primarily on the overall macroscopic shape of the image rather than the density of local points. Therefore, it can uniformly map various images with different data representations but essentially the same shape into a unique, standardized sequence of key coordinates. This determinism and uniqueness of the output is a prerequisite for subsequent high-precision hash classification and deduplication of massive amounts of data.

[0045] S2: Based on the preset grid step size, map each key coordinate point to the corresponding grid point in its grid to obtain the aligned grid point coordinates.

[0046] This step essentially involves discretizing and normalizing the feature-extracted graphic data. Its core purpose is to establish a spatial tolerance mechanism that allows maps with highly similar physical shapes but subtle differences in coordinates to be identified as belonging to the same category. Mapping refers to calculating the landing point (projection point) of each key coordinate point in the virtual grid coordinate system based on a pre-set grid step size. The corresponding grid point refers to the specific reference position within the grid cell selected as the mapping target.

[0047] In one embodiment of the first aspect of this application, the corresponding grid point is: a grid point located at a fixed position within the grid, or a grid point closest to the key coordinate point.

[0048] The grid point located at a fixed orientation within the grid refers to a pre-defined fixed reference orientation (such as the lower left, upper left, or lower right corner grid point) used as the anchor point for any given grid cell. Regardless of the specific location of the key coordinate point within the grid, it will be uniformly "attracted" to the grid point with the same orientation within its grid cell. The grid point closest to the key coordinate point is determined by calculating the Euclidean distances from the key coordinate point to the four grid points within its grid cell and mapping the coordinate point to the nearest grid point.

[0049] For example, assuming the corresponding grid point is the bottom left grid point within the grid containing the key coordinate point, the process of achieving this mapping through a rounding-down strategy is as follows:

[0050] S21: First, the entire map coordinate system is divided into a grid of size n*n. It should be understood that this division does not mean that a two-dimensional array structure must be physically generated in computer memory, but rather that a virtual grid mapping mechanism based on a rounding algorithm is established for subsequent coordinate alignment calculations.

[0051] S22: Then, for any key coordinate point P(x,y), its coordinates are converted to the coordinates of the bottom left corner of its grid. The specific calculation method is as follows:

[0052] If the coordinate x is divisible by the grid step size n (x%n=0), that is, the key coordinate point falls exactly at the lower left corner of its grid, then it is directly retained or converted proportionally, and the x-coordinate of the corresponding grid point is x'=x.

[0053] If the point is not divisible and x > 0, then truncation is performed, with the formula x' = [x / n] * n ([] represents the rounding operation), which is equivalent to forcibly pulling the point back to the grid line to its left.

[0054] If the division is not exact and x < 0, in order to counteract the characteristic of computer integer division to round to zero, the alignment direction must be kept consistent, and the formula is adjusted to x' = -[-x / n]*nn.

[0055] The y-coordinate is calculated in the same way as the x-coordinate. In this way, multiple similar graphics with slightly different original coordinates will have their key coordinate points completely overlap after grid alignment, thus providing standardized input for generating consistent classification feature codes.

[0056] S3: Determine the classification result of the map to be classified based on the coordinates of each grid point.

[0057] Step S3 aims to establish a mapping relationship from geometric data to classification conclusions. After grid alignment is completed in step S2, the resulting set of grid coordinates has been normalized, establishing a spatial tolerance mechanism and removing non-essential process errors and micro-vibrations, becoming a standard geometric description that can uniquely characterize the topology of the graphic unit. Next, step S3 is used to construct categories: if the grid coordinate sets corresponding to two layouts to be classified are completely identical in number, value, and arrangement order, then the two layouts are determined to be the same in topology and should be classified into the same category; otherwise, if the coordinate sets differ, they are determined to belong to different layout patterns.

[0058] In one embodiment of the first aspect of this application, the initial coordinate point is a relative coordinate point obtained by normalizing the original coordinates of the graphic unit with reference to a specific vertex of the map to be classified.

[0059] In one embodiment of the first aspect of this application, determining the classification result of the map to be classified based on the grid coordinates of each grid point specifically includes: converting the grid coordinates of each graphic unit into coordinate strings; encoding each coordinate string based on the BKDRHash algorithm to obtain the graphic hash value corresponding to each graphic unit; and determining the classification result of the map to be classified based on the combination of all graphic hash values ​​in the map to be classified.

[0060] It should be understood that, in order to eliminate the influence of the absolute positional differences of the layout on the wafer or design drawing on the classification results, when converting the grid point coordinates corresponding to each graphic unit into coordinate strings, the initial coordinate points used are relative coordinate points obtained by normalizing the original coordinates of the graphic units with reference to a specific vertex of the layout to be classified.

[0061] For example, the system can first determine the region corresponding to the map to be classified, such as a square region, and select a specific vertex of the square region, such as the lower left vertex (x0, y0), as a reference anchor point. Then, the system will assign the absolute coordinates (x0, y0) of each original vertex on the outline of the graphic unit to the coordinates of the original vertex. i ,y i Subtracting the coordinates of the reference anchor point from the relative coordinates (x) yields the relative coordinates (x). i -x0,y i -y0). Through this coordinate translation operation, no matter where the graphic pattern appears on the chip layout, as long as its geometry and internal structure are the same, a completely consistent initial coordinate sequence can be obtained after normalization, thus realizing the translation invariance of the classification algorithm.

[0062] Subsequently, the BKDRHash algorithm is used to encode and calculate the aforementioned coordinate strings. It should be understood that BKDRHash is an extremely efficient string hashing algorithm. Its basic principle is to select a specific seed value (e.g., 31, 131, or 1313) and, through iterative multiplication and addition operations, map a string of arbitrary length to a fixed-length integer or long integer. When performing the BKDRHash algorithm, if the layout to be classified contains only one graphic unit, the graphic hash value is the classification ID of that layout. However, if the layout to be classified contains multiple graphic units (e.g., a complex circuit structure composed of multiple polygons), it is necessary to combine these independent graphic hash values ​​(e.g., sort all graphic hash values ​​by value and then concatenate them for secondary hashing, or perform a weighted sum) to generate a global hash value representing the entire layout structure. This global hash value is the final classification result, used for fast indexing and deduplication in the classification database.

[0063] Compared to other hash algorithms, BKDRHash exhibits excellent avalanche effect and low collision rate when processing coordinate strings containing a large number of numbers and separators. Even a tiny change in the coordinate string (such as a one-unit change in the coordinate value of a point) will result in a significant change in the calculated hash value. This ensures that different shapes (even with small differences) can have drastically different hash values, leading to more accurate classification results for the maps to be classified, provided that the grid coordinates are consistent.

[0064] In one embodiment of the first aspect of this application, the distance threshold is dynamically determined based on the length of the grid step.

[0065] In this embodiment, the distance threshold (T) is not a fixed preset constant, but is dynamically determined according to the length (n) of the grid step size in the grid alignment step.

[0066] When simplifying initial coordinate points using the Douglas-Pokal algorithm, if the distance threshold is set too small (T << n), a large number of minute contour undulation details will be retained. However, in the subsequent mesh alignment step, because the amplitude is smaller than the mesh step size, these details will eventually be forcibly snapped to the same grid point, resulting in a large amount of meaningless fine calculations and wasting computational resources. Conversely, if the distance threshold is set too large (T >> n), the Douglas-Pokal algorithm will oversimplify the graphic, causing effective geometric features that could be expressed by the mesh resolution (such as small steps or grooves) to be incorrectly flattened or removed, thereby reducing the accuracy of classification.

[0067] Therefore, this embodiment employs a parameter coordination strategy to establish a functional mapping relationship between the distance threshold and the grid step size. Preferably, the two are set to satisfy a linear relationship: T = k × n, where k is a proportionality coefficient, and its value range is preferably 0.5-1.0. Thus, for example, assuming n = 10 nm, k = 0.5, and T = 5 nm, any small jitter with a vertical distance less than 5 nm is considered a redundant point and is discarded during the feature extraction stage; while feature points with a distance greater than 5 nm are retained and then mapped to the 10 nm grid system.

[0068] Through this dynamic determination mechanism, the algorithm can adaptively adjust the processing precision of the front end according to the final target resolution (grid size). This not only ensures that all retained key coordinate points are valid points that substantially contribute to the final grid shape, avoiding invalid high-precision calculations, but also guarantees that the topological features of the graph are preserved to the greatest extent under a given grid precision, achieving a global optimum of computational efficiency and classification accuracy.

[0069] A second aspect of this application provides a classification system for integrated circuit layouts, comprising: a feature extraction module for identifying each graphic unit within the layout to be classified, and extracting contour features from the initial coordinate points constituting the contours of each graphic unit to obtain key coordinate points characterizing the contour structure features; a grid alignment module for mapping each key coordinate point to a corresponding grid point within its grid according to a preset grid step size to obtain aligned grid point coordinates; and a category classification module for determining the classification result of the layout to be classified based on the grid point coordinates.

[0070] It should be understood that the specific process of each module performing the above-mentioned steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0071] It should also be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0072] A third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in any of the preceding claims.

[0073] A fourth aspect of this application provides a computer program product comprising computer program code that, when executed on a computer, causes the computer to perform the method described in any of the preceding claims.

[0074] A fifth aspect of this application provides an electronic terminal including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the method described in any of the preceding claims. The electronic terminal includes at least one processor 201, a memory 202, at least one network interface 203, and a user interface 205. The various components in the device are coupled together via a bus system 204. It is understood that the bus system 204 is used to enable communication between these components. In addition to a data bus, the bus system 204 also includes a power bus, a control bus, and a status signal bus.

[0075] The user interface 205 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0076] It is understood that memory 202 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0077] In this embodiment of the invention, the memory 202 is used to store various types of data to support the operation of the electronic terminal 200. Examples of this data include: any executable program for operation on the electronic terminal 200, such as the operating system 2021 and application programs 2022; the operating system 2021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application programs 2022 may contain various applications, such as media players, browsers, etc., for implementing various application services. The methods provided in this embodiment of the invention can be included in the application programs 2022.

[0078] The methods disclosed in the above embodiments of the present invention can be applied to processor 201, or implemented by processor 201. Processor 201 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 201 or by instructions in software form. The processor 201 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 201 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 201 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0079] In an exemplary embodiment, the electronic terminal 200 may be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to execute the aforementioned method.

[0080] The terms “component,” “module,” “system,” etc., used in this specification are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0081] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0082] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0083] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0084] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0085] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0086] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs, DVDs), or semiconductor media (e.g., solid-state disks, SSDs, etc.).

[0087] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0088] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0089] In summary, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0090] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A method for classifying integrated circuit layouts, characterized in that, include: Identify each graphic unit within the map to be classified, and extract the contour features of the initial coordinate points that constitute the contour of each graphic unit to obtain the key coordinate points that characterize the contour structure features. Based on the preset grid step size, each key coordinate point is mapped to the corresponding grid point within its grid to obtain the aligned grid point coordinates. Based on the coordinates of each grid point, determine the classification result of the map to be classified; The extraction of contour features from the initial coordinate points constituting the contours of each graphic unit specifically includes: based on the Douglas-Puk algorithm, according to a preset distance threshold, iteratively simplifying the initial coordinate points corresponding to the contours of each graphic unit to obtain the key coordinate points retained after simplification of each graphic unit. The distance threshold is dynamically determined based on the length of the grid step.

2. The method for classifying integrated circuit layouts according to claim 1, characterized in that, The initial coordinate point is a relative coordinate point obtained by normalizing the original coordinates of the graphic unit with reference to a specific vertex of the map to be classified.

3. The method for classifying integrated circuit layouts according to claim 2, characterized in that, The step of determining the classification result of the map to be classified based on the coordinates of each grid point specifically includes: Convert the grid coordinates of each graphic unit into a coordinate string; Based on the BKDRHash algorithm, each of the coordinate strings is encoded to obtain the graphic hash value corresponding to each graphic unit; The classification result of the map to be classified is determined based on the combination of all graphic hash values ​​within the map to be classified.

4. The method for classifying integrated circuit layouts according to claim 1, characterized in that, The corresponding grid point is: a grid point located in a fixed position within the grid, or the grid point closest to the key coordinate point.

5. A classification system for integrated circuit layouts, characterized in that, include: The feature extraction module is used to identify each graphic unit within the map to be classified, and to extract the contour features of the initial coordinate points that constitute the contour of each graphic unit in order to obtain the key coordinate points that characterize the contour structure features. The grid alignment module is used to map each key coordinate point to the corresponding grid point in its grid according to the preset grid step size to obtain the aligned grid point coordinates. The category division module is used to determine the classification result of the map to be classified based on the coordinates of each grid point.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1-4.

7. A computer program product, characterized in that, The computer program product includes computer program code that, when run on a computer, causes the computer to implement the method as described in any one of claims 1-4.

8. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the method according to any one of claims 1-4.

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