A GaN-based vertical cavity surface emitting laser with a flat-concave cavity structure and a preparation method thereof

Abstract

The application discloses a kind of flat concave cavity structure GaN base vertical cavity surface emitting laser and preparation method. Among them, the laser adopts the structure of setting lower concave DBR mirror in p side, it includes successively from lower to upper along light emitting direction: a substrate;Lower concave DBR mirror, the substrate is supported in the lower of the lower concave DBR mirror;SiO2 transition layer, covers the upper surface of the lower concave DBR mirror;And sequentially arranged ohmic contact layer, current limiting layer, p-type semiconductor layer, multi-quantum well active region, n-type semiconductor layer, n-side contact electrode and upper flat DBR mirror.The preparation process of the device structure of the application is more stable and reliable to some extent, and the yield of the device can be effectively improved;In addition, the application also provides a cheaper alternative for the epitaxial substrate of the GaN base flat concave cavity structure vertical cavity surface emitting laser.

Description

Technical Field

[0001] This invention relates to the field of vertical cavity surface-emitting laser technology, and in particular to a GaN-based vertical cavity surface-emitting laser with a plano-concave cavity structure and its fabrication method. Background Technology

[0002] GaN-based vertical-cavity surface-emitting lasers (VCSELs) are semiconductor lasers based on GaN materials and employing a vertical-cavity surface-emitting structure. Their core structure consists of upper and lower vertically oriented beam backlights (DBRs) and a central InGaN / GaN multi-quantum-well active region, enabling laser emission perpendicular to the substrate direction. Benefiting from the excellent properties of GaN's wide bandgap, this device can theoretically operate in the deep ultraviolet to infrared bands through doping, making it particularly suitable for high-brightness, high-efficiency visible light emission. Compared to edge-emitting lasers, it offers advantages such as a circularly symmetrical beam, low threshold current, ease of two-dimensional integration, and good process compatibility, making it a promising candidate for applications in high-speed visible light communication, laser displays, biosensing, and solid-state lighting.

[0003] Based on the top and bottom DBR structures of the device, the main types of GaN-based vertical cavity surface-emitting lasers are currently the dual-planar DBR and planar DBR structures. The high-reflectivity band of the dual-planar DBR structure is extremely sensitive to the incident angle of light. In an ideal parallel planar cavity, only light rays with a propagation direction absolutely perpendicular to the mirror surface can be efficiently reflected. Furthermore, the dual-planar structure provides almost no effective optical confinement mechanism in the direction parallel to the substrate (lateral direction), and in the fabrication process, a forward waveguide structure at the aperture is usually designed to achieve lateral confinement of light. The planar-concave DBR structure, on the other hand, significantly improves upon these aspects, resulting in a resonant cavity with lower lateral loss and stronger optical performance.

[0004] The first GaN-based vertical-cavity surface-emitting laser (DBR) structure was proposed by Sony Corporation of Japan in 2015. It involves epitaxial growth of GaN material on a single-crystal substrate and etching GaN on the n-side to fabricate a concave mirror. This method requires thinning the substrate from hundreds of micrometers to tens of micrometers during the n-side processing. To ensure device stability, temporary bonding is used on the p-side to support the wafer, which can lead to potential damage to the device during subsequent debonding processes. Furthermore, GaN single-crystal epitaxial wafers are very expensive, making them costly for commercial applications. Summary of the Invention

[0005] To address the aforementioned issues, this invention proposes a novel GaN-based plano-concave vertical-cavity surface-emitting laser (VCSEL) with a unique structure. This structure eliminates the need for temporary bonding processes to transfer the substrate, simplifying the fabrication process and improving its stability. Electroplated copper is introduced as the permanent substrate, leveraging its high thermal conductivity to achieve superior heat dissipation. Furthermore, this invention utilizes a CVD deposition of a SiO2 transition layer, upon which a curved DBR is fabricated. This allows for cavity length control while simultaneously enabling the fabrication of the plano-concave VCSEL using inexpensive sapphire epitaxial wafers.

[0006] According to one aspect of the present invention, a GaN-based vertical cavity surface-emitting laser with a plano-concave cavity structure is provided. The laser employs a structure in which a concave DBR mirror is disposed on the p-side, and comprises, from bottom to top, the following components along the light emission direction:

[0007] A substrate;

[0008] A concave DBR reflector, wherein the substrate is supported below the concave DBR reflector;

[0009] A SiO2 transition layer is applied to the upper surface of the concave DBR reflector.

[0010] In addition, the following are arranged in sequence: ohmic contact layer, current limiting layer, p-type semiconductor layer, multi-quantum well active region, n-type semiconductor layer, n-side contact electrode and upper plane DBR reflector.

[0011] In the above technical solution, the laser adopts a structural layout in which a concave DBR mirror is placed on the p-side. Along the light emission direction, a substrate, a concave DBR mirror, a SiO2 transition layer, and an epitaxial functional layer region consisting of an ohmic contact layer, a current-limiting layer, a p-type semiconductor layer, a multi-quantum-well active region, an n-type semiconductor layer, an n-side contact electrode, and a top-plane DBR mirror are stacked sequentially. The substrate is supported below the concave DBR mirror, and the SiO2 transition layer covers the upper surface of the concave DBR mirror, forming a flat substrate to support the subsequent epitaxial layers. This structure simultaneously performs multiple functions in the entire device, including optical resonator construction, p-side electrode contact, and mechanical support, and forms the basic framework of the technical solution of this invention.

[0012] The essential feature of this technology is that the concave DBR mirror is placed on the p-side and integrated with the epitaxial functional layer through the SiO2 transition layer. This construction method is significantly different from the n-side concave mirror scheme commonly used in the prior art.

[0013] First, placing the concave DBR on the p-side alters the traditional fabrication path of planar-concave cavity VCSELs. In existing technologies, concave mirrors are typically fabricated on the n-side, requiring etching of n-GaN. This necessitates temporary bonding on the p-side to support the wafer before subsequent n-side processes (such as substrate thinning and polishing), resulting in complex procedures and potential damage. This new technology, by transferring the concave mirror to the p-side, allows for substrate removal only after all p-side structures (including the concave DBR, transition layer, and electrodes) are completed, completely avoiding the temporary bonding process. This significantly simplifies the fabrication process and improves process stability and device yield.

[0014] Secondly, the introduction of the SiO2 transition layer provides a feasible path for the fabrication of the p-side concave DBR. The positional relationship of this transition layer covering the upper surface of the concave DBR allows the concave DBR to be embedded in the bottom of the device without affecting the flatness of the upper structure, thus achieving decoupling between the optical surface and the semiconductor epitaxial plane.

[0015] Furthermore, the direct support of the substrate beneath the concave DBR in the stacked structure eliminates the need for additional connecting layers or bonding interfaces between the concave DBR and the substrate, facilitating vertical heat conduction. When a high thermal conductivity material is selected for the substrate, a direct heat conduction path can be formed from the active region through the p-type layer and DBR to the substrate, improving the device's thermal management performance.

[0016] The above features together bring the following benefits: ① Simplify the process and reduce manufacturing costs; ② Improve device consistency and reliability; ③ Provide an engineering-feasible implementation scheme for the p-side concave mirror structure; ④ Reserve the structural foundation for device heat dissipation optimization.

[0017] This technical feature forms the core structural basis of the present invention. By placing the concave DBR on the p-side and introducing a SiO2 transition layer, it systematically solves the problems of complex processes and limited yield in the fabrication of existing plano-concave cavity GaN-based VCSELs. This structure not only provides a feasible path for the fabrication of p-side concave mirrors, but also optimizes the device's thermal management path through the stacking relationship. Together with subsequent cavity length adjustment, electrode placement, and other technical means, it supports the invention's objective of achieving a low-cost, high-reliability, and high-performance plano-concave cavity VCSEL.

[0018] In some embodiments, the radius of curvature R of the concave DBR mirror and the effective cavity length L of the plano-concave resonant cavity satisfy the plano-concave cavity stability condition, and their ratio is configured to form a diffraction-limited spot at the light-emitting surface of the upper plano DBR mirror.

[0019] The above technical solution further defines the optical design parameters of the plano-concave resonator in this invention. Specifically, the radius of curvature R of the concave DBR mirror and the effective cavity length L of the plano-concave resonator must satisfy two levels of conditions: First, both must meet the basic stability conditions of the plano-concave cavity to ensure that the beam inside the cavity can oscillate stably without escaping outside the cavity; second, the ratio between the two is configured so that a diffraction-limited spot can be formed at the light-emitting surface of the upper planar DBR mirror. This parameter design plays a core role in optimizing the light field distribution and improving the light-emitting performance in the device structure.

[0020] The essential feature of this technology is that it not only meets the stability requirements of the plano-concave cavity, but also further configures the ratio of the radius of curvature R to the cavity length L as a specific condition for achieving the diffraction-limited spot. This design is significantly different from the existing technology that only focuses on the stability of the cavity.

[0021] First, the stability condition of the plano-concave cavity is the basic premise for the resonant cavity to work. It only ensures that the beam does not scatter laterally during the round trip in the cavity, but does not optimize the beam size and energy distribution.

[0022] Secondly, configuring the proportional relationship to form a diffraction-limited spot at the output surface implies that this design aims for the minimum beam waist radius in the fundamental transverse mode (TEM00). According to Gaussian beam theory, when a diffraction-limited spot is obtained at the output surface, the beam cross-sectional radius at that location reaches its theoretical minimum, and the peak power density is inversely proportional to the square of the beam waist radius. Therefore, a higher output power density can be achieved with the same total power. This effect is of great significance for the practical application of VCSEL devices, such as improving coupling efficiency in optical communication and improving beam quality in laser displays.

[0023] Furthermore, this parameter configuration provides a clear optical basis for determining the SiO2 transition layer thickness. The effective cavity length L is jointly determined by factors such as the SiO2 transition layer thickness and the n-type semiconductor layer thickness, while the radius of curvature R is determined by the surface shape beneath the transition layer. Locking the ratio between the two to the conditions for forming a diffraction-limited spot effectively establishes a quantifiable optical target for the design of each layer thickness, which helps improve the first-pass success rate and performance consistency of device design.

[0024] The above features together bring the following beneficial effects: ① Maximize the power density at the light-emitting surface and improve the optical output performance of the device; ② Optimize the beam quality and obtain a light spot with a near-ideal Gaussian distribution; ③ Provide an optical theoretical basis for the design of each layer thickness and reduce the development and iteration costs; ④ Obtain higher output power at the same threshold current, or reduce the threshold current at the same output power.

[0025] This technology achieves the optical goal of forming a diffraction-limited spot at the light-emitting surface by configuring the ratio of the radius of curvature to the cavity length. This not only improves the device's output power density and beam quality but also provides quantifiable optical data for designing process parameters such as the SiO2 transition layer thickness.

[0026] In some embodiments, the thickness of the SiO2 transition layer is configured such that the effective cavity length L and the radius of curvature R satisfy a proportional relationship for forming a diffraction-limited spot.

[0027] In the above technical solution, the configuration relationship between the SiO2 transition layer thickness and the optical parameters of the resonant cavity is defined. Specifically, the thickness of the SiO2 transition layer is not arbitrarily selected, but configured so that the effective cavity length L of the plano-concave resonant cavity and the radius of curvature R of the concave DBR mirror satisfy a proportional relationship that allows for the formation of a diffraction-limited spot. This transition layer plays multiple roles in the structure of this invention: its lower surface supports the concave DBR, its upper surface provides a planar substrate for the epitaxial layer, and its own thickness participates in the optical design of the resonant cavity as an important component of the effective cavity length L.

[0028] The essential feature of this technology is that it directly links the thickness setting of the SiO2 transition layer with the optical target of the resonant cavity (forming a diffraction-limited spot), so that the selection of the process parameters of this layer has a clear optical basis. This design concept is significantly different from the existing technology that only uses the spacer layer to roughly adjust the cavity length or planarize the process.

[0029] First, the SiO2 transition layer thickness is a crucial component of the effective cavity length L, and its value determines the proportional relationship between L and R. While existing technologies employ spacer layers to adjust the cavity length, their thickness selection is typically based on ease of fabrication or coarse longitudinal mode matching, without establishing a quantitative correlation between the thickness setting and the optical objective of "forming a diffraction-limited spot at a specific location." This technology configures the transition layer thickness to achieve this objective proportionally, meaning that determining this thickness requires systematic optical calculations considering factors such as the radius of curvature R and the n-type semiconductor layer thickness, rather than simple empirical values.

[0030] Secondly, this thickness configuration upgrades the SiO2 transition layer from a simple "structural layer" to an "optical tuning layer." It not only provides fabrication feasibility for p-side concave DBRs but also actively participates in mode modulation of the resonant cavity through the setting of thickness parameters. When L and R satisfy the proportional relationship for forming a diffraction-limited spot, the beam waist radius at the light-emitting surface reaches its theoretical minimum, maximizing the power density. The realization of this effect is highly dependent on the configuration of the transition layer thickness.

[0031] Furthermore, this technical feature provides a unified optimization framework for device design under different substrate types. For sapphire substrates (thinner n-GaN) and GaN single-crystal substrates (thicker n-GaN), although the n-type layer thickness differs, the total cavity length L can be matched with a given radius of curvature R by adjusting the SiO2 transition layer thickness, ultimately converging towards the target diffraction-limited spot. This design flexibility of compensating for n-type layer differences through transition layer thickness expands the applicability of the technical solution of this invention.

[0032] The above features collectively bring the following beneficial effects: ① Incorporating the setting of the transition layer thickness into the core of optical design; ② Providing clear theoretical guidance for process parameters and reducing trial and error costs; ③ Enabling the same concave mirror design (fixed R) to be adapted to epitaxial wafers with different n-type layer thicknesses, enhancing process compatibility; ④ Ensuring the maximization of power density at the light-emitting surface and improving the practical value of the device.

[0033] This technical feature, by linking the thickness setting with the ratio of diffraction-limited spot formation, not only endows the transition layer with the function of actively tuning the resonant cavity mode, but also provides a unified optimization path for device design under different substrate types. This design concept forms an organic synergy with the p-side concave mirror construction scheme of this invention—the former provides structural feasibility, while the latter ensures optical optimization through thickness configuration. Together, they support the invention's objective of achieving a high-performance, predictable, and highly adaptable plano-concave cavity GaN-based VCSEL.

[0034] In some embodiments, the substrate is made of a conductive and thermally conductive material, and a metal seed layer is provided between it and the concave DBR reflector. The thickness of the substrate is 150-300 micrometers.

[0035] The above technical solution further defines the specific implementation of the substrate in this invention. Specifically, the substrate is made of a conductive and thermally conductive material with a thickness of 150-300 micrometers; simultaneously, a metal seed layer is disposed between the substrate and the concave DBR mirror. This substrate structure performs multiple functions in the entire device: it serves as a mechanical support substrate to support the entire epitaxial structure, provides p-side electrode contact as an electrical pathway, and acts as a heat diffusion layer to dissipate heat generated in the active region. The thickness range is chosen to balance mechanical strength and thermal resistance. The metal seed layer is located between the substrate and the DBR, serving both as a growth substrate during substrate formation and as the electrical and thermal coupling interface between the DBR and the substrate.

[0036] The essential feature of this technology lies in the systematic and comprehensive design of the substrate's material properties, thickness range, and interface layer structure with the DBR. This integrated approach is significantly different from the existing technology that treats the substrate merely as a mechanical support or focuses only on a single performance.

[0037] First, the substrate is made of a conductive and thermally conductive material, giving it both electrical and thermal functions. In existing GaN-based VCSELs, common substrate materials such as sapphire provide good epitaxial matching, but their thermal conductivity is poor (approximately 35 W / (m·K)) and they are non-conductive, requiring the fabrication of electrodes separately. This technology utilizes conductive and thermally conductive materials (such as copper, aluminum, and diamond-copper composites), allowing the substrate to directly participate in the device's electrical circuit while simultaneously serving as a highly efficient heat diffusion layer, rapidly dissipating and laterally diffusing heat generated in the active region. Compared to sapphire substrates, the thermal conductivity can be improved by more than an order of magnitude, significantly improving the device's thermal management capabilities and ensuring continuous wave operation and high-power output.

[0038] Secondly, the 150-300 micrometer thickness range was not chosen arbitrarily, but rather is the result of optimization based on multiple engineering considerations. Too thin a substrate (e.g., below 150 micrometers) may lead to insufficient mechanical strength, making it prone to warping or cracking during subsequent processes or device use; too thick a substrate (e.g., exceeding 300 micrometers) will increase thermal resistance, reduce heat dissipation efficiency, and increase material costs and processing time. The 150-300 micrometer range strikes a balance between mechanical support strength, heat conduction path length, and process operability, reflecting a comprehensive consideration of device reliability and performance.

[0039] Furthermore, the metal seed layer placed between the substrate and the concave DBR has crucial structural and technological significance. The concave DBR is composed of a dielectric film, and its surface is non-conductive, making direct electroplating or electrochemical deposition of the substrate impossible. The introduction of this metal seed layer solves this technological obstacle: on the one hand, it provides a conductive substrate for subsequent substrate formation (such as electroplating, electroless plating, etc.); on the other hand, it remains in the device as a permanent structure, acting as the electrical and thermal coupling interface between the DBR and the substrate, reducing interface thermal resistance and contact resistance. This "seed layer as functional layer" design avoids the cumbersome step of removing the temporary seed layer after processing, simplifying the process flow and improving interface quality.

[0040] The above features collectively bring the following beneficial effects: ① Significantly improves device heat dissipation capacity and enhances thermal management performance; ② The substrate directly participates in the electrical circuit, simplifying electrode design; ③ The optimized thickness range balances mechanical reliability and thermal performance; ④ The metal seed layer simultaneously meets process requirements and permanent structural functions, reducing interface losses; ⑤ The overall structural design lays the foundation for the application of high-power, high-reliability devices.

[0041] This technology systematically solves problems such as heat dissipation bottlenecks, complex processes, and interface losses in traditional GaN-based VCSELs by selecting conductive and thermally conductive materials, optimizing thickness, and introducing a metal seed layer.

[0042] In some embodiments, both the concave DBR mirror and the flat DBR mirror are composed of alternating stacks of two dielectric films with different refractive indices.

[0043] The above technical solution further defines the specific configuration of the upper and lower DBR reflectors in this invention. Specifically, both the concave DBR reflector and the flat DBR reflector are composed of alternating stacks of two dielectric films with different refractive indices. These DBR reflectors play a core role in constructing the resonant cavity in the structure of this invention: the concave DBR and the flat DBR together form a plano-concave resonant cavity, providing feedback for the light generated in the active region; simultaneously, the refractive index difference between the two materials, the number of stacking periods, and the thickness of a single layer jointly determine the reflection bandwidth and reflectivity of the reflectors, directly affecting the threshold characteristics and operating wavelength of the laser. This technical feature represents a further refinement of the optical resonant cavity reflector structure of this invention.

[0044] The essential feature of this technology lies in the use of a DBR structure made of all dielectric materials, which is significantly different from the schemes that use semiconductor materials or metal mirrors. At the same time, its combination with the specific plano-concave cavity configuration of this invention produces a synergistic technical effect.

[0045] First, by alternating stacks of two dielectric films with different refractive indices, high reflectivity can be achieved within a specific wavelength range. Compared to metal mirrors (which have limited reflectivity and suffer from absorption losses), dielectric DBRs can achieve near 100% reflectivity with extremely low absorption losses, which is crucial for reducing the threshold current of VCSELs. Compared to semiconductor DBRs (such as GaN / AlGaN material pairs), dielectric DBRs offer greater flexibility in material selection, allowing for a larger refractive index difference. Therefore, the same reflectivity can be achieved with fewer stacking cycles, which is beneficial for reducing the overall film thickness.

[0046] Secondly, this dielectric DBR structure has good process compatibility with the p-side concave mirror configuration of this invention. The concave DBR needs to be deposited on the curved surface of the SiO2 transition layer, while the dielectric film (such as TiO2 / SiO2, HfO2 / SiO2, etc.) can achieve good conformal coverage through electron beam evaporation, sputtering, etc., forming a film layer of uniform thickness on the curved surface, ensuring the optical quality of the concave mirror. If a semiconductor DBR is used, it is difficult to perform high-quality epitaxial growth on the amorphous SiO2 curved surface, significantly increasing the difficulty of process implementation.

[0047] Furthermore, the refractive index of dielectric materials is relatively insensitive to temperature changes, which helps improve the operational stability of devices. Under continuous wave operation or high-power injection conditions, heating in the active region may cause changes in the refractive index of semiconductor materials, leading to resonant wavelength drift. Dielectric DBRs have better thermal stability than semiconductor DBRs, effectively suppressing wavelength drift with temperature and improving the temperature adaptability of devices.

[0048] Furthermore, the material selection and film design of dielectric DBRs offer high flexibility. Depending on the target emission wavelength (e.g., blue, green, ultraviolet), different combinations of high and low refractive index materials can be selected, and the single-layer optical thickness can be precisely controlled to λ / 4, thereby achieving optimized design for specific wavelengths. This tunability allows the technical solution of this invention to adapt to different application scenarios, expanding its applicability.

[0049] The above characteristics together bring the following beneficial effects: ① Achieving resonant cavity feedback with high reflectivity and low absorption loss, reducing threshold current; ② Good compatibility with p-side curved surface structure, ensuring the optical quality of concave mirror; ③ Improving the operating stability and temperature adaptability of the device; ④ Achieving optimized configuration for different wavelengths through material selection and film design.

[0050] This technology combines the general construction method of dielectric DBR with the specific plano-concave cavity configuration of this invention, realizing a resonant cavity feedback system with high reflectivity, low loss, and temperature stability. The material flexibility and process compatibility of dielectric DBR allow it to be perfectly adapted to the curved surface structure of the p-side concave mirror, while providing adjustable design space for applications of different wavelengths.

[0051] According to another aspect of the present invention, a method for fabricating a GaN-based vertical-cavity surface-emitting laser with a plano-concave cavity structure is provided, comprising the following steps:

[0052] An n-type semiconductor layer, a multi-quantum-well active region, and a p-type semiconductor layer are sequentially epitaxially grown on an epitaxial substrate, and a current-limiting layer and an ohmic contact layer are fabricated on the p-type semiconductor layer.

[0053] A SiO2 transition layer is deposited on the surface of the ohmic contact layer; a curved mask is prepared on the surface of the SiO2 transition layer, and the curved mask is etched to transfer the curved shape to the SiO2 transition layer, so that the surface of the SiO2 transition layer forms a curved structure.

[0054] A DBR dielectric film is deposited on the surface of the curved structure to form a concave DBR reflector;

[0055] A permanent substrate is prepared on the surface of the concave DBR mirror.

[0056] Remove the epitaxial substrate to expose the n-type semiconductor layer;

[0057] An n-side contact electrode and an upper-plane DBR reflector are fabricated on the exposed n-type semiconductor layer surface.

[0058] The above technical solution provides a complete fabrication method for the GaN-based vertical-cavity surface-emitting laser with a plano-concave cavity structure according to the present invention. This method starts with epitaxial growth and constructs a concave mirror on the p-side through a series of process steps to ultimately form a complete device. The specific process includes: sequentially growing an n-type semiconductor layer, a multi-quantum-well active region, and a p-type semiconductor layer on an epitaxial substrate, and fabricating a current-limiting layer and an ohmic contact layer; depositing a SiO2 transition layer on the surface of the ohmic contact layer; fabricating a curved mask on the surface of the transition layer and etching to form a curved structure; depositing a DBR dielectric film on the curved structure to form a concave DBR mirror; fabricating a permanent substrate on the surface of the concave DBR; removing the original epitaxial substrate to expose the n-type semiconductor layer; and finally fabricating a planar DBR mirror on the surface of the n-type layer. This method serves as the core implementation path in the present invention, transforming the aforementioned device structure from design to physical object, with strict timing dependencies and logical connections between each step.

[0059] The essential feature of this technology lies in shifting the fabrication of concave mirrors from the traditional n-side to the p-side, and building a complete process chain around this core concept. This methodological innovation is significantly different from the n-side etching scheme commonly used in existing technologies.

[0060] First, this method avoids the temporary bonding process in existing technologies through a workflow design of "epitaxy first, then etching, and finally substrate transfer." In traditional n-side concave mirror solutions, a temporary bonding layer needs to be fabricated on the p-side to support the wafer before thinning and concave etching of the n-side can be performed. Subsequent debonding is also required, resulting in numerous process steps that are prone to damage. This method places the concave mirror fabrication before the p-side process. After completing all p-side structures (including SiO2 transition layer etching and DBR deposition), the original substrate is removed. Throughout the entire process, the wafer is always supported by the original substrate or a subsequently fabricated permanent substrate, eliminating the need for any temporary bonding steps. This simplified process path directly improves process stability and product yield.

[0061] Secondly, the introduction of the SiO2 transition layer and its surface treatment are the core technological innovations of this method. After the transition layer is deposited on the surface of the ohmic contact layer, a curved structure is formed through "curved mask preparation + etching transfer". This process has multiple functions: First, as an etchable material, SiO2 facilitates precise control of the radius of curvature of the arched curved surface formed by photoresist thermal reflow; second, the etched SiO2 curved surface provides a conformal covering substrate for subsequent DBR deposition, ensuring the optical quality of the concave DBR. This "one-time deposition, etching shaping" design realizes the integration of process steps.

[0062] Furthermore, the method's compatibility with substrate types demonstrates its process adaptability. In the step of removing the original epitaxial substrate, different removal methods can be selected depending on the substrate type—laser lift-off is used for sapphire substrates, while grinding and CMP polishing are used for GaN single-crystal substrates. This differentiated process design allows the same core process to be adapted to epitaxial wafers of different costs and application scenarios, supporting both low-cost sapphire substrate solutions and high-performance GaN homoepitaxial solutions, thus expanding the applicability of this invention.

[0063] Furthermore, the fabrication of the permanent substrate is placed at the end of the p-side processes. Fabricating the permanent substrate after completing all p-side fine structures (especially the concave DBR) avoids damage to the formed concave mirror structure by subsequent processes. At the same time, the material and process of the permanent substrate can be selected as needed (such as electroplated copper, bonding high thermal conductivity substrates, etc.), leaving room for optimization of device thermal management.

[0064] The above features collectively bring the following benefits: ① Eliminating temporary bonding processes, simplifying the process and improving yield; ② Achieving precise fabrication and multifunctional integration of curved mirrors through the SiO2 transition layer; ③ Compatibility with sapphire and GaN substrates, lowering the application threshold; ④ Process sequence design protects the fine structure and reserves space for heat dissipation optimization; ⑤ Forming a complete, efficient, and reliable plano-concave cavity VCSEL fabrication solution.

[0065] This fabrication method closely revolves around the core inventive concept of "setting the concave DBR on the p-side," constructing a complete process path from epitaxial growth to final device formation. Through the surface treatment of the SiO2 transition layer, the subsequent fabrication of the permanent substrate, and differentiated substrate removal schemes, this method systematically solves the problems of complex processes, limited yield, and high costs in existing technologies.

[0066] In some embodiments, a curved mask is prepared on the surface of the SiO2 transition layer, and etching is performed using the curved mask to transfer the curved shape to the SiO2 transition layer, thereby forming a curved structure on the surface of the SiO2 transition layer, including:

[0067] Photoresist is coated on the surface of the SiO2 transition layer. The photoresist is reflowed to form an arched surface through photolithography and high-temperature post-baking processes. After etching to form the surface, the SiO2 surface is protected with photoresist. BOE is used for wet etching to expose the ohmic contact layer outside the photoresist area for subsequent p-side ohmic contact.

[0068] The radius of curvature of the arched surface is determined by the thickness of the photoresist and the diameter of the pattern.

[0069] The above technical solution further defines the specific process implementation of the curved structure formation in the preparation method of the present invention. Specifically, in the process of preparing a curved mask on the surface of the SiO2 transition layer and etching it to form a curved structure, the following operations are adopted: first, photoresist is coated on the surface of the SiO2 transition layer, and then the photoresist is reflowed to form an arched curved surface through photolithography and high-temperature post-baking processes; the radius of curvature of the arched curved surface is determined by the thickness of the photoresist and the diameter of the pattern. This process step plays the role of converting the theoretically designed curved surface parameters (radius of curvature R) into the actual structure in the overall preparation process of the present invention.

[0070] The essential feature of this technology lies in the use of "photoresist thermal reflow" as a self-forming technique to construct a curved mask, and the mask shape is transferred to the SiO2 transition layer through etching. This technical approach is significantly different from the existing technologies that use grayscale lithography, electron beam direct writing, or direct etching of GaN to form curved surfaces.

[0071] First, the photoresist reflow process utilizes the fluidity of photoresist at high temperatures, allowing it to naturally form a smooth, arched surface under surface tension. This self-forming characteristic offers significant process simplification and cost advantages compared to methods like grayscale lithography, which require complex mask designs. Grayscale lithography necessitates specially designed masks with gradient transmittance, resulting in high equipment requirements and process complexity; while this technology only requires conventional lithography equipment and a high-temperature oven to obtain a continuous curved surface with excellent optical quality, significantly lowering the technical barrier to curved mirror fabrication.

[0072] Secondly, this process provides precise control over the radius of curvature. The radius of curvature is determined by two process parameters: the initial thickness of the photoresist and the pattern diameter. This relationship provides designers with a clear control dimension. Given a pattern diameter, the radius of curvature can be independently adjusted by changing the photoresist coating thickness; conversely, given a thickness, it can be adjusted by changing the photolithographic pattern size. This dual-parameter control mechanism allows for high process tolerance and repeatability in setting the radius of curvature, facilitating precise matching with the aforementioned optical design goals (such as the specific R-value required to form a diffraction-limited spot).

[0073] Furthermore, this process exhibits excellent compatibility with the material properties of the SiO2 transition layer. The curved surface formed by photoresist reflow is transferred to the SiO2 layer through subsequent etching steps. SiO2, as a common dielectric material, boasts mature etching technology and excellent etching selectivity, enabling high-fidelity replication of the photoresist surface morphology. Compared to directly etching the curved surface on GaN (which requires consideration of crystal orientation and etching rate anisotropy), this approach performs morphology transfer on the amorphous SiO2 material, avoiding the influence of crystal orientation on the surface shape and obtaining an optical surface closer to the ideal design.

[0074] Furthermore, the arrangement of this process step within the overall fabrication process is engineeringly sound. The preparation and etching of the curved mask occur after the deposition of the ohmic contact layer and before the deposition of the DBR. At this point, the wafer is still supported by the original substrate, providing sufficient mechanical strength to withstand photolithography, etching, and other process steps. Simultaneously, the formed SiO2 curved surface directly serves as the substrate for subsequent DBR deposition, avoiding the deformation risks associated with transferring or bonding the curved structure after its completion.

[0075] The above characteristics collectively bring the following beneficial effects: ① Achieving high-quality optical surfaces with low-cost and high-yield processes; ② Precisely controllable radius of curvature, facilitating alignment with optical design goals; ③ Avoiding the complexity and anisotropy issues of direct GaN etching; ④ Reasonable process step sequence, ensuring the integrity and stability of the surface structure; ⑤ Providing an engineering-feasible technical path for the mass production of p-side concave mirrors.

[0076] This technology utilizes a two-step process of "photoresist forming + etching transfer" to achieve a surface structure construction scheme with precise controllable radius of curvature, low process cost, and good material compatibility. This feature is organically linked to the aforementioned optical parameter design (the ratio of R to L) of this invention—the former provides the process means to achieve a specific R value, while the latter provides the optical theoretical basis for the selection of the R value.

[0077] In some embodiments, the epitaxial substrate is a sapphire substrate, and the sapphire substrate is removed using a laser lift-off process.

[0078] The above technical solution further specifies the specific removal method for the sapphire epitaxial substrate in the preparation method of the present invention. Specifically, when the epitaxial substrate is sapphire, it is removed using a laser lift-off process. This step plays the role of transferring the epitaxial structure from the growth substrate to the permanent substrate in the overall preparation process of the present invention, and is located after the preparation of all structures on the p-side (including the SiO2 transition layer surface, the concave DBR mirror, the permanent substrate, etc.) and before the preparation of the n-side electrode and the upper plane DBR. This timing arrangement and process selection constitute the complete technical solution of the present invention for sapphire substrate epitaxial wafers.

[0079] The essential feature of this technology lies in combining the laser lift-off process with the specific p-side concave mirror structure of this invention to achieve substrate transfer at a specific process node.

[0080] First, the laser lift-off process utilizes a high-energy pulsed laser to irradiate the GaN / sapphire interface through sapphire, causing the GaN at the interface to decompose into Ga and N2, thereby achieving separation of the two. This process has advantages such as high selectivity, non-contact operation, and minimal sample damage. Compared with traditional mechanical grinding and polishing, laser lift-off avoids physical damage and stress introduction to the n-type GaN layer; compared with wet etching, it avoids the potential corrosion of the device structure by chemical reagents. These advantages are particularly important for the plano-cavity structure of this invention—the n-type GaN layer will ultimately serve as the substrate for the light exit surface and the upper planar DBR, and its surface quality directly affects the mirror performance and beam quality.

[0081] Secondly, the placement of laser lift-off within the process sequence of this invention is of great significance. This step occurs after all p-side structures (especially the concave DBR and the permanent substrate) have been fabricated, at which point the device is adequately mechanically supported by the permanent substrate. The instantaneous high-pressure gas and thermal effects generated at the interface during laser lift-off can impact the thin-layer structure, while the presence of the permanent substrate effectively absorbs and disperses these stresses, protecting the fine curved surface structure on the p-side. If laser lift-off is performed before the permanent substrate is fabricated, only a few micrometers of epitaxial layer provides support, which can easily lead to fragmentation or cracks.

[0082] Furthermore, while sapphire substrate epitaxial wafers offer a significant cost advantage over GaN single-crystal substrates, their opacity and poor thermal conductivity prevent them from being used as final device substrates. The introduction of laser lift-off technology makes sapphire substrates removable, allowing for the utilization of low-cost epitaxy while ultimately achieving a device structure supported by a high thermal conductivity permanent substrate. This combination of "low-cost epitaxy + high-performance substrate transfer" effectively balances performance and cost, paving a feasible path for the commercial application of plano-cavity GaN-based VCSELs.

[0083] In addition, the n-type GaN surface exposed after laser lift-off usually has good flatness, which allows for direct deposition of the top plane DBR without the need for complex replanarization, simplifying subsequent processes and reducing the risk of interface defects introduced by additional processing, which is beneficial for obtaining high-quality n-side mirrors.

[0084] The above features together bring the following beneficial effects: ① achieving efficient and low-damage removal of sapphire substrates; ② working synergistically with permanent substrates to protect the fine structure on the p-side; ③ leveraging the low-cost advantage of sapphire substrates while obtaining high thermal conductivity permanent substrates; ④ simplifying the n-side surface treatment process and ensuring the quality of the upper plane DBR; ⑤ providing a feasible technical path for the manufacture of low-cost, high-performance plano-cavity VCSELs.

[0085] This technology leverages the advantages of laser lift-off—high efficiency and low damage—by transferring the substrate after the permanent substrate is formed, while avoiding its potential risks to thin-layer structures.

[0086] In some embodiments, the epitaxial substrate is a GaN single crystal substrate, which is removed by grinding and thinning and chemical mechanical polishing processes.

[0087] The above technical solution further specifies the specific removal method for GaN single-crystal epitaxial substrates in the preparation method of this invention. Specifically, when the epitaxial substrate is a GaN single crystal, it is removed using a combination of grinding and thinning with chemical mechanical polishing. This step plays a crucial role in the overall preparation process of this invention by transferring the epitaxial structure from the thick substrate to the permanent substrate. It occurs after the preparation of all structures on the p-side (including the SiO2 transition layer surface, the concave DBR mirror, the permanent substrate, etc.) and before the preparation of the n-side electrode and the upper plane DBR. This differentiated removal scheme for homogeneous substrates, together with the aforementioned laser lift-off scheme for sapphire substrates, constitutes the complete substrate processing technology system of this invention.

[0088] The essential feature of this technology lies in the use of a combination of "grinding and thinning + chemical mechanical polishing" to remove material properties of GaN single crystal substrates, which is adapted to the specific p-side concave mirror structure and process timing of this invention.

[0089] First, grinding and thinning rapidly removes most of the substrate material, reducing the thickness from hundreds of micrometers to tens of micrometers with high efficiency. Then, chemical mechanical polishing (CMP) is used for fine finishing, removing the damage layer introduced by grinding and obtaining a final exposed surface with excellent surface smoothness and extremely low subsurface damage. This two-step design of "rough grinding + fine polishing" ensures both process efficiency and surface quality of the n-type GaN layer, providing an ideal substrate for subsequent deposition of the upper planar DBR.

[0090] Secondly, GaN, as a wide-bandgap semiconductor material with high hardness, can achieve a certain thinning effect through grinding alone, but the surface roughness is large and a grinding damage layer exists; polishing alone is too inefficient to achieve a removal rate of hundreds of micrometers. This technology employs a two-step process, leveraging the high removal rate of grinding and the surface finishing advantages of polishing, representing an optimized choice for the characteristics of GaN material. Compared to sapphire substrates, which require laser lift-off (and cannot be effectively removed mechanically), the machinability of GaN homogeneous substrates allows for the use of this more mature semiconductor process.

[0091] Furthermore, the placement of this step within the process sequence of this invention is of significant importance. The grinding, thinning, and polishing processes apply considerable mechanical pressure and shear force to the wafer. If performed before the formation of the p-side structure, the epitaxial layer, only a few micrometers thick, cannot withstand this; if performed before the fabrication of the permanent substrate, the wafer lacks effective support. This technical feature arranges substrate removal after the formation of the permanent substrate. At this point, the device is already supported by the permanent substrate, effectively resisting stress during machining and protecting the fine curved surface structure of the p-side and the DBR mirror.

[0092] Furthermore, using a GaN single-crystal substrate as the epitaxial substrate leverages the low defect density advantage of homoepitaxial growth, resulting in epitaxial layers with excellent crystal quality. After fabricating the p-side structure, the original substrate is removed through grinding and polishing, preserving the performance advantages of the high-quality epitaxial layer while ultimately achieving a device structure supported by a high thermal conductivity permanent substrate, thus combining performance and heat dissipation capabilities. This technical approach holds unique value for applications seeking ultimate performance.

[0093] The above characteristics together bring the following beneficial effects: ① achieving efficient and high-quality removal of GaN single crystal substrates; ② obtaining n-GaN exposure surfaces with excellent surface flatness and extremely low damage layer; ③ working synergistically with permanent substrates to protect the fine structure on the p-side; ④ leveraging the low-defect advantage of homoepitaxial growth while obtaining high thermal conductivity permanent substrates; ⑤ providing a differentiated technical path for the fabrication of high-performance plano-cavity VCSELs, parallel to sapphire substrate solutions.

[0094] This technical feature, by removing the substrate after the permanent substrate is formed, leverages the crystal quality advantages of homoepitaxial growth while ensuring the integrity of the fine p-side structure. This feature, together with the aforementioned sapphire substrate laser lift-off scheme, constitutes a complete substrate processing technology system, enabling the present invention to flexibly adapt to two mainstream GaN epitaxial substrate types based on differences in cost, performance, and process conditions.

[0095] In some embodiments, preparing a permanent substrate on the surface of the concave DBR mirror includes: forming a conductive layer on the surface of the concave DBR mirror, and forming a permanent substrate made of a conductive and thermally conductive material on the conductive layer.

[0096] The above technical solution further defines the specific implementation of the permanent substrate formation in the preparation method of the present invention. Specifically, the process of preparing a permanent substrate on the surface of the concave DBR reflector includes two key sub-steps: first, a conductive layer is formed on the surface of the concave DBR, and then a permanent substrate made of conductive and thermally conductive materials is formed on the conductive layer. This step plays a crucial role in constructing the permanent support structure on the p-side of the device in the overall preparation process of the present invention, and is located after the formation of the p-side curved structure and the concave DBR, and before the removal of the epitaxial substrate. The combined design of the conductive layer and the permanent substrate constitutes a p-side composite substrate that integrates mechanical support, electrical pathways, and thermal diffusion functions.

[0097] The essential feature of this technology lies in the two-step method of constructing the p-side support structure using a "conductive layer + permanent substrate". The conductive layer is given dual functions and the permanent substrate is given multiple material properties. This design concept is significantly different from the existing technology that uses a single material and a single process to prepare the substrate or uses a temporary bonding layer that is then removed, and it produces a synergistic technical effect.

[0098] First, the conductive layer serves a crucial dual function in both process and structure. The concave-surface DBR is composed of stacked dielectric films, and its surface is non-conductive, making it unsuitable for substrate formation processes such as electroplating and electrochemical deposition, which rely on conductive substrates. The introduction of this conductive layer serves first as a process seed layer, providing the necessary conductive interface for the subsequent fabrication of the permanent substrate. Simultaneously, this conductive layer remains in the device structure after the permanent substrate is formed, acting as the electrical and thermal coupling interface between the DBR and the permanent substrate. This "process layer as functional layer" design avoids the additional step of removing the temporary seed layer after processing, simplifies the process flow, reduces the number of interfaces, and helps to lower contact resistance and interface thermal resistance.

[0099] Secondly, the permanent substrate is constructed from conductive and thermally conductive materials, enabling it to perform multiple functions simultaneously. As a mechanical support, its thickness and strength must ensure the stability and operability of the entire device structure; as an electrical pathway, its conductivity allows current to be uniformly injected into the p-side; as a heat diffusion layer, its thermal conductivity rapidly dissipates and laterally diffuses heat generated in the active region, significantly improving the device's thermal management performance. Compared to traditional solutions using non-conductive, low-thermal-conductivity substrates (such as sapphire), or solutions that merely treat the substrate as a mechanical support, this technology achieves an integrated upgrade of substrate functionality.

[0100] Furthermore, this two-step design provides flexibility in material selection and process implementation for the permanent substrate. The conductive layer can be made of metallic materials (such as Cr / Au, Ti / Au, Ni / Au, etc.) that have good interfacial properties with both the DBR and subsequent substrates, ensuring strong interfacial bonding and low contact resistance. The permanent substrate can be made of various conductive and thermally conductive materials, such as electroplated copper, bonded copper sheets, silver sintered layers, and diamond-copper composites, depending on performance requirements and cost budget, and can be formed using different processes such as electroplating, electroless plating, bonding, and deposition. This layered design and process decoupling allow the technical solution of this invention to flexibly adapt to the performance requirements and cost constraints of different application scenarios.

[0101] Furthermore, the placement of this step within the overall process timing has significant engineering implications. The permanent substrate is formed after all the fine structures on the p-side (especially the curved SiO2 transition layer and the concave DBR) have been fabricated, ensuring these structures are adequately protected during subsequent substrate removal and n-side processes. Simultaneously, removing the original epitaxial substrate after the permanent substrate is formed ensures that the entire wafer maintains mechanical support provided by either the original or permanent substrate throughout the entire process, avoiding the need for temporary bonding processes.

[0102] The above features collectively bring the following beneficial effects: ① The conductive layer simultaneously meets process requirements and permanent structural functions, simplifying the process and reducing interfaces; ② The permanent substrate integrates mechanical support, electrical conduction, and thermal diffusion functions, improving the overall performance of the device; ③ The layered design provides flexibility in material and process selection to adapt to different application needs; ④ The process timing arrangement protects the fine structure and avoids temporary bonding processes; ⑤ The overall solution provides a complete, reliable, and scalable substrate fabrication path for p-side concave mirror VCSELs.

[0103] This technology utilizes a two-step design of "conductive layer + permanent substrate" to construct a p-side composite substrate structure that integrates a process seed layer, electrical interface, and thermal interface. The dual-functional positioning of the conductive layer and the selection of material properties for the permanent substrate form an organic synergy with the aforementioned p-side concave mirror configuration and SiO2 transition layer design of this invention—the former provides protection and support for the fine optical structure, while the latter enables the optimized design of the optical resonant cavity. Attached Figure Description

[0104] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0105] Figure 1This is a schematic diagram of an embodiment of a GaN-based vertical cavity surface-emitting laser with a plano-concave cavity structure according to the present invention;

[0106] Figure 2 This is a schematic flowchart of an embodiment of the fabrication method of a GaN-based vertical cavity surface-emitting laser with a plano-concave cavity structure according to the present invention;

[0107] Figure 3 This is a schematic diagram of a fabrication example of a method for preparing a GaN-based vertical cavity surface-emitting laser with a plano-concave cavity structure according to the present invention. The example diagram shows the device structure of the plano-concave cavity vertical cavity surface-emitting laser. The dashed lines represent the distribution of the Gaussian beam of the fundamental mode inside the cavity, and the plane mirror acts as the light exit aperture, which is laterally restricted.

[0108] Figure 4 This is a schematic diagram of the process flow for fabricating a plano-concave cavity GaN-based vertical cavity surface-emitting laser using epitaxial wafers on different substrates, according to an embodiment of the method for fabricating a plano-concave cavity structure GaN-based vertical cavity surface-emitting laser of the present invention.

[0109] Figure 5 Example 1 is a schematic diagram of the process flow for fabricating a GaN-based vertical cavity surface-emitting laser with a plano-concave cavity structure, according to an embodiment of the present invention.

[0110] Figure 6 Example 2 is a schematic diagram of the process flow for fabricating a plano-concave GaN-based vertical cavity surface-emitting laser using a GaN single-crystal substrate epitaxial wafer, according to an embodiment of the present invention.

[0111] In the figure, 1. Substrate; 2. Concave DBR mirror; 3. SiO2 transition layer; 4. Ohmic contact layer; 5. Current confinement layer; 6. p-type semiconductor layer; 7. Multiple quantum well active region; 8. n-type semiconductor layer; 9. n-side contact electrode; 10. Upper planar DBR mirror; 11. Sapphire substrate; 12. Unintentionally doped u-GaN layer; 13. n-GaN layer; 14. Multiple quantum well active region; 15. p-GaN layer; 16. p-side current confinement layer; 17. Ohmic contact layer; 18. Cr protective layer; 19. SiO2 transition layer; 21. Photoresist surface; 22. Surface shape; 23. Lower reflector DBR; 24. Cu substrate; 25. n-side electrode; 26. n-side planar mirror; 101. GaN single crystal substrate. Detailed Implementation

[0112] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the invention. Similarly, the following embodiments are only some, not all, embodiments of the present invention, and all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0113] This invention proposes a novel GaN-based plano-concave cavity vertical cavity surface-emitting laser and its fabrication method. The fabrication process of this novel device structure is more stable and reliable to a certain extent, and can effectively improve the device yield. In addition, this invention also provides a more cost-effective alternative for the epitaxial substrate of the GaN-based plano-concave cavity vertical cavity surface-emitting laser.

[0114] Example 1

[0115] Please see Figure 1 A GaN-based vertical cavity surface-emitting laser with a plano-concave cavity structure, wherein the laser employs a structure in which a concave DBR mirror is disposed on the p-side, and comprises, from bottom to top, the following components along the light emission direction:

[0116] Substrate 1;

[0117] A concave DBR reflector 2, wherein the substrate 1 is supported below the concave DBR reflector;

[0118] A SiO2 transition layer 3 is applied to the upper surface of the concave DBR reflector 2.

[0119] In addition, the following are arranged in sequence: ohmic contact layer 4, current limiting layer 5, p-type semiconductor layer 6, multi-quantum well active region 7, n-type semiconductor layer 8, n-side contact electrode 9, and upper plane DBR reflector 10.

[0120] In this embodiment, the device adopts a vertical structure, consisting of, from bottom to top, a substrate 1 (a permanent substrate made by electroplating copper, and a Cr / Au seed layer (not shown in the figure) between it and the concave DBR; the thickness of the electroplated copper substrate is 150-300 micrometers, and the specific thickness can be limited according to actual needs, depending on the requirements for heat dissipation when designing the device; this embodiment does not limit it, but only provides a suitable range), a concave DBR reflector (distributed Bragg reflector) 2, a SiO2 transition layer 3, an ohmic contact layer 4, a current limiting layer 5, a p-type semiconductor layer 6, a multi-quantum well active region 7, an n-type semiconductor layer 8 and an n-side contact electrode 9, and an upper planar DBR reflector 10.

[0121] In conventional plano-cavity devices, the curved mirror is typically placed on the n-side. Therefore, during n-side fabrication, a temporary substrate is required on the p-side for support. In this invention, the curved mirror is fabricated on the p-side, and electroplated copper is used directly as the permanent p-side substrate (it should be noted that the electroplated copper substrate can be replaced with any substrate with good electrical and thermal conductivity), eliminating the need for temporary bonding and contact bonding processes. Furthermore, the plano-cavity structure achieves lateral confinement of light waves at the light exit aperture. The electroplating process prepares a copper substrate with high thermal and electrical conductivity, thereby improving the device's heat dissipation characteristics and extending its lifespan.

[0122] In this embodiment, the radius of curvature R of the concave DBR mirror and the effective cavity length L of the plano-concave resonant cavity satisfy the plano-concave cavity stability condition, and their ratio is configured to form a diffraction-limited spot at the light-emitting surface of the upper plano DBR mirror. The radius of curvature of the concave DBR mirror 2 should be greater than the device cavity length to satisfy the plano-concave cavity stability condition, and the effective cavity length and the radius of curvature of the concave mirror should satisfy a 1:2 relationship to obtain a diffraction-limited spot at the light-emitting aperture. The concave DBR mirror 2 and the upper plano DBR mirror 10 are formed by multiple alternating superpositions of two dielectric films with different refractive indices. Depending on the emission band, SiO2 and TiO2 / HrO2 can be selected to achieve high reflectivity.

[0123] In this embodiment, the thickness of the SiO2 transition layer is configured such that the effective cavity length L and the radius of curvature R satisfy a proportional relationship for forming a diffraction-limited spot. That is, the thickness of the SiO2 transition layer 3 can be adjusted according to the cavity length and the radius of curvature of the concave DBR mirror 2. This embodiment provides a thickness in the range of 2-5 micrometers.

[0124] In this embodiment, besides adjusting the cavity length, the main purpose of the SiO2 transition layer is to enable the curved mirror to be positioned on the p-side. The height of the curved surface formed after photoresist baking is typically several micrometers; therefore, a SiO2 transition layer is necessary to fabricate a curved DBR on the p-side. The transition layer thickness given in this embodiment is not a specific value, as its subsequent thickness depends on the cavity length and the radius of curvature of the curved mirror. The "Improvement Effect" section at the end of this embodiment describes the impact of changes in cavity length and radius of curvature on the power density at the exit aperture. For a fundamental Gaussian beam, when the cavity length and radius of curvature satisfy a 1:2 ratio, theoretically, the minimum beam waist radius of the plano-concave cavity diffraction limit can be obtained, which is the maximum power density at the exit aperture. The transition layer participates in the beam reflection and diffraction within the plano-concave cavity. Regarding thickness, sapphire substrate samples typically have a relatively small n-GaN epitaxial thickness, potentially requiring a thicker transition layer for the same radius of curvature. GaN single-crystal substrates, on the other hand, have a thicker n-GaN layer, and subsequent polishing and thinning can control the device cavity length within a certain range by controlling the n-GaN thickness; therefore, strict control of the transition layer cavity length is not necessary. In this embodiment, only a range for the transition layer is given. Due to errors in the growth and ICP etching of the transition layer, its thickness can fluctuate within a certain range. The introduction of this transition layer enables the fabrication of curved mirrors on low-cost sapphire substrate epitaxial wafers, improving process adaptability and reducing costs.

[0125] In this embodiment, the ohmic contact layer 4 is generally selected from ITO, IZO or graphene, and patterned electrodes can be fabricated as needed; or a semiconductor tunnel junction can be used to optimize the lateral current spread on the p-side.

[0126] In this embodiment, the current-limiting layer 5 can be prepared by ion implantation or patterning SiO2 / AlN;

[0127] In this embodiment, the improvement effect obtained by the above-mentioned improvements is as follows:

[0128] Firstly, heat dissipation management is a key factor affecting the performance of GaN-based vertical-cavity surface-emitting lasers (VCSELs). Copper has a thermal conductivity of approximately 400 W / (m·K), while sapphire has a thermal conductivity of only about 35 W / (m·K). GaN has a hexagonal wurtzite structure, and its thermal conductivity differs along the c-axis (perpendicular to the substrate) and a-axis (in-plane direction), with in-plane thermal conductivity typically being better than that along the vertical direction. Replacing the substrate with electroplated copper can rapidly diffuse and dissipate the heat conducted from the GaN active region laterally, thereby solving the thermal management problem of the device and improving the power output, continuous-wave operation stability, and long-term reliability of the VCSEL.

[0129] Secondly, the core advantage of the plano-concave cavity structure over the double-plane mirror structure lies in its ability to achieve lateral light field confinement through the focusing effect of the concave mirror (e.g., Figure 3 As shown, the dashed line represents the distribution of the fundamental mode Gaussian beam within the cavity, and the mode selection effectively reduces the requirements for DBR reflectivity and optical confinement structure. Furthermore, the plano-concave cavity structure can achieve the maximum energy density at the light-emitting surface (plane mirror position). Taking the fundamental mode Gaussian beam as an example, the energy distribution at different positions is shown in formula (1):

[0130]

[0131] in, This represents the light intensity at an axial distance z from the waist position and a radial distance r from the center. This represents the peak light intensity at an axial distance z. This represents the cross-sectional radius at an axial distance z.

[0132] The expression for the total energy P of the intracavity Gaussian beam is obtained by integrating equation (1), as shown in equation (2):

[0133]

[0134] Thus, the peak light intensity I0(z) at the axial distance z is obtained as shown in Formula 3:

[0135]

[0136] The peak light intensity I0(z) is inversely proportional to the square of the beam cross-sectional radius. Therefore, reducing the beam waist radius can effectively increase the power density at the exit aperture. This invention can adjust the beam waist radius by modifying the radius of curvature at the curved surface and the thickness of the SiO2 transition layer (changing the device cavity length) to improve device performance.

[0137] Thirdly, all GaN-based plano-concave vertical-cavity surface-emitting lasers reported internationally are epitaxially fabricated on GaN single-crystal substrates. GaN substrate epitaxial wafers are more expensive than sapphire substrates. During epitaxy, a very thick layer of n-GaN is grown, allowing for curved etching on the n-side. Furthermore, during the n-side processing, temporary bonding is required on the p-side to fix the wafer, and this temporary bonding needs to be released subsequently, increasing the processing difficulty. The device structure proposed in this invention allows for the fabrication of plano-concave vertical-cavity surface-emitting lasers on sapphire substrates, resulting in lower processing costs. While a previous Chinese patent application (CN18137289 A) also suggests using sapphire substrate epitaxy for laser fabrication, it still requires a very thick layer of n-GaN. This invention designs the curved mirror on the p-side and achieves p-side curved surface fabrication by depositing a SiO2 transition layer on the p-side, eliminating the need for a thick n-GaN epitaxy and significantly reducing epitaxial costs. Furthermore, the fabrication process of this invention does not require temporary bonding, thus improving process stability and product yield to a certain extent. Specific implementation examples will be used to illustrate the device of this invention in detail below.

[0138] Example 2

[0139] Please see Figure 1 , Figure 2 A method for fabricating a GaN-based vertical-cavity surface-emitting laser with a plano-concave cavity structure, characterized in that the method for fabricating the GaN-based vertical-cavity surface-emitting laser with a plano-concave cavity structure as described in one embodiment includes the following steps:

[0140] S1. An n-type semiconductor layer 8, a multi-quantum well active region 7 and a p-type semiconductor layer 6 are epitaxially grown sequentially on an epitaxial substrate, and a current confinement layer 5 and an ohmic contact layer 4 are fabricated on the p-type semiconductor layer 6.

[0141] In this embodiment, a buffer layer, an unintentionally doped GaN layer, an n-type semiconductor layer, a multi-quantum-well active layer, and a p-type semiconductor layer are sequentially grown on a sapphire or GaN substrate. Then, an insulating treatment is performed on the p-type semiconductor layer to form a current-limiting layer, and ITO is deposited as an ohmic contact layer. A patterned Cr layer is deposited on the ITO surface as a subsequent protective layer (not shown in the figure). The patterning is to enable the light wave focused by the curved mirror to pass smoothly through the gain medium in the cavity.

[0142] S2. Deposit a SiO2 transition layer 3 on the surface of the ohmic contact layer 4; prepare a curved mask on the surface of the SiO2 transition layer 3; use the curved mask to etch and transfer the curved shape to the SiO2 transition layer 3, so that the surface of the SiO2 transition layer forms a curved structure.

[0143] In this embodiment, based on the required cavity length, a 2-5 micrometer thick layer of SiO2 is deposited on the upper layer of the wafer using CVD. Photolithography, development, and post-baking are performed on the surface of the SiO2 layer to form an arched curved surface. Then, ICP etching is used to transfer the photoresist pattern to the surface of the SiO2 layer. The radius of curvature of the curved SiO2 surface is determined by the thickness of the photoresist and the diameter of the pattern before post-baking, and the device cavity length is determined by the thickness of the deposited SiO2 and the depth of the ICP etching surface.

[0144] S3. Deposit a DBR dielectric film on the surface of the curved structure to form a concave DBR reflector 2;

[0145] In this embodiment, photoresist is used to protect the curved SiO2 layer area, and BOE is used for wet etching to expose the underlying Cr layer (not shown in the figure), after which a curved DBR is deposited.

[0146] S4. Prepare substrate 1 on the surface of the concave DBR reflector 2;

[0147] In this embodiment, a magnetron sputtering device is used to deposit a full-surface Cr / Au layer for electrode contacts and electroplating seed layer, and an approximately 200-micrometer-thick Cu layer is electroplated as the permanent substrate of the device, thus completing all p-side processes.

[0148] S5. Remove the epitaxial substrate to expose the n-type semiconductor layer 8;

[0149] In this embodiment, if the sample is a sapphire substrate, the original sapphire substrate is removed using a laser lift-off process, followed by polishing using a CMP device; if the sample is a GaN substrate, it is directly thinned and polished.

[0150] S6. Prepare a planar DBR mirror 10 and an n-side contact electrode 9 on the exposed n-type semiconductor layer 8.

[0151] In this embodiment, ICP is used for device separation, which requires etching the Cr layer on the p side, followed by depositing electrodes and planar DBR on the n side to complete device fabrication.

[0152] In this embodiment, the n-side contact electrode 9 uses a Cr / Au electrode with a thickness of 15nm / 160nm.

[0153] Please see Figure 3 , Figure 4 To better explain the preparation method of this embodiment, the following will use... Figure 3 Taking a plano-cavity laser structure as an example, this paper introduces two different substrate fabrication methods.

[0154] Example 1: A method for fabricating a plano-concave GaN-based vertical-cavity surface-emitting laser epitaxially on a sapphire substrate, such as... Figure 5 As shown. It includes the following steps:

[0155] S1 is formed by sequentially epitaxially growing an unintentionally doped u-GaN layer 12, an n-GaN layer 13, and a multi-quantum-well active region 14 on a sapphire substrate 11. 0.27 Ga 0.73 The N / GaN and p-GaN layers 15; it should be noted that the In content in the quantum well of the multi-quantum-well active region can be changed, thereby affecting the emission wavelength of the device, and the upper and lower DBR materials and the thickness of the monolayer also change accordingly; those skilled in the art can set them according to actual needs.

[0156] S2 uses photolithography to form a pattern on the surface of the p-GaN layer, then deposits a 20nm thick SiO2 layer, and peels off the photoresist to form a p-side current confinement layer 16 (patterned SiO2 insulating layer).

[0157] S3 uses magnetron sputtering to deposit full-surface ITO on the p-side as an ohmic contact layer 17 as a current spreading layer and Cr protective layer 18. The Cr protective layer is used to protect the subsequent wet etching process and ICP etching separation mesa process.

[0158] S4 deposits a 5-10 μm thick SiO2 transition layer 19 on the p side (it should be noted that the range indicated in one of the embodiments is 2-5 micrometers, which refers to the thickness after etching), and the subsequent height depends on the dome height after the photoresist forms the curved surface;

[0159] S5 uses photolithography to perform photolithography on the surface of the SiO2 transition layer, and then bakes it at a high temperature of 200°C to form a photoresist curved surface 21. The height of the curved surface is controlled by the photoresist thickness before the post-baking.

[0160] S6 uses ICP etching process to etch the photoresist curved shape 22 to the SiO2 transition layer;

[0161] S7 protects the curved area with photoresist and uses BOE wet etching process to expose the underlying Cr protective layer;

[0162] S8 uses electron beam evaporation technology to deposit 12 pairs of TiO2 / SiO2 (each layer being 1 / 4 of the center wavelength of the epitaxial wafer) DBRs as the lower reflector DBR 23;

[0163] S9 deposits a Cr / Au seed layer and electroplats a 200μm Cu24 to form a p-side permanent substrate;

[0164] S10 uses laser lift-off technology to remove the original sapphire substrate and polishes the n-side;

[0165] S11 uses photolithography and ICP to perform mesa etching on the device, etching down to the Cr protective layer on the p side, thus separating the individual device;

[0166] S12 uses photolithography and magnetron sputtering to fabricate patterned n-side electrodes 25 with thicknesses of 15 nm-Cr and 160 nm-Au, and uses photolithography and electron beam evaporation to deposit 8.5 pairs of TiO2 / SiO2 n-side planar mirrors 26, thus completing the device fabrication on the wafer;

[0167] Example 2

[0168] A method for fabricating a plano-concave GaN-based vertical-cavity surface-emitting laser epitaxially on a GaN single-crystal substrate, such as... Figure 6 As shown. It includes the following steps:

[0169] S1 is formed by sequentially epitaxially depositing an unintentionally doped u-GaN layer 12, an n-GaN layer 13, and a multi-quantum-well active region 14 (In) on a GaN single-crystal substrate 101. 0.27 Ga 0.73 The N / GaN and p-GaN layers 15; it should be noted that the In content in the quantum well of the multi-quantum-well active region can be changed, thereby affecting the emission wavelength of the device, and the upper and lower DBR materials and the thickness of the monolayer also change accordingly; those skilled in the art can set them according to actual needs.

[0170] Steps S2-S9 are the same as in Example 1, namely the fabrication of the p-side current confinement layer 16, ohmic contact layer 17, Cr protective layer 18, SiO2 transition layer 19, lower reflector DBR 23 and Cu substrate 24, respectively.

[0171] S10 uses diamond polishing slurry to grind and thin the original GaN substrate on the n side, and then uses CMP technology to polish it to expose n-GaN and polish it until the interface is smooth;

[0172] S11 uses photolithography and ICP to perform mesa etching on the device, etching down to the Cr protective layer on the p side, thus separating the individual device;

[0173] S12 uses photolithography and magnetron sputtering to fabricate patterned n-side electrodes 25 with thicknesses of 15 nm-Cr and 160 nm-Au. Then, it uses photolithography and electron beam evaporation to deposit 8.5 pairs of TiO2 / SiO2 n-side planar mirrors 26, thus completing the device fabrication on the wafer.

[0174] The above description is only a part of the embodiments of the present invention and does not limit the scope of protection of the present invention. Any equivalent device or equivalent process transformation made based on the content of the present invention specification and drawings, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A GaN-based vertical-cavity surface-emitting laser with a plano-concave cavity structure, characterized in that, The laser employs a structure in which a concave DBR reflector is positioned on the p-side, and comprises, from bottom to top, the following components along the light emission direction: Substrate; A concave DBR reflector, wherein the substrate is supported below the concave DBR reflector; A SiO2 transition layer covers the upper surface of the concave DBR reflector; And, sequentially arranged, an ohmic contact layer, a current limiting layer, a p-type semiconductor layer, a multi-quantum well active region, an n-type semiconductor layer, an n-side contact electrode, and an upper plane DBR reflector; The radius of curvature R of the concave DBR mirror and the effective cavity length L of the plano-concave resonator satisfy the plano-concave cavity stability condition, and the ratio between the two is configured by the SiO2 transition layer thickness so that a diffraction-limited spot is formed at the light-emitting surface of the upper plano DBR mirror.

2. The GaN-based vertical-cavity surface-emitting laser with a plano-concave cavity structure according to claim 1, characterized in that, The substrate is made of conductive and thermally conductive materials, and a metal seed layer is provided between the substrate and the concave DBR reflector. The thickness of the substrate is 150-300 micrometers.

3. A GaN-based vertical-cavity surface-emitting laser with a plano-concave cavity structure according to claim 1, characterized in that, Both the concave DBR mirror and the flat DBR mirror are made of alternating layers of two dielectric films with different refractive indices.

4. A method for fabricating a GaN-based vertical-cavity surface-emitting laser with a plano-concave cavity structure, characterized in that, The method for fabricating a GaN-based vertical-cavity surface-emitting laser with a plano-concave cavity structure as described in any one of claims 1 to 3 includes the following steps: An n-type semiconductor layer, a multi-quantum-well active region, and a p-type semiconductor layer are sequentially epitaxially grown on an epitaxial substrate, and a current-limiting layer and an ohmic contact layer are fabricated on the p-type semiconductor layer. A SiO2 transition layer is deposited on the surface of the ohmic contact layer; a curved mask is prepared on the surface of the SiO2 transition layer, and the curved mask is used for etching to transfer the curved shape to the SiO2 transition layer, so that the surface of the SiO2 transition layer forms a curved structure. A DBR dielectric film is deposited on the surface of the curved structure to form a concave DBR reflector; A permanent substrate is prepared on the surface of the concave DBR mirror. Remove the epitaxial substrate to expose the n-type semiconductor layer; An n-side contact electrode and an upper-plane DBR reflector are fabricated on the exposed n-type semiconductor layer surface.

5. The method for fabricating a GaN-based vertical-cavity surface-emitting laser with a plano-concave cavity structure according to claim 4, characterized in that, A curved mask is prepared on the surface of the SiO2 transition layer, and etching is performed using the curved mask to transfer the curved shape to the SiO2 transition layer, thereby forming a curved structure on the surface of the SiO2 transition layer, including: Photoresist is coated on the surface of the SiO2 transition layer. The photoresist is reflowed to form an arched surface through photolithography and high-temperature post-baking processes. After etching to form the surface, the SiO2 surface is protected with photoresist. BOE is used for wet etching to expose the ohmic contact layer outside the photoresist area for subsequent p-side ohmic contact. The radius of curvature of the arched surface is determined by the thickness of the photoresist and the diameter of the pattern.

6. The method for fabricating a GaN-based vertical-cavity surface-emitting laser with a plano-concave cavity structure according to claim 4, characterized in that, The epitaxial substrate is a sapphire substrate, which is removed using a laser lift-off process.

7. The method for fabricating a GaN-based vertical-cavity surface-emitting laser with a plano-concave cavity structure according to claim 4, characterized in that, The epitaxial substrate is a GaN single crystal substrate, which is removed by grinding and thinning and chemical mechanical polishing processes.

8. The method for fabricating a GaN-based vertical-cavity surface-emitting laser with a plano-concave cavity structure according to claim 4, characterized in that, The preparation of a permanent substrate on the surface of the concave DBR reflector includes: forming a conductive layer on the surface of the concave DBR reflector, and forming a permanent substrate made of conductive and thermally conductive material on the conductive layer.

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