A DC-DC converter and power management system for preventing output voltage overshoot

Abstract

This application provides a DC-DC converter and power management system for preventing output voltage overshoot, comprising: a basic structural unit for outputting a main control signal; a main control switch for turning on or off under the control of the main control signal; and a time control unit for outputting a forced shutdown signal to limit the on-time of the main control switch within a preset time range based on the forced shutdown signal, thereby avoiding voltage overshoot. By introducing an independent time control unit, this application can strictly limit the on-time of the main control switch within a preset range, thus effectively solving the problem of output voltage overshoot caused by abnormally prolonged on-time during sudden load reduction, and significantly improving the reliability and stability of the system.

Description

Technical Field

[0001] This application relates to the field of converter technology, and more specifically, to a DC-DC converter and power management system for preventing output voltage overshoot. Background Technology

[0002] DC-DC converters, as core components of power management systems, are widely used in various electronic devices. In traditional DC-DC converters designed to prevent output voltage overshoot, the turn-off time of the main control switch (usually a power MOSFET) is determined by the peak value of the inductor current or the switching current.

[0003] However, this control method based on current peak detection has inherent drawbacks under certain operating conditions, especially when the load undergoes drastic step changes (such as a sudden shift from heavy load to light load or no load). When the load suddenly decreases, the output voltage tends to rise, and the error voltage drops rapidly. In the next switching cycle, because the current detection signal takes longer to rise to this reduced error voltage, the on-time of the main control switch becomes abnormally long. Although the current loop eventually turns it off, this excessively long on-time injects excess energy into the output, causing a significant overshoot in the output voltage. Voltage overshoot can not only damage the downstream load but also affect the stability and reliability of the system. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a DC-DC converter and power management system that prevents output voltage overshoot, so as to overcome the problems in the prior art.

[0005] In a first aspect, embodiments of this application provide a DC-DC converter for preventing output voltage overshoot, comprising: Basic structural unit, used to output main control signals; A main control switch is used to turn on or off under the control of the main control signal. A time control unit is used to output a forced shutdown signal to limit the conduction time of the main control switch within a preset time range based on the forced shutdown signal, so as to avoid voltage overshoot. In some technical solutions of this application, the aforementioned time control unit includes: The delay module is used to receive a clock signal, delay it for a preset time, and then output a delayed signal. The logic control module is used to receive the main control signal and the delay signal, and output the forced shutdown signal according to the logic state of the main control signal and the delay signal.

[0006] In some technical solutions of this application, the aforementioned delay module includes: The charging control module is used to charge the preset energy storage module to generate a ramp voltage under the control of the clock signal. The first comparison module is used to compare the ramp voltage with the reference voltage, and output the delay signal when the ramp voltage reaches the reference voltage.

[0007] In some technical solutions of this application, the aforementioned delay module includes: The counting module is used to count the periods of the clock signal to obtain the current count value; The second comparison module is used to compare the current count value with a preset count threshold, and output the delay signal when the current count value reaches the preset count threshold.

[0008] In some technical solutions of this application, the above-mentioned logic control module is used for: When the delayed signal changes from an active level to an inactive level, it is output as the forced shutdown signal to turn off the main control switch; When the delay signal is at an active level, the main control signal is output.

[0009] In some technical solutions of this application, the aforementioned preset energy storage module includes a first capacitor; The charging control module includes a charging current source and a switching transistor. The switching transistor is controlled by the clock signal to control the charging process of the charging current source on the first capacitor. The first comparison module includes a first trigger.

[0010] In some technical solutions of this application, the above-mentioned counting module is a digital counter; The second comparison module is a digital comparator.

[0011] In some technical solutions of this application, the above-mentioned logic control module includes AND gate circuits.

[0012] In some technical solutions of this application, the aforementioned switching transistor includes a first switching transistor and a second switching transistor.

[0013] Secondly, embodiments of this application provide a power management system, including an input power supply and the aforementioned DC-DC converter for preventing output voltage overshoot.

[0014] The technical solutions provided by the embodiments of this application may include the following beneficial effects: This application provides a DC-DC converter to prevent output voltage overshoot, comprising: a basic structure unit for outputting a main control signal; a main control switch for turning on or off under the control of the main control signal; and a time control unit for outputting a forced shutdown signal to limit the on-time of the main control switch to a preset time range based on the forced shutdown signal, thereby avoiding voltage overshoot. This application introduces an independent time control unit, which can strictly limit the conduction time of the main control switch within a preset range, thereby effectively solving the problem of output voltage overshoot caused by abnormally prolonged conduction time when the load suddenly decreases, and significantly improving the reliability and stability of the system.

[0015] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the frame of a DC-DC converter for preventing output voltage overshoot provided in an embodiment of this application is shown; Figure 2 This illustration shows a schematic diagram of a DC-DC converter for preventing output voltage overshoot provided in an embodiment of this application. Figure 3 A detailed structural diagram of a delay module provided in an embodiment of this application is shown. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0019] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0021] DC-DC converters, as core components of power management systems, are widely used in various electronic devices. In traditional DC-DC converters designed to prevent output voltage overshoot, the turn-off time of the main control switch (usually a power MOSFET) is determined by the peak value of the inductor current or the switching current.

[0022] However, this control method based on current peak detection has inherent drawbacks under certain operating conditions. Due to the light-load frequency reduction mode attached to this control method, there is a theoretical possibility of a longer conduction time during light-load output. Therefore, during light-load output, especially when the input voltage drops rapidly, particularly when the input is powered off, the current detection signal needs a longer time to rise to the set minimum error voltage at low input voltages. This causes the conduction time of the main control switch to be abnormally prolonged, and it may even fail to turn off via the current loop, instead being turned off by the set maximum duty cycle. This excessively long conduction time injects excess energy into the output, resulting in a significant overshoot in the output voltage. Voltage overshoot can not only damage the downstream load but also affect the stability and reliability of the system.

[0023] Based on this, this application provides a DC-DC converter and power management system for preventing output voltage overshoot, which are described below through embodiments. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0024] like Figure 1As shown, this application provides a DC-DC converter to prevent output voltage overshoot. This converter adds an independent time control unit to the traditional peak current control loop. Specifically, the converter includes a basic structural unit, a main control switch, and a time control unit. The basic structural unit forms the core loop, responsible for generating an error voltage based on the output voltage feedback. Based on the comparison between this error voltage and the current detection signal from the main control switch, it outputs a main control signal to control the state of the main control switch. The main control switch is the actuator for power conversion; it conducts during the effective level of the main control signal, transferring input energy to the output, and turns off when the main control signal is invalid. The key improvement of this application lies in the time control unit, whose core function is to monitor the conduction time of the main control switch and ensure that it does not exceed a safe preset time range. The time control unit outputs a forced shutdown signal. Once it detects that the on-time of the main control switch has reached the preset time, regardless of the state of the main control signal output by the basic structure unit (i.e., regardless of whether the current detection signal has reached the error voltage), the time control unit will immediately use this forced shutdown signal to override the original control logic and forcibly shut down the main control switch. Through this mechanism, the uncontrolled extension of the on-time caused by a sudden drop in error voltage can be completely eliminated, cutting off the excess energy injection path that leads to output voltage overshoot at the source, thereby effectively avoiding the output voltage overshoot phenomenon.

[0025] In an optional implementation, the time control unit can be further subdivided into a delay module and a logic control module. The delay module receives a periodic clock signal as a reference starting point. After a set delay, it outputs a delay signal whose state will reverse. The length of this delay defines a safe preset time range (i.e., the maximum allowable on-time). The logic control module simultaneously receives the main control signal from the basic structure unit and the delay signal from the delay module, and ultimately determines the turn-off time of the main control switch based on the logical relationship between these two signals. Specifically, the logic control module can be an AND gate circuit. The main control signal and the delay signal are respectively connected to the two input terminals of this AND gate, and the output of the AND gate directly drives the main control switch. Its working logic is as follows: after the start of a switching cycle, when the clock signal triggers the delay module to start timing, the delay signal is at an effective level (e.g., high level). At this time, the output of the AND gate completely follows the main control signal. If the current loop comparison is completed first (i.e., normal operation), the main control signal becomes low level, the AND gate output also becomes low, and the main control switch is normally turned off. If the current loop comparison fails to occur due to an excessively low error voltage, causing the main control signal to remain high, the delay signal will transition to an invalid level (e.g., low level) once the delay module reaches its preset time. According to the logic characteristics of an AND gate, if any input is low, the output will be low. Therefore, the transition of the delay signal will immediately force the AND gate output low; this low-level signal is the forced shutdown signal, which unconditionally shuts down the main control switch, thus strictly limiting its on-time to a preset range.

[0026] In one alternative implementation, the specific implementation of the delay module is flexible. A typical analog implementation includes a charging control module, a capacitor as an energy storage element, and a first comparison module. Upon receiving a valid edge of the clock signal, the charging control module controls a constant current source to begin linearly charging the capacitor, thereby generating a ramp voltage across the capacitor. The first comparison module (e.g., a comparator or Schmitt trigger) continuously compares this ramp voltage with a fixed reference voltage. When the ramp voltage is charged to equal the reference voltage, the output state of the first comparison module flips, generating the delay signal. The magnitude of the charging current, the capacitance value, and the reference voltage value together determine the duration of the delay. Another implementation is digital, where the delay module may include a counting module and a second comparison module. Triggered by a clock signal, the counting module begins periodically counting a higher-frequency reference clock signal. The second comparison module (e.g., a digital comparator) continuously compares the current value of the counter with a preset counting threshold. When the count value reaches the threshold, the output state of the second comparison module flips, generating the delay signal. The delay time is determined by the product of the count threshold and the period of the high-frequency reference clock. Both methods can achieve precise delay control, and the choice can be made based on the specific application scenario and integration process.

[0027] In an alternative implementation, as in practice, such as Figure 2 As shown, the delay module is a circuit labeled Delay1, whose input receives the periodic clock signal CLK generated by the system oscillator (OSC). The specific internal structure of Delay1 is as follows. Figure 3 As shown, the delay module mainly consists of a charging control module, a first capacitor C1 serving as a preset energy storage module, and a Schmitt trigger SMT1 serving as a first comparison module. The core of the charging control module is a charging current source I1, whose on / off state is finely managed by a pair of complementary control switches: specifically, a first switch P0 (e.g., a PMOS transistor) and a second switch N0 (e.g., an NMOS transistor). One end of the first capacitor C1 is grounded, and the other end is connected to the output node of the charging current source I1. This node also serves as a detection point connected to the input terminal of the Schmitt trigger SMT1.

[0028] The logic control module employs a two-input AND gate. One input of this gate receives the master control signal PWM from the underlying structural unit (e.g., output by an RS flip-flop), while the other input is connected to the output of the delay module Delay1 to receive the delay signal. The output of this AND gate is directly connected to the gate (control terminal) of the master control switch M1, serving as the final control signal driving M1. The underlying structural unit refers to all devices outside the dashed box in the figure.

[0029] Its working principle is as follows: When CLK is low, a delay is initiated. At this time, the first switch P0 is turned on, the second switch N0 is turned off, and the charging current source I1 is turned on, starting constant current charging of the first capacitor C1, thereby generating a linearly rising ramp voltage Vramp across capacitor C1. The Schmitt trigger SMT1 compares the rising Vramp with its internal fixed reference voltage Vref1. As long as Vramp is lower than Vref1, the output OUT of SMT1 remains low. When capacitor C1 continues to charge until Vramp reaches or exceeds Vref1, the output OUT of SMT1 quickly flips to high. The delay time, determined by the charging current value, the capacitance of capacitor C1, and the reference voltage Vref1, from the start of charging triggered by the valid edge of the clock signal CLK until the SMT1 output flips, is the precisely set preset delay. When the clock signal CLK jumps high, the first switch P0 turns off to cut off the charging current, while the second switch N0 turns on, providing a fast discharge path for capacitor C1 and quickly pulling its voltage Vramp back to ground potential. This resets the entire delay module, preparing it for the next operating cycle. Finally, the high and low level signals generated by the output OUT of the Schmitt trigger SMT1 constitute the delay signal.

[0030] During the delay module's timing period (i.e., when OUT is high), the AND gate acts as a transparent channel, allowing the main control signal PWM to pass through and control M1. Once the delay reaches the preset value, OUT transitions to low, and the AND gate output is immediately forced low. Regardless of the PWM signal's state at this time, this low-level signal acts as a forced shutdown signal, unconditionally turning off the main control switch M1. This achieves precise limitation on the conduction time of the main control switch M1.

[0031] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0032] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A DC-DC converter for preventing output voltage overshoot, characterized in that, include: Basic structural unit, used to output main control signals; A main control switch is used to turn on or off under the control of the main control signal. A time control unit is used to output a forced shutdown signal during a transient process of input voltage reduction, so as to limit the conduction time of the main control switch within a preset time range based on the forced shutdown signal, thereby avoiding output voltage overshoot caused by abnormal extension of the main control signal during the transient process. The time control unit includes: The delay module is used to receive a clock signal, delay it for a preset time, and then output a delayed signal. The logic control module is used to receive the main control signal and the delay signal, and output the forced shutdown signal according to the logic state of the main control signal and the delay signal.

2. The converter according to claim 1, characterized in that, The delay module includes: The charging control module is used to charge the preset energy storage module to generate a ramp voltage under the control of the clock signal. The first comparison module is used to compare the ramp voltage with the reference voltage, and output the delay signal when the ramp voltage reaches the reference voltage.

3. The converter according to claim 1, characterized in that, The delay module includes: The counting module is used to count the periods of the clock signal to obtain the current count value; The second comparison module is used to compare the current count value with a preset count threshold, and output the delay signal when the current count value reaches the preset count threshold.

4. The converter according to claim 1, characterized in that, The logic control module is used for: When the delayed signal changes from an active level to an inactive level, it is output as the forced shutdown signal to turn off the main control switch; When the delay signal is at an active level, the main control signal is output.

5. The converter according to claim 2, characterized in that, The preset energy storage module includes a first capacitor; The charging control module includes a charging current source and a switching transistor. The switching transistor is controlled by the clock signal to control the charging process of the charging current source on the first capacitor. The first comparison module includes a first trigger.

6. The converter according to claim 3, characterized in that, The counting module is a digital counter; The second comparison module is a digital comparator.

7. The converter according to claim 4, characterized in that, The logic control module includes AND gate circuits.

8. The converter according to claim 5, characterized in that, The switching transistor includes a first switching transistor and a second switching transistor.

9. A power management system, characterized in that, Includes an input power supply and a DC-DC converter for preventing output voltage overshoot as claimed in any one of claims 1-8.

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