A method for improving the working stability of PFC when the input voltage drops greatly

Abstract

This invention relates to the field of power factor correction technology, specifically to a method for improving the operational stability of PFC when the input voltage drops significantly. The method utilizes a 1 / 2-cycle maximum value detection method, employing a software phase-locked loop and a half-frequency cycle maximum value detection method to rapidly refresh the dynamic effective value of the input voltage. This value is then used as a feedforward quantity to directly participate in the calculation of the input current reference value. This allows for instantaneous compensation of input power when a voltage drop occurs, effectively suppressing bus voltage drops and current overshoot. This addresses key issues such as slow dynamic response and excessively long system recovery time in traditional PWM cycle-by-cycle current limiting schemes, as well as harmonic distortion, power factor degradation, and deteriorated system stability caused by increasing the voltage loop bandwidth.

Description

Technical Field

[0001] This invention relates to the field of power factor correction technology, and more specifically, to a method for improving the operational stability of PFC when the input voltage drops significantly. Background Technology

[0002] In AC / DC conversion circuits, the main task of the PFC (Power Factor Correction) stage is to ensure that the input current tracks the voltage waveform to guarantee a high power factor and stabilize the bus voltage. However, in actual operation, if the grid voltage drops significantly, conventional PFC control is prone to the following problems: due to the slow dynamic response of the voltage loop, the bus voltage will drop rapidly; the voltage loop integrator will continuously accumulate errors, and when the voltage recovers, the cumulative effect will cause a sharp jump in the input current command, forming a current spike, which can trigger overcurrent protection or even burn out the circuit in severe cases.

[0003] To address this issue, existing technologies primarily employ two approaches:

[0004] 1. PWM Cycle-by-Cycle Current Limiting Protection. This method uses a hardware comparator to achieve cycle-by-cycle overcurrent blocking, preventing damage from instantaneous overcurrent. However, it is essentially a passive current cutoff and does not address the fundamental contradiction of energy shortage. Therefore, the system recovers slowly, has poor dynamic response, and is unable to cope with the energy shock caused by short-term and significant voltage drops.

[0005] 2. Dynamically increase the voltage loop bandwidth. This scheme aims to improve response speed and suppress bus voltage drop, but excessive bandwidth will cause bus ripple components to be mixed into the input current reference value, which is easy to induce the third harmonic, resulting in a decrease in PF value and deterioration of THD; at the same time, increasing the bandwidth will weaken the system phase margin, which is easy to cause oscillation or even runaway.

[0006] In summary, existing PFC technologies generally suffer from protection hysteresis and a difficulty in balancing dynamic response and steady-state performance when dealing with significant input voltage drops. They cannot achieve rapid compensation and smooth recovery while ensuring harmonic performance and system stability. This not only limits their application in harsh power grids or high-reliability environments but also increases system design redundancy and safety risks. Summary of the Invention

[0007] The purpose of this invention is to overcome the key defects of existing PFC control technology when dealing with large drops in input voltage, such as slow system recovery, delayed dynamic response caused by passive cycle-by-cycle current limiting or dynamic increase of voltage loop bandwidth, as well as the resulting input current harmonic distortion, power factor reduction, weakened system stability, and even runaway.

[0008] The purpose of this invention is to provide a method to improve the stability of PFC operation when the input voltage drops significantly. By using a software phase-locked loop and a half-frequency cycle maximum value detection method, the dynamic effective value of the input voltage is rapidly refreshed and used as a feedforward quantity to directly participate in the calculation of the input current reference value. This allows for instantaneous compensation of input power when a voltage drop occurs, effectively suppressing bus voltage drops and current overshoot. This solves key problems such as slow dynamic response and excessively long system recovery time in traditional PWM cycle-by-cycle current limiting schemes, as well as harmonic distortion, power factor deterioration, and system stability degradation caused by increasing the voltage loop bandwidth.

[0009] To achieve the above objectives, the present invention aims to provide a method for improving the operational stability of PFC when the input voltage drops significantly, comprising the following steps:

[0010] Step S1: Construct a real-time input voltage detection platform based on software phase-locked loop (PLL). Use the PLL to perform real-time phase tracking of the input voltage (Vac), locate the zero-crossing moment of the voltage waveform, and provide a synchronous reference for voltage drop detection within half a power frequency cycle.

[0011] Step S2: Perform rapid calculation of the dynamic effective value of the input voltage based on the 1 / 2 cycle maximum value detection method, specifically including:

[0012] Starting from the detected zero crossing, the input voltage is sampled cycle by cycle. The input voltage value Va(k) of the current sampling cycle is compared with the input voltage value Va(k-1) of the previous sampling cycle, and the larger value is saved in the maximum value register Vmax. This process continues until the phase crosses the next zero crossing.

[0013] After sampling for half a power frequency cycle, the value stored in the register Vmax is the peak value Vpeak of the input voltage during that half power frequency cycle; combined with the steady-state effective value Vrms of the input voltage obtained through root mean square calculation, the following judgment is made:

[0014] If Vpeak < *(Vrms-ΔV), where ΔV is the preset input voltage drop warning threshold, determines that a significant drop in input voltage has occurred, and sets Vpeak < Vdrms is the dynamic effective value of the input voltage;

[0015] Step S3: Perform rapid adjustment of the input current reference value based on dynamic effective value feedforward. When it is determined that the input voltage has dropped significantly, the refreshed dynamic effective value Vdrms is used for feedforward calculation. The reference value iref of the input current loop is calculated according to the formula iref=(Vloop_out *Vac) / Vdrms², where Vloop_out is the output of the bus voltage loop and Vac is the instantaneous value of the input voltage.

[0016] Step S4: Perform PFC inner loop regulation and bus voltage stabilization control. The PFC inner loop controller adjusts based on the current error e=iref-iL and outputs the duty cycle d to control the operation of the switching transistor, thereby increasing the input power instantaneously, suppressing further drops in bus voltage, and suppressing input current overshoot caused by the voltage loop integral accumulation effect.

[0017] Step S5: Execute steady-state effective value maintenance control under normal operating conditions. If Vpeak ≥ *(Vrms-ΔV) indicates that the input voltage has not dropped significantly. Therefore, the steady-state effective value of the input voltage Vrms calculated by the root mean square is used as the dynamic effective value Vdrms, and the original feedforward calculation method is maintained.

[0018] As a further improvement to this technical solution, in step S1, the software phase-locked loop calculates the instantaneous phase θ of the input voltage in real time. When the phase crosses zero degrees, it is marked as the beginning of half a power frequency cycle, and the input voltage drop detection process in step S2 is started.

[0019] As a further improvement to this technical solution, in step S2, cycle-by-cycle sampling means sampling the input voltage once per switching cycle, with the sampling duration being half a power frequency cycle.

[0020] As a further improvement to this technical solution, in step S2, the input voltage peak value Vpeak is obtained by continuously comparing the voltage values ​​of adjacent sampling periods within half a power frequency cycle, dynamically updating the larger value to the maximum value register Vmax, and the value of Vmax at the end of the cycle is Vpeak.

[0021] As a further improvement to this technical solution, in step S2, the input voltage drop warning threshold ΔV is a preset fixed value or a variable value that is dynamically adjusted according to the system operating status.

[0022] As a further improvement to this technical solution, in step S3, the dynamic effective value Vdrms used in the feedforward calculation is refreshed within half a power frequency cycle, and the refresh speed is synchronized with the input voltage drop detection cycle.

[0023] As a further improvement to this technical solution, in step S3, in the calculation formula of the input current loop reference value iref, Vac is used as a multiplication factor to ensure that the input current tracks the phase of the input voltage, and Vdrms² is used as a division factor to reflect the influence of the change in the effective value of the input voltage on the required input current amplitude.

[0024] As a further improvement to this technical solution, in step S4, the PFC inner loop controller adopts a proportional-integral regulator, which is adjusted based on the current error e, and outputs a duty cycle d to control the on and off of the switching transistor.

[0025] As a further improvement to this technical solution, in step S5, when the input voltage does not drop significantly, the system maintains the original steady-state control parameters and does not trigger dynamic effective value refresh and fast feedforward adjustment.

[0026] As a further improvement to this technical solution, the method is implemented through a software algorithm, which does not rely on a hardware cycle-by-cycle current limiting circuit, thus saving hardware costs and reducing the MCU's computing resource consumption.

[0027] In this invention, a software phase-locked loop is first used to construct a real-time phase tracking and zero-crossing point positioning reference for the input voltage, achieving precise locking of the voltage waveform's half-cycle boundary. Then, using the 1 / 2-cycle maximum value detection method, the peak value of the input voltage is rapidly captured and the dynamic effective value is refreshed in real time within half a cycle. Based on the voltage drop criterion, the refreshed dynamic effective value is used as a feedforward quantity to directly participate in the calculation of the input current reference value, realizing instantaneous feedforward compensation from voltage drop identification to current command adjustment. Finally, under the rapid adjustment of the PFC inner loop, the input power is instantaneously increased to suppress the bus voltage drop, while effectively suppressing the current overshoot caused by the voltage loop integral accumulation effect. Thus, without relying on hardware current limiting circuits and without sacrificing steady-state harmonic performance, the entire process control from voltage disturbance occurrence to rapid power compensation and smooth system recovery is completed, significantly improving the operational stability and reliability of the PFC converter under large grid voltage fluctuations.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] This method for improving the stability of PFC operation when the input voltage drops significantly involves constructing a zero-crossing point positioning reference based on half-cycle and a maximum value detection mechanism based on a software phase-locked loop. This enables rapid refreshing of the dynamic effective value of the input voltage. Combined with feedforward compensation based on the dynamic effective value and rapid adjustment of the PFC inner loop, the entire process of control, from voltage drop identification to instantaneous input power compensation and smooth system recovery, is completed without relying on hardware current limiting circuits or sacrificing steady-state harmonic performance. This significantly improves dynamic response speed and system stability while effectively avoiding the inherent defects of traditional solutions such as slow response, harmonic distortion, and system instability. It successfully solves the common industry problem of PFC converters struggling to balance rapid compensation and high power quality when the grid voltage fluctuates significantly. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the process of the present invention;

[0031] Figure 2 This is a schematic diagram illustrating the specific implementation process of the present invention;

[0032] Figure 3 This is a schematic diagram of the input voltage drop waveform under traditional control methods.

[0033] Figure 4 This is a schematic diagram of the input voltage drop waveform under the control of the method of the present invention. Detailed Implementation

[0034] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] In AC / DC conversion circuits, the power factor correction (PFC) stage serves as the core hub connecting the power grid and load energy conversion, undertaking the crucial tasks of improving power quality, reducing harmonic pollution, and maintaining stable bus voltage. Among these, achieving accurate tracking of the input current to the input voltage is a fundamental prerequisite for ensuring that the PFC converter achieves a high power factor and good dynamic performance.

[0036] However, in actual operating conditions, especially when the input voltage drops significantly due to grid fluctuations, the stability of the PFC control system faces severe challenges. A sudden voltage drop usually signifies a momentary shortage of input energy. Given the limited dynamic response speed of conventional voltage loops, continuous load drawdown leads to a rapid decrease in bus voltage. To compensate for the lack of bus energy, the integrator in the voltage loop accumulates errors due to the persistent presence of these errors. Once the input voltage recovers, this cumulative effect forces a sharp increase in the input current command, creating a large current spike. This can not only trigger cycle-by-cycle overcurrent protection but, in severe cases, can even burn out the circuit due to thermal and electromagnetic stresses exceeding the device's limits.

[0037] To address the above issues, the industry currently employs two main approaches:

[0038] One approach employs PWM cycle-by-cycle current limiting protection technology. This technology compares the real-time sampled high-frequency current with a preset threshold using a hardware comparator. Once the current exceeds the limit, the drive signal for the current cycle is immediately blocked. Although this method can prevent damage from instantaneous overcurrent through rapid hardware response, it is essentially a passive "current interruption" protection mechanism and does not address the fundamental contradiction of energy supply and demand imbalance from the control mechanism perspective. Therefore, the system often suffers from slow dynamic response and excessively long recovery time from a fault state to a steady state. Furthermore, it cannot effectively prevent system collapse due to excessive energy deficit when dealing with short-term, significant voltage drops.

[0039] Secondly, a control strategy of dynamically increasing the voltage loop bandwidth is adopted. This scheme attempts to improve the loop response speed at the moment of voltage drop, so that the bus voltage drop can be quickly converted into a reference increment of input current, so as to replenish input power in time and suppress further bus voltage collapse. However, this scheme introduces new inherent limitations in engineering applications: excessive increase in bandwidth will cause the input current reference value to contain a large amount of ripple components introduced by bus voltage fluctuations, especially at the power frequency harmonics, which can easily excite and amplify the third harmonic component of the input current, resulting in a significant decrease in power factor (PF value) and a deterioration of total harmonic distortion (THD). At the same time, an excessively wide loop bandwidth will severely weaken the phase margin of the system. Once it encounters external disturbances, the circuit is very prone to oscillation or even divergence and loss of control, which greatly threatens the safe operation of the system.

[0040] In summary, existing PFC control technologies generally face a dilemma when dealing with significant input voltage drops: lag in protection actions and a tradeoff between dynamic response and steady-state accuracy. They cannot achieve rapid compensation and smooth recovery of bus voltage drops while ensuring input current harmonic parameters and system stability. These inherent defects not only limit the application of PFC converters in high-reliability scenarios such as harsh grid environments or frequent and severe load fluctuations, but also increase the design redundancy and safety risks of the power system.

[0041] Therefore, please refer to Figure 1 As shown, the purpose of this embodiment of the invention is to provide a method for improving the operational stability of PFC when the input voltage drops significantly, including the following steps:

[0042] Step S1: Construct a real-time input voltage detection and zero-crossing point positioning platform based on a software phase-locked loop.

[0043] This platform forms the basis for the method of this invention. Its core lies in using a software phase-locked loop to perform real-time phase tracking of the input voltage Vac, accurately locating the zero-crossing point of the voltage waveform, and providing a synchronization reference for voltage dip detection within the subsequent half-cycle of the power frequency. Specifically:

[0044] Zero-crossing detection and cycle synchronization: The software phase-locked loop continuously calculates the instantaneous phase θ of the input voltage. When the phase crosses zero degrees (or the starting point of the corresponding power frequency cycle) is detected, it is marked as the beginning of half a power frequency cycle, and the input voltage drop detection process is started.

[0045] Step S2: Perform rapid calculation of the dynamic effective value of the input voltage based on the 1 / 2 cycle maximum value detection method.

[0046] After detecting the phase zero crossing, the system enters a voltage sampling and processing flow within half a power frequency cycle, as follows:

[0047] Point-by-point sampling and maximum value hold: Starting from the current zero-crossing point, the input voltage Vac is sampled cycle by cycle (e.g., each switching cycle). Let the input voltage value of the current sampling cycle be Va(k), compare it with the value Va(k-1) of the previous sampling cycle, and save the larger of the two to the maximum value register Vmax. This process continues until the software phase-locked loop detects that the phase has crossed the next zero-crossing point (i.e., half a power frequency cycle has ended).

[0048] Peak value extraction and dynamic RMS value calculation: After sampling and comparison for half a power frequency cycle, the value stored in the register Vmax is the peak value Vpeak of the input voltage within that half power frequency cycle. Subsequently, combined with the steady-state RMS value Vrms of the input voltage obtained through root mean square calculation, the following judgments and calculations are performed:

[0049] If Vpeak < *(Vrms-ΔV), where ΔV is the preset input voltage drop warning threshold, then it is determined that the input voltage has dropped significantly.

[0050] At this point, Vpeak < As the dynamic effective value Vdrms of the input voltage, it enables rapid refresh of the dynamic effective value within half a cycle.

[0051] Step S3: Perform rapid adjustment of the input current reference value based on dynamic effective value feedforward.

[0052] When a significant drop in input voltage is detected, the system immediately uses the newly refreshed dynamic effective value Vdrms for feedforward calculation to quickly adjust the reference value of the input current loop, as follows:

[0053] Feedforward Calculation and Current Reference Update: Based on the power balance principle of PFC control, the reference value iref of the input current loop is jointly determined by the output Vloop_out of the bus voltage loop, the instantaneous value of the input voltage Vac, and the effective value of the grid voltage. The calculation formula is: iref = (Vloop_out * Vac) / Vdrms². Here, Vac serves as a multiplication factor to ensure that the input current reference value tracks the phase of the input voltage; Vdrms² serves as a division factor to reflect the impact of changes in the effective value of the input voltage on the required input current amplitude.

[0054] When Vdrms decreases rapidly due to a voltage drop, this feedforward calculation immediately increases the magnitude of iref, and the rate of change is much faster than the indirect method of increasing iref by adjusting Vloop_out through traditional voltage loop integration. This step directly responds to the energy gap, requiring a momentary increase in the input current to compensate for the input power.

[0055] Step S4: Perform PFC inner loop regulation and bus voltage stabilization control.

[0056] After the input current reference value iref increases rapidly according to step S3, the PFC inner loop controller (such as a proportional-integral regulator) adjusts based on the current error e=iref-iL (iL is the actual input current), and outputs the duty cycle d to control the operation of the switching transistor. The specific effect is as follows:

[0057] Rapid input power compensation: Under the action of inner loop regulation, the actual input current iL quickly tracks the increasing reference value iref, and the input power increases instantaneously, effectively suppressing the further drop in bus voltage due to energy shortage.

[0058] Integral accumulation effect suppression: Because the bus voltage drop is effectively suppressed, the integrator of the voltage loop accumulates less due to its smaller error during the recovery of the bus voltage to its original value, resulting in the voltage loop output Vloop_out not increasing excessively. This fundamentally avoids the problem of a sharp increase in input current after voltage recovery caused by the integral accumulation effect in traditional solutions, thereby avoiding the risk of overcurrent protection triggering or even circuit burnout.

[0059] Step S5: Execute steady-state effective value maintenance control under normal operating conditions.

[0060] If in step S2, by determining Vpeak≥ *(Vrms-ΔV) indicates that the input voltage fluctuation is within the allowable range and no significant drop has occurred. At this time, the system continues to use the steady-state effective value Vrms of the input voltage calculated by the root mean square as the dynamic effective value Vdrms, maintaining the original feedforward calculation method, without affecting the steady-state operation and harmonic performance of the system.

[0061] The specific implementation process of the above method steps is as follows: Figure 2 As shown. Figure 2 In this context, Vac: input voltage; θ: phase estimated by the software phase-locked loop; Vloop_out: output of the bus voltage loop; Vdrms: dynamic effective value of the grid voltage; iref: reference value of the input current loop; iL: input current; Kp: proportional parameter of the current loop; Ki: integral parameter; e: input current loop error; d: output duty cycle; Vrms: steady-state effective value of the grid voltage; Vpeak: peak value of the grid voltage; ΔV: threshold for input voltage drop.

[0062] In summary, this invention combines a software phase-locked loop (PLL) with a half-cycle maximum value detection method to achieve rapid half-cycle refresh of the dynamic effective value of the input voltage. This refresh is then used as a feedforward quantity to directly calculate the input current reference value. This instantaneously increases the input current and rapidly compensates for input power during voltage dips, effectively suppressing bus voltage dips and subsequent current overshoot. This method avoids the passive response and slow recovery issues of traditional cycle-by-cycle current limiting schemes, and also avoids the harmonic degradation and system instability risks associated with increasing the voltage loop bandwidth. It significantly improves the operational stability and reliability of the PFC converter under large grid voltage fluctuations.

[0063] The key innovations of this invention are as follows:

[0064] Firstly, a fast calculation method for the dynamic effective value of input voltage based on the detection of the maximum value of half a cycle is proposed. Combined with the zero-crossing point positioning of the software phase-locked loop, the peak value of the input voltage and the dynamic effective value can be captured and refreshed within half a power frequency cycle. The response speed is much faster than the traditional whole-cycle root mean square calculation, providing real-time voltage drop information for feedforward control.

[0065] Secondly, a feedforward control path based on the dynamic effective value was constructed. When a voltage drop is detected, the refreshed dynamic effective value Vdrms is directly used to participate in the calculation of the current reference value iref. The input current command is rapidly increased through the feedforward path, realizing instantaneous compensation for the input power gap. This fundamentally solves the response lag and current overshoot problems caused by the reliance on voltage loop integral regulation in traditional schemes.

[0066] Third, it achieves decoupling between dynamic response speed and steady-state control accuracy. This invention activates a fast feedforward path when the voltage drops, while maintaining the steady-state effective value Vrms for control under normal operating conditions. This ensures both rapid response to disturbances and avoids the adverse effects on steady-state harmonic parameters (PF, THD) and system stability caused by continuously increasing the loop bandwidth.

[0067] The advantages of this invention are:

[0068] First, it significantly improves the system's dynamic response capability and stability. When encountering a significant drop in input voltage, it can instantaneously increase the input current to suppress the bus voltage drop, and effectively suppress current overshoot during the voltage recovery process. The system's recovery time to steady state is greatly shortened, and its ability to resist grid disturbances is significantly enhanced.

[0069] Secondly, it saves on hardware costs. Since this invention solves the overcurrent risk at the control algorithm level, it does not require hardware protection circuits such as PWM cycle-by-cycle current limiting, thus eliminating the need for corresponding comparators, logic circuits, and peripheral components, reducing system BOM cost and PCB area.

[0070] Third, the software algorithm is simple and efficient. The 1 / 2 cycle maximum value detection method has clear logic, low computational load, requires only a few comparison and storage operations, does not occupy too much MCU computing resources, is easy to implement in various digital power controllers, and has good engineering promotion value.

[0071] Fourth, it balances dynamic performance and power quality. This invention only triggers the fast feedforward path when the voltage drops, without affecting the control loop structure and parameters of the PFC converter in steady state. Therefore, it does not introduce additional harmonic distortion, ensuring the maintenance of high power factor and low THD.

[0072] In summary, the present invention provides a method for improving the operational stability of PFC when the input voltage drops significantly. It can achieve fast and smooth input power compensation with a simple software algorithm, effectively avoiding the problems of control lag, current overshoot, harmonic degradation and system instability faced by traditional solutions when dealing with voltage drops. It significantly improves the operational reliability of PFC converters in complex power grid environments, while also having the advantages of low hardware cost, low resource consumption and easy implementation, and has extremely high practical value and promotion prospects.

[0073] Experimental example: The advantages of this invention are that it can improve the dynamic response of the system, save hardware development costs, and ensure that the system will not suffer a large input current impact when encountering a large input voltage drop, thus greatly improving the stability and reliability of the system.

[0074] like Figure 3 , Figure 4The waveforms show a comparison of experiments using the traditional method and the method proposed in this invention (input voltage drops from 220V to 170V, C1 is the input current, C2 is the bus voltage, and C3 is the input voltage).

[0075] according to Figure 3 , Figure 4 It can be seen that the method proposed in this invention rapidly increases the input current when the input voltage drops significantly, thus minimizing the drop in PFC bus voltage and greatly shortening the recovery time. In contrast, the traditional method refreshes the effective value of the input voltage too slowly, resulting in a gradual increase in input current when the input voltage drops significantly. This causes a larger drop in PFC bus voltage during this process, and the recovery time is also greatly prolonged. Therefore, the control effect of the method proposed in this invention is immediate.

[0076] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended technical solutions and their equivalents.

Claims

1. A method for improving the stability of PFC operation during a large input voltage dip, characterized in that, Includes the following steps: Step S1: Based on the zero-crossing point of the input voltage detected by the software phase-locked loop, a half-power frequency cycle synchronization reference is provided; Step S2: In each half power frequency cycle, the peak value Vpeak of the input voltage is detected, and in combination with the steady-state effective value of the input voltage, it is judged whether a large-scale drop occurs. If a drop occurs, the peak value Vpeak in the half power frequency cycle is divided by as a dynamic effective value Vdrms; Step S3: A feedforward control path with the dynamic effective value Vdrms as the core is constructed. When a voltage drop is detected, the refreshed dynamic effective value Vdrms is directly used to participate in the calculation of the reference value iref of the input current loop. The input current command is rapidly increased through the feedforward control path, realizing instantaneous compensation for the input power gap. This fundamentally solves the response lag and current overshoot problems caused by the reliance on voltage loop integral regulation in traditional schemes. Step S4: Perform PFC inner loop control based on the adjusted current loop reference value iref to suppress bus voltage slump and current overshoot; Step S5: If no drop occurs, maintain the original steady-state effective value for feedforward calculation.

2. The method for improving the working stability of PFC when the input voltage drops sharply according to claim 1, characterized in that: In step S1, the software phase-locked loop calculates the instantaneous phase of the input voltage in real time. When the phase crosses zero degrees, it is marked as the beginning of half a power frequency cycle, and the drop detection process in step S2 is started.

3. The method for improving the working stability of PFC when the input voltage drops sharply according to claim 1, characterized in that: The detection of the peak value Vpeak of the input voltage in step S2 specifically includes: The input voltage is sampled once in each switching cycle, and the sampling lasts for half a power frequency cycle; During the sampling process, the current sampled value is compared with the previous sampled value, and the larger value is dynamically updated to the maximum value register. At the end of the cycle, the value of the register is the peak value Vpeak in that half-power frequency cycle.

4. The method for improving PFC operating stability when the input voltage drops significantly, as described in claim 1, is characterized in that: The condition for determining whether a significant drop has occurred in step S2 is as follows: Vpeak *(Vrms-ΔV), where Vrms is the steady-state effective value of the input voltage obtained by calculation using the root mean square, and ΔV is the preset input voltage drop warning threshold; ΔV is a fixed value or a variable value that is dynamically adjusted according to the system operating state.

5. The method for improving PFC operating stability when the input voltage drops significantly, as described in claim 4, is characterized in that: In step S2, after determining that a significant drop has occurred, Vpeak / Vdrms is the dynamic effective value of the input voltage.

6. The method for improving PFC operating stability when the input voltage drops significantly, as described in claim 5, is characterized in that: In step S3, the feedforward calculation specifically calculates the reference value iref of the input current loop according to the formula iref=(Vloop_out×Vac) / Vdrms², where Vloop_out is the output of the bus voltage loop and Vac is the instantaneous value of the input voltage. The dynamic effective value Vdrms is refreshed within half a power frequency cycle, and the refresh rate is synchronized with the input voltage drop detection cycle; Vac is used as a multiplication factor to ensure that the input current tracks the phase of the input voltage, and Vdrms² is used as a division factor to reflect the impact of changes in the effective value of the input voltage on the required input current amplitude.

7. The method for improving PFC operating stability when the input voltage drops significantly, as described in claim 1, is characterized in that: In step S5, when the input voltage does not drop significantly, the system maintains the original steady-state control parameters and does not trigger the dynamic effective value Vdrms refresh and fast feedforward adjustment.

8. The method for improving PFC operating stability when the input voltage drops significantly, as described in claim 1, is characterized in that: In step S4, the PFC inner loop controller uses a proportional-integral regulator, which is adjusted based on the current error e=iref-iL, and outputs the duty cycle d to control the switching transistor to turn on and off, where iref is the reference value of the input current loop and iL is the actual input current.

9. The method for improving PFC operating stability when the input voltage drops significantly, as described in claim 1, is characterized in that: In step S4, while suppressing the bus voltage drop through PFC inner loop control, the input current overshoot caused by the voltage loop integral accumulation effect is also suppressed.

10. The method for improving PFC operating stability when the input voltage drops significantly, as described in claim 1, is characterized in that: The method is implemented through a software algorithm and does not rely on a hardware cycle-by-cycle current limiting circuit.

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