A superconducting josephson traveling wave parametric amplifier chip with distributed phase correction and a preparation method thereof

Abstract

The application discloses a superconducting Josephson traveling wave parametric amplifier chip with distributed phase correction and a preparation method thereof, relates to the technical field of low-temperature microwave amplifier design and manufacturing, and comprises an input / output port, an artificial transmission line composed of a superconducting Josephson series array and an LC resonator unit array distributed along the artificial transmission line. The artificial transmission line is composed of interdigital electrodes uniformly distributed along the line and superconducting Josephson junctions in series. The LC resonator unit is composed of a flat plate capacitor and a planar inductor. The lower electrode of the flat plate capacitor is divided into two parts. One part is a complete rectangular metal flat plate, and the other part is a interdigital structure and is engaged with the interdigital structure of the superconducting Josephson series array artificial transmission line. Nonlinear mixing of an input signal can be realized through the artificial transmission line composed of the superconducting Josephson series array. The interdigital coupling of the LC resonator array and the artificial transmission line provides distributed phase correction for signal transmission along the line, so that the gain of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of low-temperature microwave amplifier design and manufacturing technology, and in particular to a distributed phase-corrected superconducting Josephson traveling wave parametric amplifier chip and its fabrication method. Background Technology

[0002] Currently, superconducting Josephson junctions are the core components of superconducting quantum circuits and related low-temperature quantum-limited noise-performance microwave devices in superconducting quantum information systems. Utilizing the intrinsic nonlinear inductance of superconducting Josephson junctions, they can be combined with capacitors, resonators, etc., to realize superconducting parametric devices or circuits with functions such as mixing, amplification, isolation, and compression. This allows for parametric amplifiers with near-quantum-limited noise performance, meeting the key requirements for superconducting quantum bit signal measurement. Traveling-wave parametric amplifiers based on superconducting Josephson junctions, compared to reflective superconducting Josephson junctions, do not require additional signal separation devices, resulting in simpler measurement circuitry and a wider operating bandwidth. Leveraging the inherent advantages of superconducting Josephson junctions, such as dissipationlessness, nonlinearity, flexible adjustment, and ease of integration, they have become one of the key devices for the detection and broadband amplification of superconducting quantum signals and extremely weak signals.

[0003] Among the many publicly available broadband superconducting Josephson traveling-wave parametric amplifier (TWAPA) schemes, the basic method for amplification is to construct a high dynamic range (HMR) inductor transmission line using a superconducting Josephson junction array. Phase-shifting units are placed at discrete points at specified length intervals along the HMR inductor transmission line to periodically correct the phase difference between the pump signal and the signal to be amplified during transmission. However, this method typically fails to meet the stringent phase matching requirements of TWAPA on the transmission line, resulting in low pump energy conversion efficiency and insufficient device gain during mixing, thus preventing the device performance from meeting application requirements. Furthermore, to meet the impedance matching requirements between the HMR inductor transmission line and the external transmission line, impedance transformation lines or capacitors are usually required on the HMR inductor line. These factors increase the design complexity of the device and reduce the device fabrication yield.

[0004] Therefore, there is a need for a design and fabrication method for a broadband superconducting Josephson traveling wave parametric amplifier chip that can achieve distributed phase matching correction on the transmission line instead of discrete point phase matching correction and has low fabrication difficulty. Summary of the Invention

[0005] The purpose of this invention is to provide a distributed phase-corrected superconducting Josephson traveling wave parametric amplifier chip and its fabrication method, so as to solve the above-mentioned problems existing in the prior art.

[0006] In a first aspect, embodiments of the present invention provide a distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip, including input and output ports, an artificial transmission line composed of a superconducting Josephson series array, and an LC resonator unit array distributed along the artificial transmission line; The artificial transmission line composed of superconducting Josephson series arrays is formed by connecting interdigitated electrodes and superconducting Josephson junctions in series; the interdigitated electrodes and superconducting Josephson junctions are uniformly distributed on the artificial transmission line; the artificial transmission line composed of multiple superconducting Josephson series arrays is a metal wire; the interdigitated electrodes are metal strips with interdigitated structures. The LC resonator unit array contains multiple LC resonator units; each LC resonator unit includes a parallel plate capacitor and a planar inductor; the parallel plate capacitor includes a bottom electrode, a dielectric layer, and a top electrode; a portion of the bottom electrode is a rectangular metal plate, and the other portion is an interdigitated structure. The interdigitated structure in the LC resonator unit engages with the interdigitated structure of the interdigitated electrode in the superconducting Josephson series array, forming a distributed interdigitated capacitive coupling.

[0007] In this design, large-sized strip structures are used for the dielectric layer and the metal of the top electrode. All LC resonator units utilize only a single dielectric layer and a small number of independent areas of the top electrode metal. At bends in the artificial transmission line, LC resonator units are designed to match those elsewhere, ensuring consistent impedance throughout the transmission line. The coupling between the artificial transmission line and the LC resonator units employs a hybrid form of interdigital capacitors and parallel-plate capacitors. The coupling value can be flexibly adjusted by changing the interdigital length, the interdigital index, or the dielectric layer thickness. In the LC resonator unit design, the phase-shifting operating point of the LC resonator can be adjusted by changing the size of the metal strip on the top plate of the parallel-plate capacitor.

[0008] Optionally, the input / output port includes an input port and an output port; the input port is located at the input end of the manual transmission line; the output port is located at the output end of the manual transmission line. The input port is used to receive the signal to be amplified and the pump signal; the pump signal is used to provide the energy required for signal amplification. The output port is used to output the amplified signal to be amplified and the pump signal; The signal to be amplified and the pump signal are combined by a microwave combiner and then enter the manual transmission line through the input port. The artificial transmission line coupled by the distributed interdigitated capacitor is used to perform nonlinear mixing and phase correction of the signal to be amplified by the distributed LC resonator. The output port outputs the signal to be amplified after being amplified by a manual transmission line.

[0009] Optionally, the artificial transmission line coupled by the distributed interdigitated capacitors is a sandwich structure comprising a bottom layer, a middle layer, and a top layer; the bottom layer includes a series Josephson junction and interdigitated electrodes; the interdigitated electrodes are comb-shaped metal strips; the middle layer is the dielectric layer of the planar capacitor in the LC resonator unit; the top layer is the upper electrode of the planar capacitor in the LC resonator unit; the upper electrode is connected to a reference ground.

[0010] Optionally, the interdigitated structure and metal plate in the bottom electrode form a plate capacitor with the top electrode through a dielectric layer; The planar inductance of the LC resonator unit array is composed of metal strips; the geometric inductance of the metal strips serves as the inductance value of the LC resonator unit array.

[0011] Optionally, the LC resonator units in the LC resonator unit array share the same dielectric material template in the same dielectric layer and the metal template in the upper electrode plate; the LC resonator unit array is an array composed of one or more LC resonator units.

[0012] Optionally, the bottom electrode of the LC resonator unit array is coupled to the superconducting Josephson series array via an interdigitated structure to achieve distributed capacitive coupling on the artificial transmission line, thereby realizing distributed phase correction function.

[0013] Optionally, the method for coupling the artificial transmission line with the distributed interdigital capacitance of the LC resonator unit array further includes: The metal strips of the interdigitated electrodes in the superconducting Josephson series array, the dielectric layer in the LC resonator unit array, and the upper electrode of the LC resonator unit array form a planar capacitor. The planar capacitor and the LC resonator unit array share the dielectric layer and upper electrode in the LC resonator unit array, forming a distributed interdigital capacitive coupling.

[0014] Optionally, the coupling value of the artificial transmission line and the LC resonator unit array for distributed capacitive coupling can be adjusted by changing the length of the interdigitated structure at any position on the artificial transmission line.

[0015] Optionally, the LC resonator is coupled to a superconducting Josephson junction through a planar capacitor with a hybrid structure of interdigital structure and metal plate to form an artificial transmission line; the artificial transmission line has a phase shift function; the artificial transmission line can be periodically extended.

[0016] Secondly, embodiments of the present invention provide a method for fabricating a distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip, comprising: Step 301: A superconducting thin film is grown on a high-resistivity silicon substrate using magnetron sputtering; the superconducting thin film is a metal thin film formed from superconducting niobium. Step 302: Spin-coat photoresist on the superconducting thin film, expose the pattern using an ultraviolet lithography machine, and transfer the exposed pattern to a high-resistivity silicon substrate by reactive ion etching; Step 303: Grow a dielectric layer on a high-resistivity silicon substrate; Step 304: Spin-coat photoresist, expose the pattern using an ultraviolet lithography machine, and fabricate the dielectric layer of the parallel plate capacitor through reactive ion etching; Step 305: Spin-coat double-layer photoresist, perform a third photolithography exposure pattern, and fabricate the electrodes of the parallel plate capacitor by electron beam evaporation of metallic aluminum; Step 306: Spin-coat double-layer photoresist, perform a fourth photolithography exposure pattern, and fabricate Josephson junctions by electron beam evaporation at two angles.

[0017] Compared with the prior art, the embodiments of the present invention achieve the following beneficial effects: The distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip and its fabrication method of this invention employ a large-size strip structure for the dielectric layer and the metal of the top electrode. All LC resonator units utilize only a single dielectric layer and a small amount of independent top electrode metal, simplifying the fabrication process. LC resonator units consistent with those elsewhere are designed at bends in the artificial transmission line to ensure impedance consistency throughout the transmission line and avoid impedance mismatch.

[0018] The coupling between the transmission line path and the LC resonator unit includes a hybrid form of interdigital capacitors and parallel plate capacitors. The coupling value can be flexibly adjusted by changing the interdigital length, the number of interdigital fingers, or the thickness of the dielectric layer.

[0019] In the design of LC resonator units, the phase-shifting operating point of the LC resonator can be adjusted by adjusting the size of the metal strip on the upper plate of the parallel plate capacitor.

[0020] This technology has achieved significant reductions in the requirements for photolithography precision, greatly reduced design complexity, and improved microwave transmission performance and yield. Attached Figure Description

[0021] Figure 1 This is a planar structure diagram of a distributed phase-corrected artificial transmission line Josephson traveling wave parametric amplifier chip provided in this embodiment.

[0022] Figure 2 This is a circuit diagram of a distributed phase-corrected artificial transmission line Josephson traveling wave parametric amplifier chip unit provided in Embodiment 1 of this application.

[0023] Figure 3 This is a flowchart of a method for fabricating a distributed phase-corrected artificial transmission line Josephson traveling wave parametric amplifier chip, as provided in Embodiment 2 of this application.

[0024] Figure 4 This is a schematic diagram of frequency measurement of a single LC resonator unit provided in Embodiment 2 of this application.

[0025] Figure 5 The diagram shown is a schematic of the signal gain characteristics measured in a low-temperature environment according to Embodiment 2 of this application. Detailed Implementation

[0026] The present invention will now be described in detail with reference to the accompanying drawings.

[0027] Example 1:

[0028] like Figure 1 As shown, this embodiment provides a distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip, including an input / output port 101, an artificial transmission line 102 composed of a superconducting Josephson series array, and an LC resonator unit array 103 distributed along the artificial transmission line 102. The artificial transmission line 102, which is composed of a superconducting Josephson series array, is formed by interdigitated electrodes and superconducting Josephson junctions connected in series; the interdigitated electrodes and superconducting Josephson junctions are uniformly distributed on the artificial transmission line 102; the interdigitated electrodes are metal strips with interdigitated structures.

[0029] The interdigitated metal module is a comb-shaped superconducting metal module, meaning a comb-shaped superconducting metal module.

[0030] In this embodiment, the artificial transmission line 102 comprises 2800 superconducting Josephson junctions and 700 comb-shaped superconducting metal modules. A single superconducting Josephson junction array consists of one comb-shaped metal module and four Josephson junctions connected in series. These independent units are interconnected and periodically expanded to form an array, which is then connected to the input and output ports at both ends to form the artificial transmission line 102.

[0031] The Josephson junction is obtained by electron beam double-angle evaporation of metallic aluminum.

[0032] Among them, the artificial transmission line 102, composed of a superconducting Josephson series array, is a metal wire.

[0033] The LC resonator unit array 103 includes multiple LC resonator units; each LC resonator unit includes a parallel plate capacitor and a planar inductor 202; the parallel plate capacitor includes a bottom electrode 201, a dielectric layer 203, and an upper electrode 204; a portion of the bottom electrode 201 is a rectangular metal plate, and the other portion is an interdigitated structure.

[0034] The LC resonator unit 103 consists of a bottom electrode 201, a dielectric layer 203, and an upper electrode 204.

[0035] The artificial transmission line 102, consisting of the bottom electrode 201 and the metal strip corresponding to the superconducting Josephson junction in the artificial transmission line 102 connected in series, is formed from a niobium film using photolithography and etching processes. The dielectric layer 203 is formed by growing silicon nitride using plasma-enhanced chemical vapor deposition, and the top electrode 204 is formed by electron beam evaporation of aluminum.

[0036] The planar inductor 202 of the LC resonator unit 103 is composed of the planar inductor 202 in the LC resonator unit 103.

[0037] The LC resonator unit 103 consists of a parallel-connected plate capacitor and a planar inductor 202 connected to a reference ground 104. The interdigitated structure in the LC resonator unit engages with the interdigitated structure of the interdigitated electrode in the superconducting Josephson series array, forming a distributed interdigitated capacitive coupling.

[0038] The coupling method described above is direct capacitive coupling between interdigital structures.

[0039] The LC resonator unit 103 and the artificial transmission line 102 are coupled to each other through the interdigitated metal strip on the artificial transmission line 102 and the interdigitated structure in the bottom electrode 201 of the LC resonator unit 103.

[0040] Optionally, the input / output port 101 includes an input port and an output port; the input port is located at the input end of the manual transmission line 102; and the output port is located at the output end of the manual transmission line 102.

[0041] The input port is used to connect the signal to be amplified and the pump signal; the pump signal is used to provide the energy required for signal amplification.

[0042] The input port receives the combined signal of the signal to be amplified and the pump signal that provides the energy required for signal amplification. The output port outputs the amplified signal and the pump signal. The pump signal used for signal amplification operates at the same frequency as the resonant frequency of the LC resonator.

[0043] The output port is used to output the amplified signal to be amplified and the pump signal.

[0044] The pump signal output from the output port is the pump signal input to the input port after being amplified to the required energy.

[0045] The signal to be amplified and the pump signal are combined by a microwave combiner and then enter the artificial transmission line 102 through the input port. The artificial transmission line 102, coupled by the distributed interdigitated capacitors, is used to perform nonlinear mixing and distributed LC resonator phase correction on the signal to be amplified.

[0046] The output port outputs the signal to be amplified by the artificial transmission line 102.

[0047] In this embodiment, such as Figure 1 As shown, the input port is used to receive the signal to be amplified and the pump drive signal required for signal amplification. The signal to be amplified and the pump drive signal that provides the energy required for amplification are connected to the input port and then enter the artificial transmission line 102 of the distributed phase-corrected superconducting Josephson traveling wave parametric amplifier chip. The signal phase is matched by the nonlinear mixing effect of the superconducting Josephson series array on the artificial transmission line 102 and the phase shift of the LC resonator unit array 103 for signals of different intensities, thereby achieving the gain output of the signal to be amplified. The amplified signal is then output through the output port.

[0048] Optionally, the artificial transmission line 102 after distributed interdigitated capacitance coupling has a sandwich structure comprising a bottom layer, a middle layer, and a top layer; the bottom layer includes a series Josephson junction and interdigitated electrodes; the interdigitated electrodes are comb-shaped metal strips; the middle layer is a dielectric layer 203 containing the planar capacitors in the LC resonator unit; the top layer is the upper electrode 204 of the planar capacitors in the LC resonator unit 103; the upper electrode 204 is connected to the reference ground 104.

[0049] The connection between the upper electrode 204 and the reference ground 104 indicates that the upper electrode 204 is grounded.

[0050] The LC resonator unit 103 and the artificial transmission line 102 are coupled to each other through a sandwich structure consisting of the dielectric layer 203 of the LC resonator unit 103, the upper electrode 204 of the LC resonator unit 103, and the metal strip of the interdigital structure on the artificial transmission line 102.

[0051] Optionally, the interdigitated structure and metal plate in the bottom electrode 201 form a plate capacitor with the upper electrode 204 through the dielectric layer 203. The planar inductor 202 of the LC resonator unit array 103 is composed of a metal strip; the geometric inductance of the metal strip serves as the inductance value of the LC resonator unit array 103.

[0052] Between the first metal layer and the second metal layer.

[0053] In the artificial transmission line 102, each independent unit comb-shaped superconducting metal module interlocks with one end of the bottom electrode 201 of the planar capacitor, forming an interdigital capacitive coupling. The other end is connected to the reference ground 104 through the planar inductor 202.

[0054] Among them, the planar inductor 202 is a geometric inductor constructed using a bent metal strip, and the inductance value can be controlled by changing the length of the metal strip.

[0055] Wherein, the geometric inductance refers to a wire-wound inductor.

[0056] Among them, the metal module corresponding to the planar inductor 202 is not the same metal module as the metal module corresponding to the interdigitated electrode.

[0057] Optionally, the LC resonator units in the LC resonator unit array 103 share the same dielectric material template in the dielectric layer 203 and the metal template in the upper electrode 204; the LC resonator unit array 103 is an array composed of one or more LC resonator units.

[0058] The dielectric layer 203 is composed of dielectric material strips, and the upper electrode 204 is composed of metal strips.

[0059] Optionally, the bottom electrode 201 of the LC resonator unit array 103 is coupled to the superconducting Josephson series array via an interdigitated structure to achieve distributed capacitive coupling on the artificial transmission line 102, thereby realizing distributed phase correction function.

[0060] Optionally, the method for coupling the artificial transmission line 102 with the distributed interdigitated capacitance of the LC resonator array 103 further includes: The metal strips of the interdigitated electrodes in the superconducting Josephson series array, the dielectric layer 203 in the LC resonator unit array 103, and the upper electrode 204 in the LC resonator unit array 103 form a planar capacitor. The planar capacitor and the LC resonator unit array 103 share the dielectric layer 203 and the upper electrode 204 in the LC resonator unit array 103, forming a distributed interdigital capacitive coupling.

[0061] Optionally, the coupling value of the distributed capacitive coupling between the artificial transmission line 102 and the LC resonator unit array 103 can be adjusted by changing the length of the interdigitated structure at any position on the artificial transmission line 102.

[0062] Optionally, the LC resonator is coupled to a superconducting Josephson junction through a planar capacitor with a hybrid structure of interdigital structure and metal plate to form an artificial transmission line 102; the artificial transmission line 102 has a phase shift function; the artificial transmission line 102 can be periodically extended.

[0063] With the above structure, the artificial transmission line 102 can further increase the gain performance of the amplifier.

[0064] in, Figure 2This is a schematic diagram of the circuit structure of a distributed phase-corrected artificial transmission line 102 Josephson parametric amplifier chip unit. Each unit circuit consists of an LC resonator unit, a comb-shaped metal strip, and four Josephson junctions.

[0065] In this embodiment, a comb-shaped metal strip serves as an interdigital structure and is connected in series with four Josephson junctions to form a transmission line conduction path. The comb-shaped portion of the metal strip is coupled to the bottom electrode 201 of the LC resonator unit via an interdigital structure, and simultaneously coupled to the top electrode 204 of the LC resonator unit via a sandwich planar structure. The planar inductor 202 and planar capacitor in the LC resonator unit are designed, with the dielectric layer 203 thickness set to 200 nm, and the LC resonator operating frequency designed to be 6.6 GHz. In this embodiment, all LC resonator units use a single large-size strip-shaped dielectric layer 203 as the dielectric material strip, and the grounding metal plate corresponding to the top electrode 204 uses multiple large-size strip-shaped structures as the metal strips in the top electrode 204.

[0066] The above methods significantly reduce the dimensional accuracy requirements in device processing and improve the yield of device fabrication.

[0067] Example 2:

[0068] Embodiment 2 of this application provides a method for fabricating a distributed phase-calibrated artificial transmission line 102 superconducting Josephson traveling-wave parametric amplifier chip, such as... Figure 3 As shown, it includes: Step 301: On a high-resistivity silicon substrate, a superconducting thin film is grown by magnetron sputtering; the superconducting thin film is a metal thin film formed of superconducting niobium.

[0069] Among them, a 100nm thick niobium film is grown on a high-resistivity silicon substrate using magnetron sputtering.

[0070] Step 302: Spin-coat photoresist onto the metal thin film, expose the pattern using an ultraviolet lithography machine, and transfer the exposed pattern onto a high-resistivity silicon substrate using a reactive ion etching process.

[0071] The exposed image includes an input / output port 101, the bottom electrode 201 of the parallel plate capacitor corresponding to the LC resonator unit, and a planar inductor 202.

[0072] Step 303: Grow a dielectric layer 203 on a high-resistivity silicon substrate.

[0073] In this embodiment, the dielectric layer 203 is a silicon nitride dielectric layer 203.

[0074] Among them, the dielectric layer 203 of the plate capacitor region is preserved by performing photolithography-etching process.

[0075] Among them, a 200nm thick silicon nitride layer was grown on the substrate using a plasma-enhanced chemical vapor deposition process.

[0076] Step 304: Spin-coat photoresist onto dielectric layer 203, expose the pattern using an ultraviolet lithography machine, and fabricate dielectric layer 203 of the parallel plate capacitor by reactive ion etching.

[0077] In this process, the pattern is exposed a second time using an ultraviolet lithography machine, and a second reactive ion etching is performed to remove unnecessary silicon nitride and fabricate the dielectric layer 203 of the parallel plate capacitor.

[0078] Step 305: Spin-coat a double layer of photoresist onto dielectric layer 203, perform a third photolithography exposure pattern, and fabricate the electrodes of the parallel plate capacitor by evaporating metallic aluminum with an electron beam.

[0079] Among them, ultraviolet lithography is used to expose the pattern.

[0080] Among them, the upper electrode 204 of the parallel plate capacitor is fabricated using photolithography-thermal evaporation; The process involves spin-coating two layers of photoresist, with the bottom layer being LOR series photoresist and the top layer being AZ series photoresist.

[0081] In the third photolithography exposure pattern, an electron beam evaporated aluminum metal with a thickness of 300 nm was used to fabricate the upper electrode 204 of the planar capacitor.

[0082] Among them, the upper electrode 204 of the planar capacitor is fabricated using a photolithography-thermal evaporation method.

[0083] Step 306: Spin-coat double-layer photoresist, perform a fourth photolithography exposure pattern, and fabricate Josephson junctions by electron beam evaporation at two angles.

[0084] Among them, ultraviolet lithography is used to expose the pattern.

[0085] The process involves spin-coating two layers of photoresist: a bottom layer of LOR series photoresist and an top layer of AZ series photoresist. A fourth photolithography pattern is then applied, followed by electron beam evaporation to fabricate the Josephson junction.

[0086] The Josephson junction is fabricated using a dual-angle evaporation process. During the first evaporation, the substrate is held at a 58-degree angle to the evaporation direction, and a 50nm thick aluminum film is evaporated. After evaporation, the substrate is exposed to pure oxygen for surface oxidation, forming the insulating layer of the Josephson junction. During the second evaporation, the substrate is rotated 90 degrees while maintaining the 58-degree angle to the evaporation direction, and a 120nm thick aluminum film is evaporated, completing the Josephson junction fabrication.

[0087] In this process, the fabricated chip undergoes a stripping process, in which it is sequentially placed in N-methylpyrrolidone, acetone, isopropanol, and deionized water to remove excess photoresist and metal film, thus completing the fabrication of the distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip.

[0088] In this embodiment, the electron beam evaporation process is carried out in a closed environment with a background vacuum of less than 6e-9 Torr.

[0089] Among them, such as Figure 4 As shown, in this embodiment, the actual sample device, under a low temperature environment of 100mK, measured the operating frequency of the LC resonator array, which was concentrated at 6.6GHz, forming a bandgap that allows the amplified signal and the driving signal to be phase matched.

[0090] Among them, such as Figure 5 As shown, in this embodiment, the signal gain characteristics of the actual sample device were measured at a low temperature of 100mK. The specific measurement process is as follows: a microwave signal generator was used to generate a pump drive signal with a frequency of 6.5GHz, and another microwave generator generated a weak signal of -70dBm with a frequency of 5.7GHz. The two signals were combined by a combiner and then further attenuated by an attenuator so that the intensity of the weak signal when it reached the chip input port was -150dBm. At the chip output terminal, the signal was amplified by two stages of low-temperature amplifier and room-temperature amplifier on the output line and then connected to a signal analyzer. The measured output signal intensity was -68.8dBm. By comparing the change in the output intensity of the weak signal obtained from the switching pump drive signal, the signal gain of the device at the weak signal frequency can be obtained as 20dB.

[0091] Example 3:

[0092] The fabricated distributed phase-corrected artificial transmission line 102 Josephson traveling wave parametric amplifier chip includes two superconducting thin films and a dielectric layer 203. The two superconducting thin films are a first metal thin film layer and a second metal thin film layer, respectively.

[0093] Optionally, the first metal thin film layer includes a transmission line path corresponding to the artificial transmission line 102 and a bottom electrode 201 of a parallel plate capacitor, a planar inductor 202, and a reference ground plane 104 arranged along the transmission line path.

[0094] The transmission line path is composed of comb-shaped metal strips and Josephson junctions prepared by dual-angle electron beam evaporation. The transmission line path is coupled to the bottom electrode 201 of the parallel plate capacitor through an interdigitated capacitor structure. The bottom electrode 201 of the parallel plate capacitor is connected to the reference ground plane 104 through a planar inductor 202.

[0095] The second metal thin film layer is the upper electrode 204 of the planar capacitor in the LC resonator unit array 103.

[0096] The dielectric layer 203 is a silicon nitride thin film using a high dielectric constant material, located between the first metal thin film layer and the second metal thin film layer.

[0097] Optionally, the artificial transmission line 102 is coupled to the distributed interdigital capacitance of the LC resonator unit array 103, further comprising: In the artificial transmission line 102, the comb-shaped metal strips of each independent unit, along with the metal plate, dielectric layer 203, and second metal thin film layer in the interdigitated structure portion, constitute the parallel plate capacitor of the transmission line path corresponding to the artificial transmission line 102. This parallel plate capacitor shares the second metal thin film layer with the parallel plate capacitor in the LC resonator unit, thereby achieving coupling between the artificial transmission line 102 and the parallel plate capacitor corresponding to the LC resonator unit.

[0098] Optionally, the parallel plate capacitor of the artificial transmission line 102 is composed of a bottom electrode 201, a dielectric layer 203, and a second metal thin film. The parallel plate capacitor is connected in parallel with the planar inductor 202 to form an LC resonator unit, which is used as a phase-shifting unit.

[0099] The distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip and its fabrication method involve two coupling methods between the transmission line path and the LC resonator unit. One method involves direct interdigital coupling between the comb-shaped superconducting metal modules and the bottom electrode 201 structure of the planar capacitor. The other method involves the interdigital metal plates, dielectric layer 203, and second metal thin film layer corresponding to the interdigitated portions of the comb-shaped superconducting metal modules in the artificial transmission line 102 forming a planar capacitor. This planar capacitor shares the second metal thin film layer with the planar capacitor in the LC resonator, thus achieving capacitive coupling between the transmission line path and the planar capacitor in the LC resonator unit.

[0100] The above description is merely a further embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope disclosed in the present invention, based on the technical solution and concept of the present invention, shall fall within the scope of protection of the present invention.

[0101] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, this invention is not directed to any particular programming language. It should be understood that the contents of the invention described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of the invention.

[0102] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0103] The various component embodiments of the present invention can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the apparatus according to embodiments of the present invention. The present invention can also be implemented as a device or apparatus program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such programs implementing the present invention can be stored on a computer-readable medium or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

Claims

1. A distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip, characterized in that, It includes input / output ports, an artificial transmission line composed of a superconducting Josephson series array, and an array of LC resonator units distributed along the artificial transmission line; The artificial transmission line composed of superconducting Josephson series arrays is formed by connecting interdigitated electrodes and superconducting Josephson junctions in series; the interdigitated electrodes and superconducting Josephson junctions are uniformly distributed on the artificial transmission line; the artificial transmission line composed of multiple superconducting Josephson series arrays is a metal wire; the interdigitated electrodes are metal strips with interdigitated structures. The LC resonator unit array contains multiple LC resonator units; each LC resonator unit includes a parallel plate capacitor and a planar inductor; the parallel plate capacitor includes a bottom electrode, a dielectric layer, and a top electrode; a portion of the bottom electrode is a rectangular metal plate, and the other portion is an interdigitated structure. The interdigitated structure in the LC resonator unit engages with the interdigitated structure of the interdigitated electrode in the superconducting Josephson series array, forming a distributed interdigitated capacitive coupling. The input / output port includes an input port and an output port; the input port is located at the input end of the manual transmission line; the output port is located at the output end of the manual transmission line. The input port is used to receive the signal to be amplified and the pump signal; the pump signal is used to provide the energy required for signal amplification. The output port is used to output the amplified signal to be amplified and the pump signal; The signal to be amplified and the pump signal are combined by a microwave combiner and then enter the manual transmission line through the input port. The artificial transmission line coupled by the distributed interdigitated capacitor is used to perform nonlinear mixing and phase correction of the signal to be amplified by the distributed LC resonator. The output port outputs the signal to be amplified by a manual transmission line; The artificial transmission line after distributed interdigital capacitive coupling has a sandwich structure consisting of a bottom layer, a middle layer, and a top layer. The bottom layer includes series Josephson junctions and interdigitated electrodes; the interdigitated electrodes are comb-shaped metal strips. The intermediate layer is the dielectric layer of the parallel plate capacitor in the LC resonator unit; The upper layer is the upper electrode of the parallel plate capacitor in the LC resonator unit; the upper electrode is connected to the reference ground; The interdigitated structure and metal plate in the bottom electrode form a parallel plate capacitor with the top electrode through a dielectric layer. The planar inductance of the LC resonator unit array is composed of metal strips; the geometric inductance of the metal strips serves as the inductance value of the LC resonator unit array.

2. The distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip according to claim 1, characterized in that, The LC resonator units in the LC resonator unit array share the same dielectric material template in the same dielectric layer and the metal template in the upper electrode plate; the LC resonator unit array is an array composed of one or more LC resonator units.

3. The distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip according to claim 1, characterized in that, The bottom electrode of the LC resonator unit array is coupled to the superconducting Josephson series array via an interdigitated structure to achieve distributed capacitive coupling on the artificial transmission line, thereby realizing distributed phase correction function.

4. The distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip according to claim 1, characterized in that, The artificial transmission line is coupled to the distributed interdigital capacitance of the LC resonator unit array, and further includes: The metal strips of the interdigitated electrodes in the superconducting Josephson series array, the dielectric layer in the LC resonator unit array, and the upper electrode of the LC resonator unit array form a planar capacitor. The planar capacitor is connected in parallel with the bottom electrode, dielectric layer, and top electrode of the LC resonator unit array, forming a distributed interdigitated capacitive coupling.

5. The distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip according to claim 1, characterized in that, The coupling value of the distributed capacitive coupling between the artificial transmission line and the LC resonator unit array can be adjusted by changing the length of the interdigitated structure at any position on the artificial transmission line.

6. The distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip according to claim 1, characterized in that, The LC resonator is coupled to a superconducting Josephson junction through a planar capacitor with a hybrid structure of interdigital and metal plates to form an artificial transmission line; the artificial transmission line has a phase shift function; the artificial transmission line can be periodically extended.

7. A method for fabricating a distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip, characterized in that, The method for fabricating the distributed phase-corrected superconducting Josephson traveling-wave parametric amplifier chip according to claims 1-6 includes: Step 301: A superconducting thin film is grown on a high-resistivity silicon substrate using magnetron sputtering; the superconducting thin film is a metal thin film formed from superconducting niobium. Step 302: Spin-coat photoresist on the superconducting thin film, expose the pattern using an ultraviolet lithography machine, and transfer the exposed pattern to a high-resistivity silicon substrate by reactive ion etching; Step 303: Grow a dielectric layer on a high-resistivity silicon substrate; Step 304: Spin-coat photoresist, expose the pattern using an ultraviolet lithography machine, and fabricate the dielectric layer of the parallel plate capacitor through reactive ion etching; Step 305: Spin-coat double-layer photoresist, perform a third photolithography exposure pattern, and fabricate the electrodes of the parallel plate capacitor by electron beam evaporation of metallic aluminum; Step 306: Spin-coat double-layer photoresist, perform a fourth photolithography exposure pattern, and fabricate Josephson junctions by electron beam evaporation at two angles.

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