A method and system for real-time optimization of IgHEtherCAT master stations

Abstract

The embodiment of the present application relates to the technical field of industrial network, and discloses a method for IgH EtherCAT master station real-time optimization, comprising: carrying out real-time analysis on an EtherCAT frame header in a received data frame to extract frame characteristic information; monitoring reference clock time stamps returned from one or more EtherCAT slave stations, and calculating actual drift value sequences on multiple communication periods; predicting a predicted drift value of a next communication period by using a historical drift vector; adjusting the reference clock time sent to the slave station by superimposing the predicted drift value on the reference clock time by an IgH master station kernel module to provide feedforward compensation; and if the change of the frame length indicated by the extracted frame characteristic information exceeds a set threshold, dynamically reconfiguring a direct access storage descriptor ring by a reconfiguration module executed on a processing system. The scheme of the embodiment of the present application realizes lower and more stable communication delay and higher clock synchronization accuracy.

Description

Technical Field

[0001] This invention relates to the field of industrial network technology, specifically to a method and system for real-time optimization of IgH EtherCAT master stations. Background Technology

[0002] Currently, existing IgH EtherCAT master station solutions in Zynq embedded platform applications suffer from several technical shortcomings, including low bandwidth utilization due to static DMA descriptor ring configuration, limited synchronization accuracy due to passive compensation in distributed clock synchronization, mutual interference caused by shared transmission queues for real-time messages and non-real-time network traffic, lack of hardware acceleration utilization of Zynq platform FPGA logic, and the absence of multi-dimensional real-time performance comprehensive evaluation and adaptive optimization mechanisms. Therefore, designing a solution to improve real-time optimization has become a pressing technical problem for those skilled in the art. Summary of the Invention

[0003] To address the aforementioned shortcomings, this invention discloses a method for real-time optimization of IgH EtherCAT master stations, which can improve the real-time communication performance of IgH master stations.

[0004] The first aspect of this invention discloses a method for real-time optimization of an IgH EtherCAT master station, comprising: A data capture module implemented in programmable logic is used to parse the EtherCAT frame header in the received data frame in real time to extract frame feature information; The data capture module stores the extracted frame feature information into a shared memory register accessible by the processing system. The drift monitoring module, implemented in the programmable logic, monitors reference clock timestamps returned from one or more EtherCAT slave stations, calculates the actual drift value sequence over multiple communication cycles, and stores the historical drift vector in a block random access memory accessible by the processing system. The IgH master station kernel module running on the processing system executes a double exponential smoothing algorithm to predict the predicted drift value for the next communication cycle using the historical drift vector; The IgH master station kernel module provides feedforward compensation by superimposing the predicted drift value onto the reference clock time and adjusting the reference clock time sent to one or more EtherCAT slave stations. If the change in the length of the extracted frame feature information exceeds a set threshold, the reconfiguration module executed on the processing system dynamically reconfigures the direct access to the storage descriptor ring. A multi-queue gating scheduler implemented in the Ethernet access controller of the processing system performs time-aware gating control on at least a first transmit queue and a second transmit queue, wherein the first transmit queue is used to transmit real-time EtherCAT frames and the second transmit queue is used to transmit non-real-time network traffic, and the gating control includes disabling the second transmit queue during the guard band interval of the real-time communication cycle.

[0005] As an optional implementation, in a first aspect of the present invention, the dynamic reconfiguration of the direct access storage descriptor ring includes: The real-time communication cycle is paused during the guard band interval; The buffer lengths and memory alignments of multiple direct access memory descriptors are recalculated based on the extracted frame feature information. The reconfigured descriptor table is loaded into the direct access storage engine of the processing system; Restore the real-time communication cycle.

[0006] As an optional implementation, in the first aspect of the present invention, the real-time optimization method further includes: The data capture module detects emergency service data object requests from the IgH master station kernel module; in response to the detection, while maintaining the real-time communication cycle, the second sending queue is temporarily activated to send emergency service requests. And / or, the real-time optimization method further includes: The phase comparator implemented in the EtherCAT slave station generates a Sync0 interrupt only when the phase difference between the slave station's local time and the corrected reference clock time sent from the master station is less than a predetermined threshold. And / or, the real-time optimization method further includes: The data capture module monitors the queue depth and sending request frequency of the second sending queue; A congestion flag is generated when the queue depth or the sending request frequency exceeds a predetermined threshold, wherein the gating control is adjusted according to the congestion flag.

[0007] As an optional implementation, in a first aspect of the present invention, the double exponential smoothing algorithm includes: The horizontal and trend components are calculated based on the historical drift vector using a first smoothing factor for the horizontal component and a second smoothing factor for the trend component. The predicted drift value is calculated and determined based on the horizontal component and the trend component.

[0008] As an optional implementation, in the first aspect of the present invention, before the double exponential smoothing algorithm is executed by the IgH master station kernel module running on the processing system, the method further includes: A historical periodic feature template library is constructed, which includes multiple predefined time series templates. Each time series template corresponds to a periodic jitter mode, which includes normal mode, oscillation mode, sudden spike mode and drift mode. Extract the periodic execution time sequence and jitter sequence of the current communication cycle from the frame feature information to form the current cycle feature vector; Calculate the normalized distance between the current periodic feature vector and each template in the historical periodic feature template library; The periodic jitter pattern corresponding to the template with the smallest regularity distance is selected as the current periodic jitter pattern recognition result; Based on the current period jitter pattern recognition result, adjust the smoothing factor parameter of the double exponential smoothing algorithm.

[0009] As an optional implementation, in the first aspect of the present invention, calculating the normalized distance between the current periodic feature vector and each template in the historical periodic feature template library includes: Construct a cumulative distance matrix between the current periodic feature vector and the template feature vector, wherein the elements D in the cumulative distance matrix are... i,j This represents the minimum cumulative distance between the first i elements of the current periodic feature vector and the first j elements of the template feature vector; A window constraint is applied to the cumulative distance matrix to limit the maximum allowable deviation of the regularized path from the diagonal, wherein the maximum width is determined based on the maximum allowable jitter value of the EtherCAT communication cycle; The cumulative distance matrix is ​​calculated recursively using the following formula: D i,j = d i,j +min{D i-1,j D i,j-1 D i-1,j-1}, where d i,j The Euclidean distance between the i-th element of the current periodic feature vector and the j-th element of the template feature vector; Extract the bottom right element D of the cumulative distance matrix. n,m As the normalization distance, where n is the length of the current periodic feature vector and m is the length of the template feature vector; The step of adjusting the smoothing factor parameters of the double exponential smoothing algorithm based on the current period jitter pattern recognition result includes: When the recognition result is normal mode, the first smoothing factor and the second smoothing factor are kept at their preset default values; When the identification result is an oscillation mode, the first smoothing factor is increased to enhance the response sensitivity to recent jitter; When the identification result is a sudden spike pattern, the second smoothing factor is increased to enhance the sensitivity to trend changes; When the identification result is a drift pattern, both the first smoothing factor and the second smoothing factor are increased to accelerate the tracking of the drift trend.

[0010] As an optional implementation, in the first aspect of the present invention, the real-time optimization method further includes: The data capture module collects real-time performance index data, which includes the period jitter value between the actual communication period and the set period, the master-slave station distributed clock synchronization deviation value, the real-time thread scheduling delay value, the frame transmission delay value from submission by the direct memory access module to completion of transmission by the network card, the CPU load fluctuation value of the processor core, and the abnormal frame rate value, which is the proportion of abnormal frames to the total number of transmitted frames. The six real-time performance metrics collected were normalized to obtain the normalized values ​​of each metric. The six normalized values ​​are weighted and fused to obtain the original quality index; The minimum value among the six normalized values ​​is extracted, and a minimum value penalty is applied to the original quality index to obtain the real-time quality index; the real-time quality index is then used as a comprehensive evaluation parameter for the real-time performance of the IgH master station. The real-time quality index is compared with a preset first threshold and a second threshold, wherein the first threshold is greater than the second threshold; When the real-time performance quality index is greater than or equal to the first threshold, the current real-time performance is determined to be excellent, and the current parameter configuration is maintained. When the real-time performance quality index is between the second threshold and the first threshold, the current real-time performance is determined to be in a good state, and lightweight parameter fine-tuning is performed. When the real-time performance quality index is less than or equal to the second threshold, the current real-time performance is determined to be in a degraded state, and parameter reconfiguration is performed.

[0011] As an optional implementation, in the first aspect of the present invention, the lightweight parameter fine-tuning includes: The most severely degraded indicator is determined by multiplying the normalized value of each indicator by its weight. When the most severely degraded metric is periodic jitter, the first smoothing factor of the double exponential smoothing algorithm is increased to enhance the response to jitter. When the most severely degraded indicator is the synchronization deviation, the second smoothing factor of the double exponential smoothing algorithm is increased to enhance the tracking of the drift trend; When the most severe degradation indicator is scheduling delay or frame transmission delay, adjust the protection band interval of the multi-queue gating scheduler. When the most severe degradation metric is CPU load fluctuation, reduce the sampling frequency of the data capture module. When the most severely degraded metric is the abnormal frame rate, the link diagnostic process is triggered. The parameter reconfiguration includes: When the real-time performance quality index is less than or equal to the second threshold, record all current parameter configurations and real-time performance indicators. Iterate through multiple preset parameter configuration templates and select the template that maximizes the improvement in real-time quality index prediction. Perform a parameter configuration template switching operation, which includes switching the direct memory access descriptor configuration, adjusting the guard band interval, and updating the smoothing factor parameters; and recalculate the real-time quality index after the switching is completed to verify the optimization effect.

[0012] A second aspect of this invention discloses a system for real-time optimization of IgH EtherCAT master stations, comprising: Parsing module: This module, implemented in programmable logic, is used to perform real-time parsing of the EtherCAT frame header in the received data frame to extract frame feature information. Storage module: used to store the extracted frame feature information by the data capture module into a shared memory register accessible by the processing system; Monitoring module: A drift monitoring module implemented in the programmable logic is used to monitor reference clock timestamps returned from one or more EtherCAT slave stations, calculate the actual drift value sequence over multiple communication cycles, and store the historical drift vector to a block random access memory accessible by the processing system. Smoothing module: Used by the IgH master station kernel module running on the processing system to execute a double exponential smoothing algorithm to predict the predicted drift value for the next communication cycle using the historical drift vector; Correction module: Used by the IgH master station kernel module to adjust the reference clock time sent to one or more EtherCAT slave stations by superimposing the predicted drift value onto the reference clock time to provide feedforward compensation; Comparison module: If the change in the length of the extracted frame feature information exceeds a set threshold, the reconfiguration module executed on the processing system dynamically reconfigures the direct access storage descriptor ring. Gating module: for performing time-aware gating control on at least a first transmit queue and a second transmit queue by a multi-queue gating scheduler implemented in the Ethernet access controller of the processing system, wherein the first transmit queue is used to transmit real-time EtherCAT frames and the second transmit queue is used to transmit non-real-time network traffic, the gating control including disabling the second transmit queue during the guard band interval of the real-time communication cycle.

[0013] A third aspect of the present invention discloses an electronic device, comprising: a memory storing executable program code; a processor coupled to the memory; the processor calling the executable program code stored in the memory to execute the method for real-time optimization of the IGH ETHERCAT master station disclosed in the first aspect of the present invention.

[0014] A fourth aspect of the present invention discloses a computer-readable storage medium storing a computer program, wherein the computer program causes a computer to execute the method for real-time optimization of the IGH ETHERCAT master station disclosed in the first aspect of the present invention.

[0015] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: The real-time optimization method for IgH EtherCAT master stations in this embodiment of the invention systematically solves the real-time bottleneck faced by IgH EtherCAT master stations through four types of means: hardware acceleration of critical paths, predictive clock compensation, adaptive DMA scheduling, and time-aware queue isolation; ultimately achieving lower and more stable communication latency and higher clock synchronization accuracy. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating the method for real-time optimization of the IgH EtherCAT master station disclosed in an embodiment of the present invention. Figure 2 This is a schematic diagram of the dynamic reconfiguration process disclosed in an embodiment of the present invention; Figure 3 This is a schematic diagram of the feature matching process disclosed in an embodiment of the present invention. Figure 4 This is a schematic diagram of the structure of a system for real-time optimization of an IgH EtherCAT master station provided by an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that the terms "first," "second," "third," "fourth," etc., in the specification and claims of this invention are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "having," and any variations thereof, in the embodiments of this invention are intended to cover non-exclusive inclusion. Exemplarily, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0020] Example 1

[0021] Please see Figure 1 , Figure 1 This is a flowchart illustrating the method for real-time optimization of an IgH EtherCAT master station disclosed in an embodiment of the present invention. The execution entity of the method described in this embodiment is an execution entity composed of software and / or hardware. This execution entity can receive relevant information via wired and / or wireless means and can send certain instructions. It may also have certain processing and storage functions. This execution entity can control multiple devices, such as remote physical servers or cloud servers and related software, or local hosts or servers and related software that perform related operations on devices located in a certain location. In some scenarios, multiple storage devices can also be controlled; these storage devices may be placed in the same location as the devices or in different locations. Figure 1 As shown, the method based on real-time optimization for IgH EtherCAT master stations includes the following steps: S101: A data capture module implemented in programmable logic to perform real-time parsing of the EtherCAT frame header in the received data frame to extract frame feature information; S102: The data capture module stores the extracted frame feature information into a shared memory register accessible by the processing system; S103: A drift monitoring module implemented in the programmable logic monitors reference clock timestamps returned from one or more EtherCAT slave stations, calculates the actual drift value sequence over multiple communication cycles, and stores the historical drift vector in a block random access memory accessible by the processing system. S104: The IgH master station kernel module running on the processing system executes a double exponential smoothing algorithm to predict the predicted drift value for the next communication cycle using the historical drift vector; S105: The IgH master station kernel module adjusts the reference clock time sent to one or more EtherCAT slave stations by superimposing the predicted drift value onto the reference clock time to provide feedforward compensation; S106: If the change in the length of the extracted frame feature information exceeds a set threshold, the reconfiguration module executed on the processing system dynamically reconfigures the direct access to the storage descriptor ring. S107: A multi-queue gating scheduler implemented in the Ethernet access controller of the processing system performs time-aware gating control on at least a first transmission queue and a second transmission queue, wherein the first transmission queue is used to transmit real-time EtherCAT frames and the second transmission queue is used to transmit non-real-time network traffic, and the gating control includes disabling the second transmission queue during the guard band interval of the real-time communication cycle.

[0022] In this embodiment of the invention, the data acquisition module offloads the parsing of the EtherCAT frame header from the processing system (PS) to the programmable logic (PL), avoiding the problem of untimely frame information acquisition caused by CPU interrupts or kernel scheduling delays. Furthermore, the zero-copy mechanism of the shared memory registers allows the master station kernel module to directly and with low latency acquire frame feature information, reducing the data transmission overhead between the PS and PL. These mechanisms collectively shorten the processing latency of the communication cycle and significantly reduce latency jitter, providing a foundation for high-precision synchronous control.

[0023] The drift monitoring module continuously collects slave reference clock timestamps for multiple communication cycles at the hardware layer, generating a high-resolution historical drift vector. A dual exponential smoothing algorithm predicts drift trends in the master station kernel, which, compared to traditional proportional-integral compensation, more accurately captures drift changes and avoids overshoot or lag.

[0024] By superimposing the predicted drift value onto the reference clock time to achieve feedforward compensation, the clock adjustment commands sent by the master station are more forward-looking, effectively suppressing the cumulative effect of clock drift and improving the time synchronization accuracy of the entire network.

[0025] The frame length change threshold detection mechanism can sense changes in network load or frame structure (such as dynamic adjustment of the number of slave stations, changes in process data length, etc.). Dynamic reconfiguration of the DMA descriptor ring allows the data channel to quickly adapt to new frame lengths, avoiding frame loss or data misalignment due to insufficient or overflowing DMA buffers. This mechanism ensures the system's robustness to changes in communication scale during operation, eliminating the need for network downtime and reinitialization, thus improving system flexibility and availability.

[0026] The multi-queue gating scheduler, combined with a time-aware gating mechanism, strictly divides guard band intervals within the EtherCAT real-time communication cycle. During the guard band, the second transmission queue (non-real-time traffic) is disabled, ensuring that the transmission of real-time frames (the first transmission queue) is not blocked or interfered with by background network traffic. This mechanism eliminates the jitter caused by non-real-time traffic interference to real-time communication, ensuring that the transmission time of EtherCAT frames strictly conforms to the predetermined schedule, enhancing communication determinism and meeting the high deterministic requirements of periodic real-time data in industrial settings. Through these optimizations, the system offloads critical real-time paths (frame parsing, clock synchronization, DMA scheduling, and queue transmission) from software processing to hardware or with hardware assistance, significantly reducing CPU load.

[0027] More preferably, such as Figure 2 As shown, the dynamic reconfiguration of the direct access storage descriptor ring includes: S1061: Suspend the real-time communication cycle during the guard band interval; S1062: Recalculate the buffer length and memory alignment of multiple direct access memory descriptors based on the extracted frame feature information; S1063: Load the reconfigured descriptor table into the direct access memory engine of the processing system; S1064: Resume the real-time communication cycle.

[0028] In practice, the guard band is a reserved no-communication window in the EtherCAT real-time communication cycle (usually located between the end of a periodic data exchange and the start of the next cycle). Real-time communication cycles are paused within this window to ensure that the reconfiguration process does not result in the loss of real-time frames or transmission delays.

[0029] When the EtherCAT frame length changes (e.g., the number of slaves increases or decreases), the existing DMA buffer may not match the new frame structure, leading to data truncation, overwriting, or buffer overflow. Dynamically adjusting the buffer length ensures that the DMA can transfer the new frame completely; optimizing memory alignment improves memory access efficiency, especially at the AXI bus or DDR controller level, where aligned access reduces the number of accesses.

[0030] The above method completes the switching of descriptor table pointers all at once within the guard band window, rather than modifying descriptors one by one. This ensures that the DMA engine uses the new configuration parameters from the very first frame after communication is resumed, avoiding problems such as descriptor chain breaks or data being written to incorrect addresses that could result from mixing old and new configurations. Since the entire reconfiguration process is compressed within the guard band interval, and the guard band itself is not used for real-time data transmission, the effective bandwidth usage for the real-time cycle is zero. Compared to the common approach of dynamically allocating memory and reinitializing DMA at the software layer (which can take hundreds of microseconds to milliseconds), this method minimizes the impact of reconfiguration on real-time performance and ensures strict periodicity between adjacent communication cycles.

[0031] More preferably, the real-time optimization method further includes: The data capture module detects emergency service data object requests from the IgH master station kernel module; in response to the detection, while maintaining the real-time communication cycle, the second sending queue is temporarily activated to send emergency service requests. The solution in this invention provides a fast channel for urgent SDO requests while maintaining real-time communication cycles. When the data capture module detects an urgent SDO request from the IgH kernel, it temporarily activates a second sending queue. This mechanism breaks the conventional setting that the second queue is only activated during non-real-time traffic, allowing urgent configuration or diagnostic commands to be sent without waiting for the next non-real-time window.

[0032] Since the entire process does not interrupt the real-time communication cycle, the exchange of periodic process data (PDO) is still strictly carried out according to the gating schedule. Emergency SDOs are sent by temporarily borrowing guard bands or non-real-time time slots, which ensures low-latency response to emergency commands and avoids destructive interference to real-time traffic.

[0033] And / or, the real-time optimization method further includes: The phase comparator implemented in the EtherCAT slave station generates a Sync0 interrupt only when the phase difference between the slave station's local time and the corrected reference clock time sent from the master station is less than a predetermined threshold. The solution of this invention introduces intelligent interrupt generation logic at the EtherCAT slave hardware level, which effectively reduces slave processing overhead.

[0034] Traditional Sync0 interrupts are triggered unconditionally in every communication cycle, even if the deviation between the slave's local clock and the master's reference clock is very small. By using a phase comparator, an interrupt is generated only when the phase difference is less than a predetermined threshold, avoiding redundant interrupt triggering when synchronization accuracy requirements are met.

[0035] For slave microcontrollers (MCUs), reduced interrupt frequency means more processing cycles can be used for application-layer tasks (such as motor control algorithms and sensor data fusion), or a lower-cost slave processor can be selected for the same load. Lower interrupt frequency also reduces slave power consumption, especially in multi-axis systems (such as dozens or even hundreds of slaves), where the cumulative energy savings are more significant, meeting the green and energy-efficient requirements of industrial equipment. This approach avoids frequent interrupt responses caused by minor noise or jitter when the master and slave clocks are highly synchronized, further enhancing system stability.

[0036] And / or, the real-time optimization method further includes: The data capture module monitors the queue depth and sending request frequency of the second sending queue; A congestion flag is generated when the queue depth or the sending request frequency exceeds a predetermined threshold, wherein the gating control is adjusted according to the congestion flag.

[0037] This invention incorporates network congestion awareness into gating scheduling decisions, enabling adaptive coordination between real-time and non-real-time traffic. The data capture module continuously monitors the depth and sending request frequency of the second sending queue. When it detects an accumulation of non-real-time traffic or a sudden surge in requests, it generates a congestion flag. This mechanism enables the system to perceive non-real-time traffic pressure, rather than passively bearing the impact of congestion. The gating scheduler adaptively adjusts based on the congestion flag. When the congestion flag is set, the gating window of the second sending queue can be temporarily increased, or the guard band interval can be extended to allow more non-real-time data to be discharged, preventing queue overflow and packet loss. Once congestion is alleviated, the normal time-aware gating strategy is restored. The adjustment process always adheres to the real-time priority principle, ensuring that the deterministic transmission of the first sending queue (real-time EtherCAT frames) is not affected. Congestion control optimizes the quality of service for non-real-time traffic only while ensuring real-time performance.

[0038] More preferably, the double exponential smoothing algorithm includes: The horizontal and trend components are calculated based on the historical drift vector using a first smoothing factor for the horizontal component and a second smoothing factor for the trend component. The predicted drift value is calculated and determined based on the horizontal component and the trend component.

[0039] Specifically, EtherCAT clock drift typically exhibits two superimposed characteristics: a horizontal component, which reflects the current offset reference value, i.e., the static deviation of the slave clock relative to the master reference clock; and a trend component, which reflects the rate of drift change, i.e., the cumulative offset trend caused by the difference in crystal oscillator frequency.

[0040] By applying a first smoothing factor to the horizontal component and a second smoothing factor to the trend component, this algorithm can: smooth and filter the current value of the drift, suppressing measurement noise and instantaneous jitter; and independently model the trend of drift changes, capturing the long-term evolution of clock frequency deviation. Compared with traditional single-factor exponential smoothing or simple proportional-integral compensation, this method more accurately describes the physical nature of clock drift, providing a more precise prediction basis for subsequent feedforward compensation.

[0041] Industrial environments are susceptible to electromagnetic interference and bus arbitration jitter, which can cause transient noise in the timestamps returned from slave stations. The exponentially weighted averaging characteristic of the first smoothing factor effectively suppresses this high-frequency noise, preventing drastic fluctuations in predicted values. Even if the timestamp of a certain communication cycle becomes abnormal due to interference, the second smoothing factor, through the accumulation of historical trends, can still maintain a stable estimate of the drift rate of change, avoiding excessive influence of single-point anomalies on the prediction results. The final predicted drift value combines fast tracking capability and noise suppression capability, making feedforward compensation smoother and more stable.

[0042] The dual exponential smoothing algorithm of this invention can achieve unbiased prediction when the drift exhibits an approximately linear change (i.e., the crystal oscillator frequency deviation is basically constant).

[0043] For the EtherCAT distributed clock synchronization mechanism, this means that: the reference clock time compensation value sent by the master station can accurately offset the cumulative drift of the slave station; the phase difference between the master and slave clocks approaches zero in steady state, and the timing of the Sync0 interrupt generation is more precise.

[0044] More preferably, such as Figure 3 As shown, prior to the execution of the double exponential smoothing algorithm by the IgH master station kernel module running on the processing system, the following steps are also included: S1031: Construct a historical periodic feature template library, which includes multiple predefined time series templates. Each time series template corresponds to a periodic jitter mode, including normal mode, oscillation mode, sudden spike mode and drift mode. S1032: Extract the periodic execution time sequence and jitter sequence of the current communication cycle from the frame feature information to form the current cycle feature vector; S1033: Calculate the normalized distance between the current periodic feature vector and each template in the historical periodic feature template library; S1034: Select the periodic jitter pattern corresponding to the template with the smallest regularity distance as the current periodic jitter pattern recognition result; S1035: Adjust the smoothing factor parameter of the double exponential smoothing algorithm based on the current period jitter pattern recognition result.

[0045] Traditional double exponential smoothing algorithms use a fixed smoothing factor, which cannot adapt to changes in drift characteristics under different operating conditions. This proposed solution dynamically adjusts the smoothing factor through pattern recognition, achieving adaptive parameter optimization.

[0046] Specifically, dynamic time warping calculates the distance between the current period's feature vector and the template library using regularized distance, rather than simple Euclidean distance. Its advantage lies in the fact that the jitter sequence in EtherCAT communication cycles may have phase shifts; dynamic time warping, through non-linear alignment, can identify jitter patterns that are similar in shape but different in phase. Different templates may correspond to jitter features of different durations, and dynamic time warping naturally supports similarity measurement of sequences of unequal lengths; even if the current sequence has local compression or stretching, dynamic time warping can still accurately match the most similar template.

[0047] In this embodiment of the invention, both the periodic execution time series and the jitter sequence extracted can be directly obtained from the frame feature information already collected by the data capture module, without additional hardware overhead. The dimension of the feature vector is controllable. This scheme upgrades the drift prediction capability of the IgH master station from passive prediction with fixed parameters to active adaptation driven by a pattern. By identifying the jitter characteristics of the current communication cycle and dynamically configuring the most matching prediction parameters, the system maintains high accuracy in steady state, responds quickly in transient state, and operates robustly under abnormal conditions, significantly improving the adaptability of the EtherCAT master station to complex industrial environments and its long-term operational reliability.

[0048] This scheme introduces a template-matching-based periodic jitter pattern recognition mechanism before the execution of the double exponential smoothing algorithm. First, a historical periodic feature template library is constructed, including various predefined time-series templates such as normal mode, oscillation mode, sudden spike mode, and drift mode. The periodic execution time series and jitter sequence of the current communication cycle are extracted from frame feature information to form the current cycle feature vector. By calculating the normalization distance between the current cycle feature vector and each template, the periodic jitter pattern corresponding to the template with the smallest distance is selected as the recognition result. When calculating the normalization distance, a cumulative distance matrix between the current cycle feature vector and the template feature vector is constructed. A window constraint is applied to the cumulative distance matrix to limit the maximum allowable deviation of the normalization path from the diagonal. This width is determined based on the maximum allowable jitter value of the EtherCAT communication cycle. The cumulative distance matrix is ​​calculated using a recursive formula, and the lower right corner element is extracted as the normalization distance. This method achieves phase-insensitive robust matching, accurately matching even if the jitter waveform has phase shifts or local compression / stretching. Simultaneously, the window constraint effectively reduces computational complexity and prevents physically unreasonable alignment results.

[0049] More preferably, the step of calculating the normalized distance between the current periodic feature vector and each template in the historical periodic feature template library includes: Construct a cumulative distance matrix between the current periodic feature vector and the template feature vector, wherein the elements D in the cumulative distance matrix are... i,j This represents the minimum cumulative distance between the first i elements of the current periodic feature vector and the first j elements of the template feature vector; A window constraint is applied to the cumulative distance matrix to limit the maximum allowable deviation of the regularized path from the diagonal, wherein the maximum width is determined based on the maximum allowable jitter value of the EtherCAT communication cycle; The cumulative distance matrix is ​​calculated recursively using the following formula: D i,j = d i,j +min{D i-1,j D i,j-1 D i-1,j-1}, where d i,j The Euclidean distance between the i-th element of the current periodic feature vector and the j-th element of the template feature vector; Extract the bottom right element D of the cumulative distance matrix. n,m As the normalization distance, where n is the length of the current periodic feature vector and m is the length of the template feature vector; The scheme of this invention allows the current period feature vector and the template feature vector to be non-linearly scaled and aligned on the time axis, so that they can still be accurately matched even if there is a phase shift or local compression / stretching in the jitter waveforms of the two. The recursive formula ensures that the path from the starting point to the current point always selects the direction with the minimum cumulative distance, and the final D is obtained. n,m This is the total distance under the optimal regularized path.

[0050] The key parameter in this scheme, the window width, is directly related to the maximum allowable jitter value of the EtherCAT communication cycle, reflecting a deep adaptation to the real-time characteristics of EtherCAT. In the EtherCAT distributed clock synchronization mode, the jitter of the communication cycle is usually controlled within a very small range, and the corresponding window width can be set to a smaller value to further reduce the amount of computation.

[0051] The step of adjusting the smoothing factor parameters of the double exponential smoothing algorithm based on the current period jitter pattern recognition result includes: When the recognition result is normal mode, the first smoothing factor and the second smoothing factor are kept at their preset default values; When the identification result is an oscillation mode, the first smoothing factor is increased to enhance the response sensitivity to recent jitter; When the identification result is a sudden spike pattern, the second smoothing factor is increased to enhance the sensitivity to trend changes; When the identification result is a drift pattern, both the first smoothing factor and the second smoothing factor are increased to accelerate the tracking of the drift trend.

[0052] This invention adjusts the smoothing factor parameters of the dual exponential smoothing algorithm based on the identification results. When the identification result is in a normal mode, the first and second smoothing factors are kept at their preset default values ​​to maintain optimal noise suppression and prediction stability in steady state. When the identification result is in an oscillation mode, the first smoothing factor is increased to enhance the response sensitivity to recent jitter and reduce phase lag. When the identification result is in a sudden spike mode, the second smoothing factor is increased to enhance the response sensitivity to trend changes and avoid single-point anomalies affecting level estimation. When the identification result is in a drift mode, both the first and second smoothing factors are increased to accelerate the tracking of the drift trend and accelerate convergence to the new drift rate. This mode-driven parameter adaptation mechanism enables the predictor to maintain high accuracy in steady state, respond quickly in transient state, and operate robustly in abnormal state, significantly improving the adaptability of the EtherCAT master station to complex industrial environments and the reliability of long-term operation.

[0053] More preferably, the real-time optimization method further includes: The data capture module collects real-time performance index data, which includes the period jitter value between the actual communication period and the set period, the master-slave station distributed clock synchronization deviation value, the real-time thread scheduling delay value, the frame transmission delay value from submission by the direct memory access module to completion of transmission by the network card, the CPU load fluctuation value of the processor core, and the abnormal frame rate value, which is the proportion of abnormal frames to the total number of transmitted frames. The six real-time performance metrics collected were normalized to obtain the normalized values ​​of each metric. The six normalized values ​​are weighted and fused to obtain the original quality index; The minimum value among the six normalized values ​​is extracted, and a minimum value penalty is applied to the original quality index to obtain the real-time quality index; the real-time quality index is then used as a comprehensive evaluation parameter for the real-time performance of the IgH master station. The real-time quality index is compared with a preset first threshold and a second threshold, wherein the first threshold is greater than the second threshold; When the real-time performance quality index is greater than or equal to the first threshold, the current real-time performance is determined to be excellent, and the current parameter configuration is maintained. When the real-time performance quality index is between the second threshold and the first threshold, the current real-time performance is determined to be in a good state, and lightweight parameter fine-tuning is performed. When the real-time performance quality index is less than or equal to the second threshold, the current real-time performance is determined to be in a degraded state, and parameter reconfiguration is performed.

[0054] The solution in this invention establishes a complete real-time performance comprehensive evaluation and graded response mechanism. The data acquisition module collects six real-time performance metrics, including the period jitter between the actual communication period and the set period, the master-slave distributed clock synchronization deviation, the real-time thread scheduling latency, the frame transmission latency from submission by the direct memory access module to completion of network card transmission, the CPU load fluctuation of the processor core, and the abnormal frame rate (the proportion of abnormal frames to the total transmitted frames). These six metrics cover key domains of EtherCAT master station real-time performance, such as time synchronization, scheduling latency, data path, system load, and communication quality, enabling the system to fully perceive its own operating status.

[0055] Six real-time performance metrics were collected and normalized to obtain normalized values ​​for each metric. These values ​​were then weighted and fused to obtain the original quality index. Finally, the minimum value among the six normalized values ​​was extracted and applied as a minimum penalty to the original quality index, resulting in the real-time performance quality index, which serves as a comprehensive evaluation parameter for the IgH master station's real-time performance. Weighted fusion reflects the overall average performance level, avoiding the excessive influence of occasional fluctuations in a single metric on the evaluation results. The minimum penalty reflects the "weakest link" effect, ensuring that the system's real-time performance is limited by its weakest link; even if five metrics perform well, a severe deterioration in any one metric will lower the real-time performance quality index.

[0056] The real-time performance quality index is compared with a preset first threshold and a second threshold, where the first threshold is greater than the second threshold. When the real-time performance quality index is greater than or equal to the first threshold, the current real-time performance is considered excellent, and the current parameter configuration is maintained to avoid unnecessary adjustments that introduce additional overhead or disturbances. When the real-time performance quality index is between the second and first thresholds, the current real-time performance is considered good, and lightweight parameter fine-tuning is performed to prevent further performance degradation during minor performance fluctuations. When the real-time performance quality index is less than or equal to the second threshold, the current real-time performance is considered degraded, and parameter reconfiguration is performed to take proactive recovery measures to ensure the basic functions of the system in the event of a severe performance decline.

[0057] This hierarchical response mechanism uses performance evaluation results as feedback input for various optimization mechanisms, forming a complete closed-loop control system encompassing perception, evaluation, decision-making, and execution. This enables the system to possess self-perception, self-decision-making, and self-optimization capabilities. The acquisition of all six performance indicators reuses existing data capture modules, requiring no additional hardware resources and reducing implementation costs.

[0058] More preferably, the lightweight parameter fine-tuning includes: The most severely degraded indicator is determined by multiplying the normalized value of each indicator by its weight. When the most severely degraded metric is periodic jitter, the first smoothing factor of the double exponential smoothing algorithm is increased to enhance the response to jitter. When the most severely degraded indicator is the synchronization deviation, the second smoothing factor of the double exponential smoothing algorithm is increased to enhance the tracking of the drift trend; When the most severe degradation indicator is scheduling delay or frame transmission delay, adjust the protection band interval of the multi-queue gating scheduler. When the most severe degradation metric is CPU load fluctuation, reduce the sampling frequency of the data capture module. When the most severely degraded metric is the abnormal frame rate, the link diagnostic process is triggered. The parameter reconfiguration includes: When the real-time performance quality index is less than or equal to the second threshold, record all current parameter configurations and real-time performance indicators. Iterate through multiple preset parameter configuration templates and select the template that maximizes the improvement in real-time quality index prediction. Perform a parameter configuration template switching operation, which includes switching the direct memory access descriptor configuration, adjusting the guard band interval, and updating the smoothing factor parameters; and recalculate the real-time quality index after the switching is completed to verify the optimization effect.

[0059] The solution in this embodiment of the invention further refines the specific execution strategies for lightweight parameter fine-tuning and parameter reconfiguration in the hierarchical response mechanism, providing the IgH EtherCAT master station with the ability to accurately locate performance bottlenecks, implement targeted optimization measures, and systematically restore the system state.

[0060] In terms of lightweight parameter fine-tuning, this scheme first accurately identifies the most severely degraded metric by multiplying the normalized value of each metric by its weight. This design ensures the targeted nature of the fine-tuning operation and avoids unnecessary disturbances that might be introduced by blind adjustments. When the most severely degraded metric is identified as periodic jitter, the response to jitter is enhanced by increasing the first smoothing factor of the double exponential smoothing algorithm, enabling the predictor to track the fluctuations in the communication cycle more quickly and effectively reducing phase lag. When the most severely degraded metric is synchronization deviation, the tracking of drift trends is enhanced by increasing the second smoothing factor of the double exponential smoothing algorithm, accelerating the convergence speed of the predictor for slave clock frequency deviations, thereby reducing the steady-state synchronization error between the master and slave stations. When the most severely degraded metric is scheduling delay or frame transmission delay, the allocation of time resources is optimized by adjusting the guard band interval of the multi-queue gating scheduler. Appropriately increasing the guard band can provide more time margin for real-time thread scheduling and frame transmission, alleviating the delay problem caused by scheduling constraints. When the most severe degradation metric is CPU load fluctuation, the system overhead is reduced by decreasing the sampling frequency of the data capture module. This releases processing resources while ensuring basic monitoring capabilities, preventing further deterioration of the load fluctuation. When the most severe degradation metric is abnormal frame rate, the link diagnostic process is triggered to proactively investigate physical layer issues, such as checking network cable connection status, electromagnetic interference sources, or slave station communication quality. This addresses communication quality problems at their root, rather than simply adjusting the master station parameters.

[0061] Because the fine-tuning only targets a single degradation metric and adjusts local parameters, the process can be completed in a very short time, typically without affecting the normal execution of the next real-time communication cycle. Furthermore, the fine-tuning is controllable and reversible; if performance does not improve or new problems arise after the fine-tuning, the system can quickly revert to its pre-adjustment configuration, ensuring system stability.

[0062] Regarding parameter reconfiguration, when the real-time performance quality index deteriorates below the second threshold, the system determines that the current state cannot be recovered through fine-tuning and a more thorough reconfiguration operation is required. This solution first records all current parameter configurations and real-time performance metrics to provide a data foundation for subsequent optimization effect verification and problem tracing. Then, it iterates through multiple preset parameter configuration templates, which typically cover different operating scenarios, such as high-load scenario templates, high-synchronization-accuracy scenario templates, and low-latency scenario templates. By estimating the improvement in the real-time performance quality index after applying each template, the template with the largest estimated improvement is selected for switching.

[0063] The parameter configuration template switching operation covers multiple levels, including switching the direct memory access descriptor configuration to adapt to changing frame structure characteristics, adjusting the guard band interval to reallocate the time windows of real-time and non-real-time traffic, and updating the smoothing factor parameters of the dual exponential smoothing algorithm to match the current drift characteristics. After the switch is completed, the real-time quality index is recalculated to verify the optimization effect, forming a closed-loop verification mechanism.

[0064] The value of the aforementioned reconfiguration mechanism lies in its systematic recovery capabilities and self-evolution potential. When the system deviates from its optimal operating state due to sudden anomalies or long-term degradation, the reconfiguration operation can switch the entire system to a pre-validated stable configuration template, achieving rapid recovery and avoiding the delays and uncertainties of manual intervention. Simultaneously, the system can record the parameter configurations and performance indicators before and after reconfiguration for offline analysis and continuous optimization of the template library. This allows the preset configuration templates to be continuously updated based on actual operating data, improving the template coverage and effectiveness.

[0065] The above solution achieves refined diagnosis and layered processing of system performance issues through a two-level response mechanism of lightweight fine-tuning and parameter reconfiguration. Lightweight fine-tuning resolves minor performance fluctuations in a low-intrusive manner, while parameter reconfiguration restores severe performance degradation through a systematic approach. The two work together to ensure that the IgH EtherCAT master station maintains optimal operating conditions in complex and ever-changing industrial environments.

[0066] The real-time optimization method for IgH EtherCAT master stations in this embodiment of the invention systematically solves the real-time bottleneck faced by IgH EtherCAT master stations through four types of means: hardware acceleration of critical paths, predictive clock compensation, adaptive DMA scheduling, and time-aware queue isolation; ultimately achieving lower and more stable communication latency and higher clock synchronization accuracy.

[0067] Example 2

[0068] Please see Figure 4 , Figure 4 This is a schematic diagram of the system structure for real-time optimization of the IgH EtherCAT master station disclosed in an embodiment of the present invention. Figure 4 As shown, the system for real-time optimization of the IgH EtherCAT master station may include: Parsing module 21: This module is used to run a data capture module implemented in programmable logic to parse the EtherCAT frame header in the received data frame in real time to extract frame feature information. Storage module 22: used to store the extracted frame feature information by the data capture module into a shared memory register accessible by the processing system; Monitoring module 23: A drift monitoring module implemented in the programmable logic is used to monitor reference clock timestamps returned from one or more EtherCAT slave stations, calculate the actual drift value sequence over multiple communication cycles, and store the historical drift vector to a block random access memory accessible by the processing system. Smoothing module 24: Used by the IgH master station kernel module running on the processing system to execute a double exponential smoothing algorithm to predict the predicted drift value of the next communication cycle using the historical drift vector; Correction module 25: used by the IgH master station kernel module to adjust the reference clock time sent to one or more EtherCAT slave stations by superimposing the predicted drift value onto the reference clock time to provide feedforward compensation; Comparison module 26: If the change in the length of the extracted frame feature information exceeds a set threshold, the reconfiguration module executed on the processing system dynamically reconfigures the direct access storage descriptor ring. Gating module 27: for performing time-aware gating control on at least a first transmit queue and a second transmit queue by a multi-queue gating scheduler implemented in the Ethernet access controller of the processing system, wherein the first transmit queue is used to transmit real-time EtherCAT frames and the second transmit queue is used to transmit non-real-time network traffic, the gating control including disabling the second transmit queue during the guard band interval of the real-time communication cycle.

[0069] The real-time optimization method for IgH EtherCAT master stations in this embodiment of the invention systematically solves the real-time bottleneck faced by IgH EtherCAT master stations through four types of means: hardware acceleration of critical paths, predictive clock compensation, adaptive DMA scheduling, and time-aware queue isolation; ultimately achieving lower and more stable communication latency and higher clock synchronization accuracy.

[0070] Example 3

[0071] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device disclosed in an embodiment of the present invention. The electronic device can be a computer, a server, etc. Of course, in certain cases, it can also be a mobile phone, tablet computer, monitoring terminal, or other smart device, as well as an image acquisition device with processing capabilities. Figure 5 As shown, the electronic device may include: Memory 510 storing executable program code; Processor 520 coupled to memory 510; The processor 520 calls the executable program code stored in the memory 510 to execute some or all of the steps in the method for real-time optimization of the IgH EtherCAT master station in Embodiment 1.

[0072] This invention discloses a computer-readable storage medium storing a computer program that causes a computer to perform some or all of the steps in the method for real-time optimization of an IgH EtherCAT master station as described in Embodiment 1.

[0073] This invention also discloses a computer program product, wherein when the computer program product is run on a computer, the computer performs some or all of the steps in the method for real-time optimization of the IgH EtherCAT master station in Embodiment 1.

[0074] This invention also discloses an application publishing platform, which is used to publish computer program products. When the computer program products are run on a computer, the computer performs some or all of the steps in the method for real-time optimization of the IgH EtherCAT master station in Embodiment 1.

[0075] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0076] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they can be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0077] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0078] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-accessible memory. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several requests to cause a computer device (which can be a personal computer, server, or network device, specifically a processor in the computer device) to execute some or all of the steps of the methods described in the various embodiments of the present invention.

[0079] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0080] Those skilled in the art will understand that some or all of the steps in the various methods of the embodiments described can be implemented by a program instructing related hardware. This program can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-Erasable Programmable Read-Only Memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0081] The foregoing has provided a detailed description of the method, system, electronic device, and storage medium for real-time optimization of the IgH EtherCAT master station disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for real-time optimization of IgH EtherCAT master stations, characterized in that, include: A data capture module implemented in programmable logic is used to parse the EtherCAT frame header in the received data frame in real time to extract frame feature information; The data capture module stores the extracted frame feature information into a shared memory register accessible by the processing system. The drift monitoring module, implemented in the programmable logic, monitors reference clock timestamps returned from one or more EtherCAT slave stations, calculates the actual drift value sequence over multiple communication cycles, and stores the historical drift vector in a block random access memory accessible by the processing system. A historical periodic feature template library is constructed, which includes multiple predefined time series templates. Each time series template corresponds to a periodic jitter mode, which includes normal mode, oscillation mode, sudden spike mode and drift mode. Extract the periodic execution time sequence and jitter sequence of the current communication cycle from the frame feature information to form the current cycle feature vector; Calculate the normalized distance between the current periodic feature vector and each template in the historical periodic feature template library; the calculation of the normalized distance between the current periodic feature vector and each template in the historical periodic feature template library includes: constructing a cumulative distance matrix between the current periodic feature vector and the template feature vector, wherein the elements D in the cumulative distance matrix i,j This represents the minimum cumulative distance between the first i elements of the current period feature vector and the first j elements of the template feature vector; a window constraint is applied to the cumulative distance matrix to limit the maximum allowable deviation of the regularized path from the diagonal, wherein the maximum width is determined based on the maximum allowable jitter value of the EtherCAT communication cycle; the cumulative distance matrix is ​​calculated recursively, and the recursive formula is: D i,j = d i,j +min{D i-1,j D i,j-1 D i-1,j-1 }, where d i,j The Euclidean distance between the i-th element of the current periodic feature vector and the j-th element of the template feature vector is calculated; the bottom right element D of the cumulative distance matrix is ​​extracted. n,m As the normalization distance, where n is the length of the current periodic feature vector and m is the length of the template feature vector; The periodic jitter pattern corresponding to the template with the smallest regularity distance is selected as the current periodic jitter pattern recognition result; Based on the current period jitter pattern recognition result, the smoothing factor parameters of the double exponential smoothing algorithm are adjusted; the double exponential smoothing algorithm includes: using a first smoothing factor for the horizontal component and a second smoothing factor for the trend component, calculating the horizontal component and the trend component based on the historical drift vector; and calculating and determining the predicted drift value based on the horizontal component and the trend component. The step of adjusting the smoothing factor parameters of the double exponential smoothing algorithm based on the current period jitter pattern recognition result includes: When the recognition result is normal mode, the first smoothing factor and the second smoothing factor are kept at their preset default values; When the identification result is an oscillation mode, the first smoothing factor is increased to enhance the response sensitivity to recent jitter; When the identification result is a sudden spike pattern, the second smoothing factor is increased to enhance the sensitivity to trend changes; When the identification result is a drift pattern, both the first smoothing factor and the second smoothing factor are increased to accelerate the tracking of the drift trend; The IgH master station kernel module running on the processing system executes a double exponential smoothing algorithm to predict the predicted drift value for the next communication cycle using the historical drift vector; The IgH master station kernel module provides feedforward compensation by superimposing the predicted drift value onto the reference clock time and adjusting the reference clock time sent to one or more EtherCAT slave stations. If the change in the length of the extracted frame feature information exceeds a set threshold, the reconfiguration module executed on the processing system dynamically reconfigures the direct access to the storage descriptor ring. A multi-queue gating scheduler implemented in the Ethernet access controller of the processing system performs time-aware gating control on at least a first transmit queue and a second transmit queue, wherein the first transmit queue is used to transmit real-time EtherCAT frames and the second transmit queue is used to transmit non-real-time network traffic, and the gating control includes disabling the second transmit queue during the guard band interval of the real-time communication cycle.

2. The method for real-time optimization of IgH EtherCAT master stations as described in claim 1, characterized in that, The dynamic reconfiguration of the direct access storage descriptor ring includes: The real-time communication cycle is paused during the guard band interval; The buffer lengths and memory alignments of multiple direct access memory descriptors are recalculated based on the extracted frame feature information. The reconfigured descriptor table is loaded into the direct access storage engine of the processing system; Restore the real-time communication cycle.

3. The method for real-time optimization of IgH EtherCAT master stations as described in claim 1, characterized in that, The real-time optimization method further includes: The data capture module detects emergency service data object requests from the IgH master station kernel module; in response to the detection, while maintaining the real-time communication cycle, the second sending queue is temporarily activated to send emergency service requests. And / or, the real-time optimization method further includes: The phase comparator implemented in the EtherCAT slave station generates a Sync0 interrupt only when the phase difference between the slave station's local time and the corrected reference clock time sent from the master station is less than a predetermined threshold. And / or, the real-time optimization method further includes: The data capture module monitors the queue depth and sending request frequency of the second sending queue; A congestion flag is generated when the queue depth or the sending request frequency exceeds a predetermined threshold, wherein the gating control is adjusted according to the congestion flag.

4. The method for real-time optimization of IgH EtherCAT master stations as described in claim 1, characterized in that, The real-time optimization method further includes: The data capture module collects real-time performance index data, which includes the period jitter value between the actual communication period and the set period, the master-slave station distributed clock synchronization deviation value, the real-time thread scheduling delay value, the frame transmission delay value from submission by the direct memory access module to completion of transmission by the network card, the CPU load fluctuation value of the processor core, and the abnormal frame rate value, which is the proportion of abnormal frames to the total number of transmitted frames. The six real-time performance metrics collected were normalized to obtain the normalized values ​​of each metric. The six normalized values ​​are weighted and fused to obtain the original quality index; The minimum value among the six normalized values ​​is extracted, and a minimum value penalty is applied to the original quality index to obtain the real-time quality index; the real-time quality index is then used as a comprehensive evaluation parameter for the real-time performance of the IgH master station. The real-time quality index is compared with a preset first threshold and a second threshold, wherein the first threshold is greater than the second threshold; When the real-time performance quality index is greater than or equal to the first threshold, the current real-time performance is determined to be excellent, and the current parameter configuration is maintained. When the real-time performance quality index is between the second threshold and the first threshold, the current real-time performance is determined to be in a good state, and lightweight parameter fine-tuning is performed. When the real-time performance quality index is less than or equal to the second threshold, the current real-time performance is determined to be in a degraded state, and parameter reconfiguration is performed.

5. The method for real-time optimization of IgH EtherCAT master stations as described in claim 4, characterized in that, The lightweight parameter fine-tuning includes: The most severely degraded indicator is determined by multiplying the normalized value of each indicator by its weight. When the most severely degraded metric is periodic jitter, the first smoothing factor of the double exponential smoothing algorithm is increased to enhance the response to jitter. When the most severely degraded indicator is the synchronization deviation, the second smoothing factor of the double exponential smoothing algorithm is increased to enhance the tracking of the drift trend; When the most severe degradation indicator is scheduling delay or frame transmission delay, adjust the protection band interval of the multi-queue gating scheduler. When the most severe degradation metric is CPU load fluctuation, reduce the sampling frequency of the data capture module; When the most severely degraded metric is the abnormal frame rate, the link diagnostic process is triggered. The parameter reconfiguration includes: When the real-time performance quality index is less than or equal to the second threshold, record all current parameter configurations and real-time performance indicators. Iterate through multiple preset parameter configuration templates and select the template that maximizes the improvement in real-time quality index prediction. Perform a parameter configuration template switching operation, which includes switching the direct memory access descriptor configuration, adjusting the guard band interval, and updating the smoothing factor parameters; and recalculate the real-time quality index after the switching is completed to verify the optimization effect.

6. A system for real-time optimization of IgH EtherCAT master stations, characterized in that, include: Parsing module: This module, implemented in programmable logic, is used to perform real-time parsing of the EtherCAT frame header in the received data frame to extract frame feature information. Storage module: used to store the extracted frame feature information by the data capture module into a shared memory register accessible by the processing system; Monitoring module: A drift monitoring module implemented in the programmable logic is used to monitor reference clock timestamps returned from one or more EtherCAT slave stations, calculate the actual drift value sequence over multiple communication cycles, and store the historical drift vector to a block random access memory accessible by the processing system. A historical periodic feature template library is constructed, which includes multiple predefined time series templates. Each time series template corresponds to a periodic jitter mode, which includes normal mode, oscillation mode, sudden spike mode and drift mode. Extract the periodic execution time sequence and jitter sequence of the current communication cycle from the frame feature information to form the current cycle feature vector; Calculate the normalized distance between the current periodic feature vector and each template in the historical periodic feature template library; the calculation of the normalized distance between the current periodic feature vector and each template in the historical periodic feature template library includes: constructing a cumulative distance matrix between the current periodic feature vector and the template feature vector, wherein the elements D in the cumulative distance matrix i,j This represents the minimum cumulative distance between the first i elements of the current period feature vector and the first j elements of the template feature vector; a window constraint is applied to the cumulative distance matrix to limit the maximum allowable deviation of the regularized path from the diagonal, wherein the maximum width is determined based on the maximum allowable jitter value of the EtherCAT communication cycle; the cumulative distance matrix is ​​calculated recursively, and the recursive formula is: D i,j = d i,j +min{D i-1,j D i,j-1 D i-1,j-1 }, where d i,j The Euclidean distance between the i-th element of the current periodic feature vector and the j-th element of the template feature vector is calculated; the bottom right element D of the cumulative distance matrix is ​​extracted. n,m As the normalization distance, where n is the length of the current periodic feature vector and m is the length of the template feature vector; The periodic jitter pattern corresponding to the template with the smallest regularity distance is selected as the current periodic jitter pattern recognition result; Based on the current period jitter pattern recognition result, the smoothing factor parameters of the double exponential smoothing algorithm are adjusted; the double exponential smoothing algorithm includes: using a first smoothing factor for the horizontal component and a second smoothing factor for the trend component, calculating the horizontal component and the trend component based on the historical drift vector; and calculating and determining the predicted drift value based on the horizontal component and the trend component. The step of adjusting the smoothing factor parameters of the double exponential smoothing algorithm based on the current period jitter pattern recognition result includes: When the recognition result is normal mode, the first smoothing factor and the second smoothing factor are kept at their preset default values; When the identification result is an oscillation mode, the first smoothing factor is increased to enhance the response sensitivity to recent jitter; When the identification result is a sudden spike pattern, the second smoothing factor is increased to enhance the sensitivity to trend changes; When the identification result is a drift pattern, both the first smoothing factor and the second smoothing factor are increased to accelerate the tracking of the drift trend; Smoothing module: Used by the IgH master station kernel module running on the processing system to execute a double exponential smoothing algorithm to predict the predicted drift value for the next communication cycle using the historical drift vector; Correction module: Used by the IgH master station kernel module to adjust the reference clock time sent to one or more EtherCAT slave stations by superimposing the predicted drift value onto the reference clock time to provide feedforward compensation; Comparison module: If the change in the length of the extracted frame feature information exceeds a set threshold, the reconfiguration module executed on the processing system dynamically reconfigures the direct access storage descriptor ring. Gating module: for performing time-aware gating control on at least a first transmit queue and a second transmit queue by a multi-queue gating scheduler implemented in the Ethernet access controller of the processing system, wherein the first transmit queue is used to transmit real-time EtherCAT frames and the second transmit queue is used to transmit non-real-time network traffic, the gating control including disabling the second transmit queue during the guard band interval of the real-time communication cycle.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program causes a computer to perform the method for real-time optimization of an IgH EtherCAT master as described in any one of claims 1 to 5.

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