An embedded hardware rendering signal processing method and device, a terminal and a medium

Abstract

The application discloses an embedded hardware rendering signal processing method and device, a terminal and a medium, relates to the technical field of ultra-high-definition video signal processing, and has the technical scheme as follows: multiple types of heterogeneous signals are uniformly formatted and synchronously calibrated, and a signal source to be processed is selected to obtain a standardized baseband signal; according to the manufacturing task requirements of different buses in the multiple buses, the standardized baseband signal is subjected to differentiated exclusive rendering operation; the rendered signal is distributed to the corresponding bus and transmitted to the next stage of the distributed processing unit based on the logic of the multiple-bus isolation and the distributed unit cascade; the signals of each bus after cascade processing are synthesized and converted into a target format for independent output. The application realizes the deep adaptation of the software processing logic and the multiple-bus distributed hardware architecture by constructing the complete pipeline processing method of signal standardization preprocessing, bus exclusive rendering, collaborative isolation distribution and synthesis output.

Description

Technical Field

[0001] This invention relates to the field of ultra-high-definition video signal processing technology, and more specifically, to an embedded hardware rendering signal processing method, apparatus, terminal, and medium. Background Technology

[0002] The ultra-high-definition (4K / 8K) audiovisual industry has placed increasingly stringent demands on the real-time performance, low latency, high resource utilization, and flexible scalability of video signal processing. Multi-bus distributed embedded hardware architectures, characterized by stackable performance and flexible scalability, have become the mainstream development trend in this field.

[0003] However, existing signal processing methods still follow the processing logic of traditional centralized or single-bus architectures, and have failed to be specifically designed for the core architectural feature of "multi-bus + distributed". As a result, the potential advantages of this architecture cannot be fully utilized and there are several significant defects. The specific problems are as follows: (1) The existing method lacks a multi-bus distributed collaborative mechanism. The signal flow between the distributed processing unit and multiple buses has redundant interaction, resulting in high processing delay and difficulty in meeting the real-time requirements of ultra-high-definition video live broadcast scenarios; (2) It fails to combine the task division characteristics of the multi-bus with the cascading characteristics of the distributed unit to adopt the same processing logic for different production tasks (such as broadcasting, pre-monitoring, and monitoring), and it cannot realize the sharing of a single signal source among multiple buses, resulting in low hardware resource utilization; (3) The signal distribution mechanism only realizes single-dimensional isolation (only bus isolation or only unit isolation), and fails to build a dual collaborative isolation system of "multi-bus + distributed unit", which is prone to signal resource contention and affects the stability of system processing; (4) The existing method is not adaptable to the multi-bus distributed architecture. When adding a distributed processing unit or expanding the bus function, the processing logic needs to be redesigned, which is difficult to adapt to the needs of dynamic architecture expansion and the system has poor scalability.

[0004] The aforementioned problems severely restrict the release of the performance potential of multi-bus distributed hardware architecture. Therefore, the industry urgently needs an embedded video rendering and signal processing method that is centered on "multi-bus distributed" and deeply adapted to the hardware architecture, so as to fully leverage the dual advantages of multi-bus task division and the scalability of distributed units. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide an embedded hardware rendering signal processing method, apparatus, terminal, and medium. By constructing a complete pipelined processing method that includes signal standardization preprocessing, bus-specific rendering, collaborative isolation distribution, and composite output, the invention achieves deep adaptation between software processing logic and multi-bus distributed hardware architecture.

[0006] The above-mentioned technical objective of the present invention is achieved through the following technical solution: In a first aspect, an embedded hardware rendering signal processing method is provided, applied to a hardware architecture comprising physically isolated multiple buses and multiple cascaded distributed processing units, the method comprising: The input heterogeneous signals of various types are formatted and synchronously calibrated, and the signal source to be processed is selected to obtain a standardized baseband signal; The distributed processing unit performs differentiated, dedicated rendering operations on the standardized baseband signal according to the production task requirements corresponding to different buses in the multi-bus system. The rendered signal is distributed to the corresponding bus and passed to the next level of distributed processing unit based on the logic of multi-bus isolation and distributed unit cascading; among them, it supports the synchronous distribution of the same signal source to multiple buses. In the final distributed processing unit, the signals from each bus after cascading processing are combined and converted into the target format for independent output.

[0007] Furthermore, the process of unifying the format and synchronizing the input heterogeneous signals of various types includes: Hardware format conversion is performed on the aforementioned heterogeneous signals to obtain a baseband signal with a unified format; Clock recovery and frame-level synchronization calibration are performed on the baseband signal.

[0008] Furthermore, the production task requirements corresponding to the different buses include at least two of the following: PGM broadcast task, PVW pre-monitoring task, and MV multi-screen monitoring task. The differentiated, proprietary rendering operations include scaling, overlaying, and special effects creation.

[0009] Furthermore, the logic based on multi-bus isolation and distributed unit cascading, distributing to the corresponding bus and passing to the next-level distributed processing unit, includes: The rendered signals are distributed according to bus tasks to achieve physical isolation between different bus signals; The signals distributed to each bus are output to the next level of distributed processing unit as input signals for pipelined processing.

[0010] Furthermore, in the final stage of the distributed processing unit, the signals from each bus after cascaded processing are synthesized and converted into the target format for independent output, specifically as follows: The signals corresponding to the PGM broadcasting task, PVW pre-monitoring task, and MV multi-screen monitoring task are respectively synthesized into independent baseband streams; Each baseband stream is independently converted to SDI, ST2110, or network stream format for output.

[0011] Furthermore, the method is applied to a converged switcher scenario, wherein: The multi-bus includes PGM bus, PVW bus, and MV bus; The distributed processing unit includes R card, M0 card and M1 card cascaded in sequence; The differentiated dedicated rendering operations, distribution, and transmission are executed sequentially among the R card, M0 card, and M1 card; The method achieves an end-to-end latency of less than or equal to 20ms.

[0012] Furthermore, the method is applied to slow-motion and highlight replay scenarios, wherein: The multi-bus includes the PGM0 bus and PGM1 bus for dual-channel slow-motion production, as well as the MV bus; The differentiated rendering operation performed on the standardized baseband signal includes: performing video file decoding and speed-up / slow-motion rendering on the signals of the PGM0 bus and the PGM1 bus according to the slow-motion production logic scheduled by the application layer.

[0013] Secondly, an embedded hardware rendering signal processing device is provided, applied to a hardware architecture comprising physically isolated multi-bus and multiple cascaded distributed processing units, the device comprising: The preprocessing module is used to unify the format and synchronize the input heterogeneous signals of various types, and select the signal source to be processed to obtain a standardized baseband signal; The rendering module is used by the distributed processing unit to perform differentiated and dedicated rendering operations on the standardized baseband signal according to the production task requirements corresponding to different buses in the multi-bus system. The distribution and cascading module is used to distribute the rendered signal to the corresponding bus and pass it to the next level of distributed processing unit based on the logic of multi-bus isolation and distributed unit cascading; it supports the synchronous distribution of the same signal source to multiple buses. The synthesis output module is used in the last-stage distributed processing unit to synthesize the signals from each bus after cascading processing and convert them into the target format for independent output.

[0014] Thirdly, a computer terminal is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement an embedded hardware rendering signal processing method as described in any one of the first aspects.

[0015] Fourthly, a computer-readable medium is provided having a computer program stored thereon, the computer program being executed by a processor to implement an embedded hardware rendering signal processing method as described in any one of the first aspects.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention proposes an embedded hardware rendering signal processing method that decouples and reorganizes the traditional centralized signal processing flow, strictly adhering to the two core hardware characteristics of multi-bus task division and cascading transmission of distributed units. Logically, it starts with standardized preprocessing to lay a consistent signal foundation for subsequent distributed processing; it achieves parallel task processing through bus-specific rendering; and it ensures the order and efficiency of signal flow in complex architecture through collaborative isolation distribution; finally, it synthesizes the output. This method solves the comprehensive technical problems of high latency, low resource utilization, and poor scalability caused by the mismatch between processing logic and hardware architecture in existing technologies. It fully leverages the dual advantages of hardware multi-bus isolated concurrency and distributed performance stacking, simultaneously achieving low latency, high throughput, high resource utilization, and high system scalability in ultra-high-definition video processing scenarios.

[0017] 2. This invention eliminates the differences in format and timing between different signal sources through hardware-level preprocessing, generating a standardized baseband signal stream with strict timing alignment and unified format. This ensures that when performing parallel and pipelined rendering on multiple distributed processing units and multiple buses, all processing nodes operate based on a consistent and synchronized signal reference. This avoids processing misalignment, screen tearing, or synchronization loss caused by differences in signal sources, and solves the technical problem of poor signal synchronization consistency in distributed systems. It provides a reliable and consistent data source guarantee for the entire low-latency, high-stability multi-bus distributed processing link.

[0018] 3. This invention allocates differentiated rendering pipelines on a dedicated physical bus based on the varying requirements for signal quality, processing complexity, and real-time performance of different tasks such as broadcasting, pre-monitoring, and monitoring. For example, in slow-motion scenes, video decoding and variable-speed rendering tasks are allocated to the PGM0 / PGM1 bus. This solves the problem of complex resource allocation and mutual interference caused by different tasks competing for the same processing resources in traditional solutions. It achieves truly dedicated channels for each task, enabling core tasks such as broadcasting and pre-monitoring to obtain deterministic processing resources and quality assurance. At the same time, tasks such as multi-screen monitoring can be performed in parallel without conflict, significantly improving the system's parallel processing capability and overall determinism.

[0019] 4. In the signal distribution stage, this invention achieves hard isolation of signals from different tasks through a physical bus to prevent preemption and crosstalk; it also uses cascading transmission to linearly transmit bus signals as a whole pipeline between distributed units, constructing a processing pipeline. Simultaneously, a single signal source can be injected into multiple buses, realizing one-time signal access and parallel multiplexing of multiple tasks. This technology solves the problems of chaotic signal flow management and redundant copying leading to latency and resource waste in distributed architectures. While ensuring strict order and non-interference of signal flows, it minimizes signal copying and transmission overhead, thereby reducing overall system latency and significantly improving the utilization efficiency of input signal resources.

[0020] 5. This invention decouples complex switcher processing tasks (such as multi-screen compositing, keying, and special effects) onto three dedicated hardware units and forms three parallel processing pipelines on the PGM, PVW, and MV buses. This matrix-style collaborative logic of three units × three buses makes signal processing resemble a highly coordinated industrial assembly line, solving the stringent technical problem of extremely low end-to-end latency (usually required within the frame level) in large-scale live broadcast scenarios. It achieves industry-leading performance with end-to-end latency ≤20 milliseconds, fully meeting the real-time requirements of ultra-high-definition live broadcasts. At the same time, the system can linearly expand input channels by adding R-cards and other units, exhibiting excellent scalability. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart from Embodiment 1 of the present invention; Figure 2 This is a system block diagram in Embodiment 4 of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of this invention are only for explaining this invention and are not intended to limit this invention.

[0023] Example 1: An embedded hardware rendering signal processing method, applicable to hardware architectures including physically isolated multi-bus systems and multiple cascaded distributed processing units, such as... Figure 1 As shown, the specific implementation steps are as follows.

[0024] S1: Perform format unification and synchronous calibration on the input heterogeneous signals of various types, and select the signal source to be processed to generate a standardized baseband signal.

[0025] In complex multimedia processing systems, various heterogeneous signals, such as SDI (Serial Digital Interface), ST2110 (IP Video Standard), NVI (Network Video Interface), network streams, and various audio and video files, are flexibly connected to a multi-bus distributed architecture through dedicated hardware interfaces. This architecture design allows these signals to be seamlessly integrated into any level of distributed processing unit, thereby achieving high scalability and modular layout, providing fundamental support for large-scale signal integration. Through its built-in hardware logic, the system performs three key standard preprocessing operations: First, it performs hardware-level format conversion on the heterogeneous input signals, unifying signals from different sources into a standard baseband format. This process not only eliminates format differences between signals but also improves signal interoperability, ensuring compatibility in subsequent processing stages. Next, the system completes clock recovery and frame-level synchronization calibration. Through precise clock extraction and synchronization mechanisms, it ensures that signals between multiple buses and distributed processing units remain strictly consistent in time and at the frame level, effectively avoiding synchronization errors and data loss and maintaining the integrity of the signal flow. Finally, based on instructions issued from the application layer or the real-time requirements of multi-bus and distributed system collaborative scheduling, the hardware selection module dynamically selects the signal source to be processed. This module supports parallel selection of multiple signals and millisecond-level fast switching, enhancing the system's flexibility and responsiveness. These preprocessing steps collectively lay a solid standardized foundation for subsequent multi-bus distributed processing, ensuring the efficiency and stability of the entire system when handling high loads and multi-source signals.

[0026] S2: The distributed processing unit performs differentiated and exclusive rendering operations on the standardized baseband signal according to the production task requirements of different buses in the multi-bus system.

[0027] In video production systems, the production tasks corresponding to different buses include at least two of the following: PGM (Program) broadcast tasks, PVW (Preview) pre-monitoring tasks, and MV (Multi-View) multi-screen monitoring tasks. Among these, the PGM broadcast task involves the generation and output of the final program signal, ensuring broadcast-quality; the PVW pre-monitoring task is used for real-time preview and signal debugging to ensure the accuracy of the production process; and the MV multi-screen monitoring task is responsible for simultaneously monitoring multiple video sources to facilitate directorial decisions. Differentiated, dedicated rendering operations cover scaling, overlaying, and special effects production. For example, scaling adjusts the screen ratio to adapt to different output formats, overlaying achieves the merging of subtitles, logos, or picture-in-picture, and special effects production includes visual enhancement processing such as transitions and filters. The distributed processing unit is based on multi-bus task division. According to the specific production task requirements of different buses (such as PGM, PVW, MV), it performs differentiated rendering processing on the pre-processed standardized baseband signal: according to the task logic of PGM broadcast, PVW pre-monitoring, and MV multi-screen monitoring, it completes core rendering operations such as signal scaling, overlay, and special effects production. Each distributed processing unit only undertakes the stage-specific specific task of the corresponding bus, without functional redundancy. Through multi-bus division of labor and distributed unit collaboration, parallel task processing and dynamic resource scheduling are realized, thereby effectively improving overall processing efficiency, reducing system latency, and enhancing the flexibility and reliability of the production process.

[0028] S3: Based on the logic of multi-bus isolation and distributed unit cascading, the rendered signal is distributed to the corresponding bus and passed to the next level of distributed processing unit; among them, it supports the synchronous distribution of the same signal source to multiple buses.

[0029] Specifically, the system first precisely distributes the rendered signals according to a preset bus task allocation strategy, thereby achieving strict physical isolation between different bus signals and preventing mutual interference during transmission. Then, the signals distributed to each independent bus are output sequentially to the next-level distributed processing unit as input signals, entering a pipelined, multi-stage, high-efficiency processing flow. After the rendering processing stage is completely finished, each distributed processing unit, through its built-in hardware distribution module, accurately and strictly distributes the generated rendering results to the corresponding target bus based on the dual design logic of "multi-bus isolation + distributed cascading," ensuring that the signal paths carried by different buses are completely independent, without intersection or crosstalk, achieving complete isolation between buses at the physical level. Simultaneously, these processed signals are further output to the next-level distributed processing unit as input signals for the next stage of the processing flow, continuing to be transmitted and processed in a pipelined manner, thus realizing cascading and collaboration between distributed processing units. The system also supports the synchronous distribution of the same signal source to multiple independent buses, achieving a highly efficient operation mode of "one input, multiple buses, and multiple tasks in parallel processing", giving full play to the significant advantages of the multi-bus distributed architecture in resource reuse, load balancing, and processing concurrency.

[0030] S4: In the last stage of distributed processing unit, the signals from each bus after cascading processing are combined and converted into the target format for independent output.

[0031] Specifically, the process first synthesizes the signals corresponding to the PGM broadcasting task, PVW pre-monitoring task, and MV multi-view monitoring task into their respective independent baseband streams, ensuring that the signals of each task are isolated and intact at the source. Subsequently, each baseband stream is independently converted into the corresponding format such as SDI, ST2110, or network stream according to the actual transmission and scheduling requirements, so as to adapt to the interface and protocol standards of different stages.

[0032] At the end of the multi-bus distributed architecture rendering link, the final distributed processing unit undertakes the key function of signal integration and delivery. This unit completes the final dedicated synthesis and standardized output of each bus signal through a dedicated hardware synthesis module: First, it aggregates the final rendering results of each bus after being processed by the multi-unit distributed processing in front, and generates independent bus streams that meet broadcast-grade standards according to the task; then, it converts each baseband signal into an interface format (such as SDI, ST2110, NVI, network stream, etc.) compatible with downstream production, broadcasting, or monitoring equipment, flexibly responding to the differentiated needs of different terminals and platforms; finally, it completes the independent hardware channel output and delivery of each bus signal (such as PGM, PVW, MV), serving specific scenarios such as formal broadcasting, pre-switching monitoring, and on-site monitoring, and through strict signal isolation and synchronization processing, it ensures that there is no mutual interference between the outputs of each bus, achieving high-quality and high-reliability parallel signal output.

[0033] Example 2: An embedded hardware rendering signal processing method, applied to a fusion switcher scenario, wherein: the multi-bus includes a PGM bus, a PVW bus and an MV bus; the distributed processing unit includes an R card, an M0 card and an M1 card cascaded in sequence; differentiated dedicated rendering operations, distribution and transmission are executed sequentially among the R card, M0 card and M1 card; the end-to-end latency of the method is less than or equal to 20ms.

[0034] The converged switcher scenarios include, but are not limited to, converged media studios and large-scale live broadcasts. Its signal processing method is an advanced solution designed for high-performance live broadcast environments, aiming to achieve efficient, stable, and low-latency broadcast control operations. This method is compatible with a specific hardware architecture: a multi-bus distributed embedded hardware architecture using R-cards, M0 cards, and M1 cards in a three-level cascade, performing signal processing based on the PGM, PVW, and MV buses. This ensures that the end-to-end latency does not exceed 20 milliseconds, thereby guaranteeing real-time response and signal synchronization, meeting the stringent requirements of large-scale event live broadcasts.

[0035] Signal standardization preprocessing stage: Multi-source heterogeneous signals, such as those from cameras, video recorders, or network streams, are first connected to a distributed R card to complete format unification and synchronous calibration, and intelligently select the signal source to be switched, providing standardized input for subsequent rendering and switching operations.

[0036] Bus-specific rendering stage: The R card performs multi-screen overlay on the MV bus to integrate multiple monitoring screens; at the same time, it handles basic M / E rendering on the PGM and PVW buses, implementing simple blending and transition effects, thereby clarifying the functional division of the three buses and improving processing efficiency.

[0037] Collaborative isolation distribution phase: The R card distributes the three bus signals to the M0 card through the isolation channel to achieve multi-bus distributed collaborative transmission, ensuring the independence and synchronization of signals during transmission and avoiding mutual interference.

[0038] Bus-dedicated rendering stage: After receiving the signal, the M0 card focuses on video decoding, signal optimization and enhancement. Through technologies such as noise reduction and color correction, it significantly improves the clarity of the MV monitoring screen and the accuracy of the PVW preview signal, providing operators with a reliable preview reference.

[0039] Collaborative isolation distribution phase: The M0 card continues to distribute the optimized signal to the M1 card to maintain the continuity of the signal flow and low-latency transmission in order to support subsequent high-level processing.

[0040] Bus-dedicated rendering stage: The M1 card undertakes core rendering tasks, completing high-level rendering such as DSK (downstream keying), internal / external key overlay, and switching effects (for PGM and PVW buses), while also handling global MV monitoring rendering to achieve complex image and text overlay and dynamic effects, thereby enhancing the visual expressiveness of the broadcast content.

[0041] Synthesis and delivery phase: The M1 card finally synthesizes and outputs the PGM broadcast signal for live streaming, the PVW pre-monitoring signal for the director to make real-time adjustments, and the MV monitoring signal to support multi-screen monitoring, completing the full-link processing from input to output, ensuring broadcast quality and operational flexibility.

[0042] This invention features a clearly defined three-bus architecture, with distributed units working collaboratively in a pipeline manner, achieving a processing latency of no more than 20 milliseconds. Signal channels can be expanded by adding R-cards, thereby meeting the needs of multi-camera live streaming.

[0043] Example 3: An embedded hardware rendering signal processing method, applied to slow-motion and highlight replay scenarios, wherein: the multi-bus includes a PGM0 bus and a PGM1 bus for dual-channel slow-motion production, as well as an MV bus; performing differentiated dedicated rendering operations on the standardized baseband signal includes: performing video file decoding and speed-up / slow-down rendering on the signals of the PGM0 bus and PGM1 bus according to the slow-motion production logic scheduled by the application layer.

[0044] This embodiment describes a signal processing method for slow-motion and highlight replay scenarios, specifically designed and adapted for a multi-bus distributed embedded hardware architecture based on a three-level cascaded R-card, M0-card, and M1-card system. This architecture relies on three independent buses—PGM0, PGM1, and MV—to realize signal flow and processing, supporting parallel slow-motion production across two channels. In terms of application-layer scheduling, the system configures tasks according to the business logic of slow-motion production, ensuring the real-time performance and stability of signal scheduling, rendering, and output processes, thereby fully leveraging the advantages of distributed hardware in parallel computing and resource isolation.

[0045] Signal standardization preprocessing: Multiple camera signals are first fed into a distributed R-card processing unit, where format unification, timing synchronization, and signal calibration are completed. The system then selects the live signal source and simultaneously records both high-bitrate and low-bitrate signals, providing the material basis for subsequent slow-motion processing.

[0046] Bus-specific rendering (R card level): The R card completes multi-screen overlay and basic graphics rendering according to the monitoring requirements of the MV bus; at the same time, the PGM0 and PGM1 buses determine whether to perform signal copying based on application layer instructions, thereby realizing a clear division of labor among the three buses in rendering tasks.

[0047] Collaborative isolation distribution (R card to M0 card): The R card distributes the rendering results of the MV bus and the copy signals of the PGM0 and PGM1 buses to the next-level M0 card through the corresponding bus paths. The three buses transmit in parallel to ensure isolation and synchronization between signals.

[0048] Bus-specific rendering (M0 card level): The M0 card performs dual-channel video file decoding and variable-speed rendering on the PGM0 / PGM1 bus to generate slow-motion effects; at the same time, it further optimizes and renders multi-screen monitoring images on the MV bus.

[0049] Collaborative isolation distribution (M0 card to M1 card): The M0 card continues to distribute the processed signal to the last-level M1 card via the corresponding bus, maintaining the three-level cascaded distributed processing flow.

[0050] Bus-specific rendering (M1 card level): The M1 card performs decoding of multi-screen audio and video files and high-level rendering of multi-screen fusion on the PGM0 / PGM1 bus, and completes the fine rendering of the final monitoring screen on the MV bus.

[0051] Synthesis and Output: The M1 card aggregates the processing results from each bus and outputs two slow-motion broadcast signals, PGM0 and PGM1, as well as the MV bus monitoring signal, completing the final output stage of the slow-motion production process.

[0052] This invention achieves low-latency, high-stability processing of slow-motion signals through task division among the PGM0, PGM1, and MV buses and collaborative processing by the R-card, M0 card, and M1 card three-level distributed units. The system boasts excellent scalability; signal access channels can be linearly expanded simply by adding R-cards. It fully leverages the combined advantages of the multi-bus distributed architecture in performance stacking, resource isolation, and parallel processing, making it suitable for video production scenarios with high real-time requirements, such as large-scale sporting events and variety shows.

[0053] Example 4: An embedded hardware rendering signal processing device, applied to a hardware architecture comprising physically isolated multiple buses and multiple cascaded distributed processing units, such as... Figure 2 As shown, the device includes a preprocessing module, a rendering module, a distribution and cascading module, and a compositing output module.

[0054] The system comprises the following modules: a preprocessing module for unifying and synchronizing the input heterogeneous signals of various types, selecting the signal source to be processed, and obtaining a standardized baseband signal; a rendering module for performing differentiated rendering operations on the standardized baseband signal by the distributed processing unit according to the production task requirements of different buses in the multi-bus system; a distribution and cascading module for distributing the rendered signal to the corresponding bus and passing it to the next-level distributed processing unit based on the logic of multi-bus isolation and distributed unit cascading; supporting the synchronous distribution of the same signal source to multiple buses; and a synthesis output module for synthesizing the signals from each bus after cascading processing in the final distributed processing unit and converting them into the target format for independent output.

[0055] Example 5: A computer terminal includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements an embedded hardware rendering signal processing method as described in Example 1.

[0056] Example 6: A computer-readable medium having a computer program stored thereon, the computer program being executed by a processor to implement an embedded hardware rendering signal processing method as described in Example 1.

[0057] Working Principle: This invention first performs standardized preprocessing on multi-source heterogeneous signals to eliminate format and timing differences, laying the foundation for distributed collaboration. Then, crucially, rendering tasks are assigned to specific buses (e.g., PGM broadcast, PVW pre-monitoring, MV monitoring), with each distributed processing unit handling only the phased tasks corresponding to its assigned bus, achieving parallel processing. Next, a distribution mechanism combining multi-bus isolation and distributed unit cascading ensures that signals from each bus flow do not interfere with each other and can be orderly transmitted to the next processing unit, supporting the synchronous distribution of a single signal source to multiple buses for resource sharing. Finally, the final unit completes the synthesis and format conversion of each bus signal for output. This invention, through task division, collaborative pipeline, and isolated transmission logic, transforms the multi-bus concurrency and distributed cascading potential of the hardware architecture into practical technical effects of low latency, high throughput, high resource utilization, and linear scalability.

[0058] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0059] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0060] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0061] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0062] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An embedded hardware rendering signal processing method, characterized in that, The method, applied to a hardware architecture comprising physically isolated multi-bus systems and multiple cascaded distributed processing units, includes: The input heterogeneous signals of various types are formatted and synchronously calibrated, and the signal source to be processed is selected to obtain a standardized baseband signal; The distributed processing unit performs differentiated, dedicated rendering operations on the standardized baseband signal according to the production task requirements corresponding to different buses in the multi-bus system. The rendered signal is distributed to the corresponding bus and passed to the next level of distributed processing unit based on the logic of multi-bus isolation and distributed unit cascading; among them, it supports the synchronous distribution of the same signal source to multiple buses. In the final distributed processing unit, the signals from each bus after cascading processing are combined and converted into the target format for independent output. The method is applied to a converged switcher scenario, wherein: The multi-bus includes PGM bus, PVW bus, and MV bus; The distributed processing unit includes R card, M0 card and M1 card cascaded in sequence; The differentiated dedicated rendering operations, distribution, and transmission are executed sequentially among the R card, M0 card, and M1 card; The method achieves an end-to-end latency of less than or equal to 20ms. Alternatively, the method can be applied to slow-motion and highlight replay scenarios, wherein: The multi-bus includes the PGM0 bus and PGM1 bus for dual-channel slow-motion production, as well as the MV bus; The differentiated rendering operation performed on the standardized baseband signal includes: performing video file decoding and speed-up / slow-motion rendering on the signals of the PGM0 bus and the PGM1 bus according to the slow-motion production logic scheduled by the application layer.

2. The embedded hardware rendering signal processing method according to claim 1, characterized in that, The process of unifying and synchronizing the input heterogeneous signals of various types includes: Hardware format conversion is performed on the aforementioned heterogeneous signals to obtain a baseband signal with a unified format; Clock recovery and frame-level synchronization calibration are performed on the baseband signal.

3. The embedded hardware rendering signal processing method according to claim 1, characterized in that, The production task requirements corresponding to the different buses include at least two of the following: PGM broadcasting task, PVW pre-monitoring task, and MV multi-screen monitoring task. The differentiated, proprietary rendering operations include scaling, overlaying, and special effects creation.

4. The embedded hardware rendering signal processing method according to claim 1, characterized in that, The logic based on multi-bus isolation and distributed unit cascading distributes data to the corresponding bus and passes it to the next-level distributed processing unit, including: The rendered signals are distributed according to bus tasks to achieve physical isolation between different bus signals; The signals distributed to each bus are output to the next level of distributed processing unit as input signals for pipelined processing.

5. The embedded hardware rendering signal processing method according to claim 1, characterized in that, In the final stage of distributed processing unit, the signals from each bus after cascaded processing are combined and converted into the target format for independent output. Specifically: The signals corresponding to the PGM broadcasting task, PVW pre-monitoring task, and MV multi-screen monitoring task are respectively synthesized into independent baseband streams; Each baseband stream is independently converted to SDI, ST2110, or network stream format for output.

6. An embedded hardware rendering signal processing device, characterized in that, The device is applied to a hardware architecture comprising physically isolated multi-bus systems and multiple cascaded distributed processing units, the device comprising: The preprocessing module is used to unify the format and synchronize the input heterogeneous signals of various types, and select the signal source to be processed to obtain a standardized baseband signal; The rendering module is used by the distributed processing unit to perform differentiated and dedicated rendering operations on the standardized baseband signal according to the production task requirements corresponding to different buses in the multi-bus system. The distribution and cascading module is used to distribute the rendered signal to the corresponding bus and pass it to the next level of distributed processing unit based on the logic of multi-bus isolation and distributed unit cascading; it supports the synchronous distribution of the same signal source to multiple buses. The synthesis output module is used in the last stage of distributed processing unit to synthesize the signals from each bus after cascading processing and convert them into the target format for independent output. The device is applied in a fusion switcher scenario, wherein: The multi-bus includes PGM bus, PVW bus, and MV bus; The distributed processing unit includes R card, M0 card and M1 card cascaded in sequence; The differentiated dedicated rendering operations, distribution, and transmission are executed sequentially among the R card, M0 card, and M1 card; The device achieves an end-to-end latency of less than or equal to 20ms. Alternatively, the device may be used in slow-motion and highlight replay scenarios, wherein: The multi-bus includes the PGM0 bus and PGM1 bus for dual-channel slow-motion production, as well as the MV bus; The differentiated rendering operation performed on the standardized baseband signal includes: performing video file decoding and speed-up / slow-motion rendering on the signals of the PGM0 bus and the PGM1 bus according to the slow-motion production logic scheduled by the application layer.

7. A computer terminal, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements an embedded hardware rendering signal processing method as described in any one of claims 1-5.

8. A computer-readable medium having a computer program stored thereon, characterized in that, The computer program, when executed by a processor, can implement an embedded hardware rendering signal processing method as described in any one of claims 1-5.

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