A semiconductor structure and a method of manufacturing the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, and particularly relates to the technical field of semiconductors. The manufacturing method of the semiconductor structure comprises the following steps: providing a semiconductor substrate, the substrate comprising a first metal layer; forming an interlayer dielectric layer on the semiconductor substrate, the interlayer dielectric layer covering the first metal layer; forming a metal trench and a via on the interlayer dielectric layer, wherein the via penetrates through the interlayer dielectric layer and exposes the first metal layer; forming a diffusion barrier layer on the inner wall of the via and the metal trench, the diffusion barrier layer comprising a TaN adhesion layer, a TaSiN barrier layer and a Ta sacrificial layer which are sequentially stacked; performing reverse sputtering treatment on the diffusion barrier layer by using a mixed gas of helium and argon; and filling a metal material into the via and the metal trench to form a metal interconnection structure electrically connected with the first metal layer. The application can realize directional inhibition of reverse sputtering etching and protection of weak areas, and improve the problem of tiger tooth defects.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] In back-end-of-line (BEOL) semiconductor manufacturing, copper interconnect technology, due to its low metal resistivity, is widely used in the metal wiring fabrication of advanced process chips. Currently, the dual damascene process is the mainstream copper interconnect process. Before electroplating copper to fill metal trenches and vias, this process typically requires the deposition of a barrier layer to prevent copper from diffusing into the interlayer dielectric (ILD), a critical process unit ensuring the electrical performance and long-term reliability of the copper interconnect structure.

[0003] However, during barrier layer deposition, resputtering can cause etching to the formed barrier layer and even the underlying interlayer metallic dielectric (IMD). Especially for trench structures with high aspect ratios, the geometry at the trench bottom disrupts the dynamic balance between resputtering and forward deposition in planar areas, resulting in a geometric amplification effect. The trench sidewalls can also affect high-energy Ar... + Ions act as guides, causing them to slide along the wall to the corner at the bottom of the trench, where they accumulate. Due to the geometric constraints at the bottom corner, the ions cannot be effectively scattered, and the energy is released in a concentrated manner, resulting in the over-etching of the barrier layer material at that location, forming sharp protrusions or depressions, which are commonly referred to in the industry as tiger tooth "V" type defects.

[0004] The sharp point of the "tiger tooth" defect can cause a local electric field concentration effect. Even under the normal operating voltage of the device, it may cause premature breakdown of the insulating dielectric layer and form a leakage channel between metal layers. At the same time, the tiger tooth defect can shorten the effective insulation distance between adjacent metal lines, significantly increase the interlayer parasitic capacitance, and thus increase the crosstalk noise between metal wirings. This may lead to problems such as abnormal coupling voltage and signal timing deviation, and in severe cases, even cause chip failure. In addition, the stress concentration at the tiger tooth tip can accelerate the electromigration effect, causing interface delamination or crack propagation, further weakening the long-term reliability of the copper interconnect structure and shortening the life of the device. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the present invention provides a semiconductor structure and its manufacturing method to improve the technical problem of metal tooth defects.

[0006] To achieve the above and other related objectives, the present invention provides a method for manufacturing a semiconductor structure, the method comprising the following steps:

[0007] A semiconductor substrate is provided, the semiconductor substrate including a first metal layer; An interlayer dielectric layer is formed on the semiconductor substrate, and the interlayer dielectric layer covers the first metal layer; Metal trenches and vias are formed on the interlayer dielectric layer, the vias penetrating the interlayer dielectric layer and exposing the first metal layer; A diffusion barrier layer is formed on the inner wall of the through hole and the inner wall of the metal trench. The diffusion barrier layer includes a TaN attachment layer, a TaSiN barrier layer and a Ta sacrificial layer stacked sequentially. The diffusion barrier layer is subjected to reverse sputtering treatment using a mixed gas of helium and argon, which transfers part of the Ta sacrificial layer formed on the bottom wall of the through hole and the metal trench to the side wall. Metal material is filled into the through holes and the metal trenches to form corresponding through holes and a second metal layer.

[0008] In one embodiment of the present invention, the step of forming a diffusion barrier layer on the inner wall of the through hole and the inner wall of the metal trench includes: Using magnetron sputtering of a pure Ta target, high-purity nitrogen and argon are simultaneously introduced into the reaction chamber to deposit a TaN deposit with a thickness of 30 Å to 40 Å on the inner wall of the through hole and the inner wall of the metal trench. A TaSiN barrier layer with a thickness of 50 Å to 60 Å was deposited on the TaN deposited layer by simultaneously introducing high-purity nitrogen and argon gas into the reaction chamber using a Ta and Si dual-target co-sputtering method. High-purity argon gas was introduced into the reaction chamber by magnetron sputtering of a pure Ta target, and a Ta sacrificial layer with a thickness of 20 Å to 30 Å was deposited on the TaSiN barrier layer.

[0009] In one embodiment of the present invention, the atomic concentration of Si element in the TaSiN barrier layer is 20 at% to 25 at%.

[0010] In one embodiment of the present invention, during the anti-sputtering process, the flow ratio of helium to argon is 1:1 to 1:3, and the anti-sputtering time is 5 to 7 seconds.

[0011] In one embodiment of the present invention, after the anti-sputtering treatment is completed, the method further includes: introducing high-purity argon gas into the reaction chamber by magnetron sputtering a pure Ta target, and depositing a Ta wetting layer with a thickness of 20 Å to 30 Å on the Ta sacrificial layer.

[0012] In one embodiment of the present invention, the step of filling the through hole and the metal trench with metal material includes: A seed crystal layer is formed on the surface of the diffusion barrier layer; A metallic material is formed on the surface of the seed crystal layer to fill the through holes and the metal trenches, thereby forming a via and a second metal layer.

[0013] In one embodiment of the present invention, the step of forming an interlayer dielectric layer on the semiconductor substrate includes: A nitrogen-doped silicon carbide layer is formed on the semiconductor substrate; A hydrogen-containing silicon oxide layer is formed on the nitrogen-doped silicon carbide layer; A tetraethyl orthosilicate layer is formed on the hydrogen-containing carbon oxide silicon layer.

[0014] The thickness of the nitrogen-doped silicon carbide layer is 380 Å to 420 Å, the thickness of the hydrogen-containing silicon oxide layer is 2610 Å to 2890 Å, and the thickness of the tetraethyl orthosilicate layer is 240 Å to 260 Å.

[0015] In one embodiment of the present invention, the step of forming metal trenches and vias on the interlayer dielectric layer includes: The patterns of the vias and the metal trenches are defined on the interlayer dielectric layer using photolithography and etching processes to form a template for a metal interconnect structure. The template for the metal interconnect structure includes a first trench corresponding to the metal trenches and a second trench corresponding to the vias. Based on the template of the metal interconnect structure, the interlayer dielectric layer is etched until the second trench communicates with the first metal layer, forming a metal trench and a through hole.

[0016] In one embodiment of the present invention, the step of defining the patterns of the vias and the metal trenches on the interlayer dielectric layer using photolithography and etching processes to form a template for a metal interconnect structure includes: A hard mask layer, an oxide layer, and a first anti-reflection layer are sequentially formed on the interlayer dielectric layer; A first patterned photoresist layer is formed on the first anti-reflective layer, and the first patterned photoresist layer has the pattern of the metal trenches. Using the first patterned photoresist layer as a template, the first anti-reflection layer, oxide layer and hard mask layer are etched sequentially to form the first trench; Remove the first patterned photoresist layer and the first anti-reflective layer; A second anti-reflective layer is formed on the oxide layer and within the first trench; A second patterned photoresist layer is formed on the second anti-reflective layer, and the second patterned photoresist layer has the pattern of the through hole; Using the second patterned photoresist layer as a template, the second antireflective layer, the oxide layer, the hard mask layer, and part of the interlayer dielectric layer are etched sequentially to form the second trench; Remove the second anti-reflective layer and the second patterned photoresist layer.

[0017] The present invention also provides a semiconductor structure manufactured using the manufacturing method described above. The semiconductor structure includes a semiconductor substrate, an interlayer dielectric layer, a diffusion barrier layer, a second metal layer, and vias. The semiconductor substrate includes a first metal layer. The interlayer dielectric layer is formed on the semiconductor substrate and covers the first metal layer. Metal trenches and vias are formed in the interlayer dielectric layer. The diffusion barrier layer is formed on the inner walls of the metal trenches and the inner walls of the vias. The diffusion barrier layer includes a TaN attachment layer, a TaSiN barrier layer, and a Ta sacrificial layer stacked sequentially. The second metal layer is formed within the metal trenches. The vias are formed within the vias and communicate with the first metal layer.

[0018] In summary, the semiconductor structure manufacturing method provided by this invention first forms vias and metal trenches in the interlayer dielectric layer above the first metal layer, then forms a multilayer barrier layer structure composed of TaN / TaSiN / Ta on the inner walls of the vias and metal trenches, and subsequently uses a light inert gas He. + with Ar + The mixed plasma is subjected to backsputtering treatment, and the bombardment intensity and scattering behavior are controlled by the difference in the mass of different ions, so as to achieve plasma scattering buffering.

[0019] An unexpected effect is that this invention, by employing a TaN / TaSiN / Ta multilayer barrier layer structure and combining it with He... + / Ar + Hybrid anti-sputtering process can achieve directional suppression of anti-sputtering etching and precise protection of weak areas. It solves the problems of anti-sputtering over-etching and "tiger tooth" defects in high aspect ratio structures from two dimensions: material structure and process conditions. It also has good compatibility with subsequent interconnect processes.

[0020] In this multilayer barrier structure, the bottom TaN layer exhibits strong adhesion to the low-k interlayer dielectric layer, resulting in stable interfacial bonding. The intermediate amorphous TaSiN layer, free of significant grain boundary defects, effectively blocks copper diffusion channels while possessing high density, high hardness, and excellent thermal stability. This significantly resists ion bombardment during backsputtering, enhancing the structure's resistance to over-etching. The surface Ta layer can be redeposited on the metal trenches and via sidewalls during backsputtering, facilitating the wetting and coverage of subsequent seed layers and improving step coverage. This multilayer structure directly reduces the etching of the bottom dielectric material during backsputtering, and its smooth interface with fewer defects helps reduce and stabilize interconnect resistance, ensuring reliable electrical signal transmission.

[0021] Using He + with Ar + By using a mixed inert gas for backsputtering, the bombardment energy and scattering behavior can be controlled by the difference in ion mass, thereby achieving buffering and homogenization of plasma bombardment and specifically enhancing the anti-backsputtering capability of the trench bottom. This invention can reduce the backsputtering etching amount at the trench bottom by more than 80% and reduce the incidence of serrated defects from 90% to below 10%.

[0022] The manufacturing method of this invention does not require increasing the total thickness of the barrier layer, does not affect the subsequent metal material filling process, and is based on the existing mainstream process framework. It does not require modification of the equipment structure and can be implemented by simply adjusting the target material and gas source. It has low cost, strong process compatibility, and can be flexibly applied to advanced processes of 40nm and below. It has outstanding protection effect and application advantages, especially for high aspect ratio interconnect structures. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0024] In the attached diagram: Figure 1 A schematic diagram illustrating the canine tooth defect created by existing processes; Figure 2 This is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a semiconductor substrate and an interlayer dielectric layer provided in one embodiment of the present invention; Figure 4 This is a schematic diagram of a structure in which a first patterned photoresist layer is formed on an interlayer dielectric layer according to an embodiment of the present invention. Figure 5 This is a schematic diagram of the structure for forming the first trench according to one embodiment of the present invention; Figure 6 This is a schematic diagram of a structure for removing the first patterned photoresist layer according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure for forming a second patterned photoresist layer according to one embodiment of the present invention; Figure 8 This is a schematic diagram of the structure for forming the second trench provided in one embodiment of the present invention; Figure 9This is a schematic diagram of a structure for removing the second patterned photoresist layer according to an embodiment of the present invention; Figure 10 This is a schematic diagram of a structure in which metal trenches and vias are formed in an interlayer dielectric layer according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure for forming a diffusion barrier layer provided in one embodiment of the present invention; Figure 12 for Figure 11 A partially enlarged schematic diagram of the diffusion barrier layer; Figure 13 This is a schematic diagram of the structure during anti-sputtering provided in one embodiment of the present invention; Figure 14 A partial structural schematic diagram of the formation of the Ta wetting layer is provided in one embodiment of the present invention; Figure 15 A schematic diagram of the structure during electrochemical copper plating provided in one embodiment of the present invention; Figure 16 A schematic diagram of the structure after chemical mechanical grinding provided in one embodiment of the present invention.

[0025] The attached figures are labeled as follows: 100, First metal layer; 101, First interlayer dielectric layer; 200, Second interlayer dielectric layer; 210, Nitrogen-doped silicon carbide layer; 220, Hydrogen-containing silicon oxide layer; 230, Tetraethyl orthosilicate layer; 300, Metal trench; 310, Hard mask layer; 320, Oxide layer; 330, First antireflective layer; 340, First patterned photoresist layer; 350, First trench; 400, Via; 410, Second antireflective layer; 420, Second patterned photoresist layer; 430, Second trench; 500, Diffusion barrier layer; 510, TaN adhesion layer; 520, TaSiN barrier layer; 530, Ta sacrificial layer; 540, Ta wetting layer; 600, Copper metal; 610, Second metal layer; 620, Via. Detailed Implementation

[0026] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0028] In this document, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0029] In this document, when referring to numerical ranges, unless otherwise specified, the distribution of selectable values ​​within a numerical range is considered continuous, including the two endpoints of the range (i.e., the minimum and maximum values), and every value between these two endpoints. When multiple numerical ranges are provided to describe a feature or property, these numerical ranges can be combined.

[0030] In semiconductor back-end dual damascene processes, PVD (Physical Vapor Deposition) is typically used to deposit a diffusion barrier layer on the inner wall of vias. The principle involves introducing a working gas into a vacuum chamber, ionizing it to form plasma, and then using high-energy ions to bombard the target material, causing target atoms to sputter out and ultimately form a film on the wafer substrate surface. However, during this process, some high-energy Ar atoms that are not fully confined by the magnetic field may... + Instead of bombarding the target material, it may bombard the newly deposited barrier layer on the substrate surface, forming a reverse sputtering that etches the barrier layer and the underlying material (such as IMD). Especially in high aspect ratio trench structures, the geometric amplification effect can cause ion accumulation at the bottom corners of the trench, resulting in excessive ion buildup and thus creating "tiger tooth" defects (such as...). Figure 1 (as shown in the circle).

[0031] To address the aforementioned defects, existing improvement methods mainly focus on fine-tuning PVD process parameters, increasing the thickness of the diffusion barrier layer, and adjusting the process method, as detailed below: (1) Process parameter adjustment: Reducing PVD sputtering power, increasing deposition gas pressure, and increasing Ar gas flow rate are the most commonly used parameter optimization methods to reduce backsputtering. The core logic is to reduce ion energy, reduce bombardment of the trench bottom, or increase ion collision frequency to weaken directional backsputtering, and disperse high-energy ions through gas flow disturbance. However, although reducing power, increasing gas pressure, and simply increasing Ar gas flow rate can reduce backsputtering, it will lead to a decrease in barrier layer deposition rate, reduced production capacity, poorer film density, increased film porosity, and increased Cu diffusion risk.

[0032] (2) Increase the total thickness of the barrier layer: By reserving the backsputtering allowance, the bottom material is avoided from being exposed. However, this will increase the difficulty of trench filling, which will easily cause voids in subsequent Cu electroplating, and still cannot completely solve the problem of local backsputtering concentration at the bottom of the trench.

[0033] (3) Tilting the substrate to adjust the ion incident angle: This is an attempt to make the ions act more evenly on the sidewalls and bottom of the trench. It requires complex fixtures and control systems, which makes it difficult to implement.

[0034] (4) Directly depositing TaSiN on the dielectric layer: Although the steps are simple, in actual processes, the chemical bond between TaSiN and the dielectric layer is weak, mainly relying on weak van der Waals forces, resulting in poor film adhesion and easy peeling.

[0035] (5) Fine-tuning the target-substrate distance and optimizing the static distribution of the magnetron magnetic field: The core logic is to extend the ion flight distance to reduce the energy when reaching the wafer and reduce the direct ion penetration to the bottom of the trench, which can improve film uniformity and reduce surface ion damage. However, this method will exacerbate the shadowing effect in high aspect ratio (40nm and below) structures in advanced processes, resulting in poor coverage of the steps at the bottom of the trench.

[0036] In summary, the existing improvement methods are all local adjustments to the existing PVD process, and do not fundamentally solve the contradiction between back sputtering and forward deposition, thus failing to effectively eliminate the "tiger tooth" defect.

[0037] Based on this, the present invention provides a semiconductor structure and its manufacturing method, which employs a TaN / TaSiN / Ta multilayer barrier layer structure and combines it with He + / Ar + The hybrid anti-sputtering process achieves directional suppression of anti-sputtering etching and precise protection of weak areas, solving the problems of anti-sputtering over-etching and "tiger tooth" defects in high aspect ratio structures from two dimensions: material structure and process conditions. It also has good compatibility with subsequent interconnect processes.

[0038] Please see Figure 2 The method for manufacturing a semiconductor structure according to the present invention includes the following steps: S1. A semiconductor substrate is provided, the semiconductor substrate including a first metal layer 100 (see...). Figure 3 ); S2. An interlayer dielectric layer is formed on a semiconductor substrate, the interlayer dielectric layer covering the first metal layer 100 (see...). Figure 3 ); S3. Form metal trenches 300 and vias 400 on the interlayer dielectric layer, wherein the vias 400 penetrate the interlayer dielectric layer and expose the first metal layer 100 (see...). Figure 10 ); S4. A diffusion barrier layer 500 is formed on the inner wall of the through-hole 400 and the inner wall of the metal trench 300. The diffusion barrier layer 500 includes a TaN attachment layer 510, a TaSiN barrier layer 520, and a Ta sacrificial layer 530 stacked sequentially (see...). Figure 11 and Figure 12 ); S5. A mixture of helium and argon is used to perform back-sputtering treatment on the diffusion barrier layer 500, causing part of the Ta sacrificial layer 530 formed on the bottom wall of the through-hole 400 and the metal trench 300 to be transferred to the sidewall (see...). Figure 13 ); S6. Fill the through hole 400 and the metal trench 300 with metal material to form the through hole 620 and the second metal layer 610 (see...). Figure 15 and Figure 16 ).

[0039] The following is combined with Figures 3 to 16 The steps in the manufacturing method of the semiconductor structure of the present invention are described in detail.

[0040] Please see Figure 3In step S1, the semiconductor substrate is a structure based on a substrate (not shown in the figure) after some device fabrication steps (such as deposition, etching, ion implantation, etc.) have been completed. The substrate can be a silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a germanium-silicon-on-insulator substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), etc. As an example, the substrate is a silicon substrate. The semiconductor substrate includes one or more electronic components formed on the substrate, which may include at least one of MOS (Metal-Oxide-Semiconductor) devices, sensor devices, memory devices, etc. The first metal layer 100 is a wiring layer formed on the substrate using a metal interconnect process. The first metal layer 100 can be the bottom wiring layer or a wiring layer above the bottom wiring layer. The first metal layer 100 can be connected to the electronic components on the substrate. A first interlayer dielectric layer 101 is provided around the first metal layer 100, meaning the first metal layer 100 is formed within the first interlayer dielectric layer 101, which serves as an isolation layer between the first metal layer 100 and its underlying structure. In some embodiments, the first interlayer dielectric layer 101 can be a single layer or multiple layers, and its material is selected from dielectric materials with low dielectric constant (low-k), including but not limited to one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, nitrogen-doped silicon carbide (NDC), hydrogen-containing silicon oxycarbonate (SiCOH), tetraethyl orthosilicate (TEOS), silicate glass (BPSG), and undoped silicate glass (USG). For example, the material of the first interlayer dielectric layer 101 is SiCOH.

[0041] Next, step S2 is performed to form an interlayer dielectric layer on the semiconductor substrate. To distinguish it from the first interlayer dielectric layer 101, this interlayer dielectric layer is designated as the second interlayer dielectric layer 200. The second interlayer dielectric layer 200 is used to create isolation between the first metal layer 100 and the wiring layer to be formed when a wiring layer is formed on the first metal layer 100. The material of the second interlayer dielectric layer 200 is a low-k dielectric material, which can be the same as or different from the material of the first interlayer dielectric layer 101. The second interlayer dielectric layer 200 can be a single layer or multiple layers, depending on the specific requirements.

[0042] In one embodiment, the second interlayer dielectric layer 200 includes, from bottom to top, a nitrogen-doped silicon carbide (NDC) layer 210, a hydrogen-containing silicon oxide (SiCOH or BD) layer 220, and a tetraethyl orthosilicate (TEOS) layer 230. The nitrogen-doped silicon carbide layer 210 serves as a dielectric barrier layer, preventing metal atom diffusion or mixing between different dielectric layers, while also providing structural stability. The hydrogen-containing silicon oxide layer 220 serves as an interlayer isolation dielectric, reducing parasitic capacitance between wirings through its low dielectric constant. The tetraethyl orthosilicate can be converted into silicon oxide (SiO2) as a low-k dielectric material for interlayer isolation. In this embodiment, the second interlayer dielectric layer 200 uses three layers of materials with different dielectric constants as isolation metal layers, which can reduce parasitic capacitance and lower RC delay. Furthermore, the thickness of the nitrogen-doped silicon carbide layer 210 is 380 Å to 420 Å, specifically 380 Å, 400 Å, or 420 Å, etc.; the thickness of the hydrogen-containing silicon oxide layer 220 is 2610 Å to 2890 Å, specifically 2610 Å, 2750 Å, or 2890 Å, etc.; and the thickness of the tetraethyl orthosilicate layer 230 is 240 Å to 260 Å, specifically 240 Å, 250 Å, or 260 Å, etc.

[0043] In this embodiment, step S2, forming an interlayer dielectric layer on the semiconductor substrate, specifically includes: first, forming a nitrogen-doped silicon carbide layer 210 of a predetermined thickness on the semiconductor substrate, the nitrogen-doped silicon carbide layer 210 covering the first interlayer dielectric layer 101 and the first metal layer 100; then, forming a hydrogen-containing silicon oxide layer 220 of a predetermined thickness on the nitrogen-doped silicon carbide layer 210; and then forming a tetraethyl orthosilicate layer 230 of a predetermined thickness on the hydrogen-containing silicon oxide layer 220. The formation of each of the above dielectric layers can be achieved using conventional processes in the art, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.

[0044] Please see Figures 3 to 10 Then, step S3 is performed to form a metal trench 300 and a via 400 on the interlayer dielectric layer. The metal trench 300 extends along the length direction in a plane parallel to the surface of the semiconductor substrate to form a wiring pattern of the second metal layer 610. The via 400 penetrates the second interlayer dielectric layer 200 in the longitudinal direction and exposes the top of the first metal layer 100. Subsequently, metal material is filled to connect the first metal layer 100 and the second metal layer 610.

[0045] In one embodiment, the metal trench 300 and the through hole 400 are formed using photolithography and etching processes, specifically including the following steps: Please see Figures 3 to 9The process involves using photolithography and etching to define patterns of vias 400 and metal trenches 300 on the interlayer dielectric layer, forming a template for the metal interconnect structure. Specifically, this includes sequentially forming a hard mask layer 310, an oxide layer 320, and a first anti-reflective layer (ARC) 330 on the second interlayer dielectric layer 200. (See [link to documentation]). Figure 3 and Figure 4 The hard mask layer 310, for example, is a titanium nitride hard mask layer with a thickness of 200 Å. It serves as a hard mask in the photolithography / etching process to achieve precise pattern transfer and prevent damage to the underlying dielectric material. The first anti-reflection layer 330 is used to improve the interference of the high reflectivity of the metal hard mask layer on the photolithography accuracy. The oxide layer 320 is disposed between the hard mask layer 310 and the first anti-reflection layer 330, which can block the direct contact between the metal hard mask layer and the anti-radiation material, prevent the interface chemical reaction between the two, and avoid damaging the anti-reflection performance of the first anti-reflection layer 330 and the surface characteristics of the hard mask layer 310. The oxide layer 320 is, for example, a silicon dioxide (SiO2) layer. The hard mask layer 310, the oxide layer 320, and the first anti-reflection layer (ARC) 330 can be formed using conventional processes in the art and are not limited here. Next, a first patterned photoresist layer 340 is formed on the first anti-reflection layer 330. This photoresist layer has a pattern of metal trenches 300, see [reference]. Figure 4 The first patterned photoresist layer 340 is formed as follows: First, a photoresist layer is spin-coated onto the first anti-reflection layer 330, and then, through exposure and development processes, a first patterned photoresist layer 340 with a metal trench 300 pattern is obtained. Then, using the first patterned photoresist layer 340 as a template, the first anti-reflection layer 330, the oxide layer 320, and the hard mask layer 310 are sequentially etched to form the first trench 350. See [link to documentation]. Figure 5 The first trench 350 is the initial trench of the metal trench 300, realizing the transfer of the metal trench 300 pattern to the hard mask layer 310. The etching process can employ dry etching, wet etching, or a combination of both; no limitation is made here. Then, the first patterned photoresist layer 340 and the first anti-reflective layer 330 are removed, see [link to relevant documentation]. Figure 6 The removal method can employ conventional methods in the art, such as ashing or peeling. Then, a second anti-reflective layer 410 is formed on the oxide layer 320 and inside the first trench 350, and a second patterned photoresist layer 420 is formed on the second anti-reflective layer 410. This photoresist layer has a pattern of through-holes 400. (See attached image.) Figure 7The second anti-reflective layer 410 uses a conventional anti-reflective material, which can be the same as or different from the first anti-reflective layer 330; no restriction is placed here. The second anti-reflective layer 410 fills the first trench 350 to prevent subsequent etching processes from affecting its morphology. The formation method of the second patterned photoresist layer 420 is the same as that of the first patterned photoresist layer 340, i.e., first spin-coating a photoresist layer, then forming it through exposure and development processes. Then, using the second patterned photoresist layer 420 as a template, the second anti-reflective layer 410, oxide layer 320, hard mask layer 310, and part of the second interlayer dielectric layer 200 are etched sequentially to form the second trench 430. See [link to documentation]. Figure 8 The second trench 430 serves as the initial via 400, enabling the transfer of the via 400 pattern to the second interlayer dielectric layer 200. Etching methods can include dry etching, wet etching, or a combination of both. The etching depth of the second interlayer dielectric layer 200 is set according to actual production requirements, ensuring that its remaining thickness matches the etching depth of the metal trench 300 to guarantee that the subsequent metal trench 300 and via 400 can be etched and formed synchronously. Finally, the second anti-reflective layer 410, the second patterned photoresist layer 420, and the oxide layer 320 are removed. See [link to documentation]. Figure 9 The removal can be done using conventional methods such as ashing or peeling. After this step is completed, the patterns of the metal trenches 300 and vias 400 have been successfully transferred to the second interlayer dielectric layer 200, thus obtaining the template for the metal interconnect structure.

[0046] Please see Figure 9 and Figure 10 Then, based on the template of the metal interconnect structure, the second interlayer dielectric layer 200 is etched until the second trench 430 is connected to the first metal layer 100. In this step, only the locations of the first trench 350 and the second trench 430 are exposed, while the remaining areas are shielded and protected by the hard mask layer 310. Therefore, the etching process only occurs at the above two trench locations. After etching, the first trench 350 forms a metal trench 300, and the second trench 430 forms a via 400.

[0047] Please see Figure 11 Next, step S4 is performed to form a diffusion barrier layer 500 on the inner wall of the through hole 400 and the inner wall of the metal trench 300. This diffusion barrier layer 500 is used to prevent the metal material subsequently filled in the through hole 400 and the metal trench 300 from diffusing laterally, that is, to prevent electromigration.

[0048] Please see Figure 11 and Figure 12The diffusion barrier layer 500 in this application includes a TaN attachment layer 510, a TaSiN barrier layer 520, and a Ta sacrificial layer 530 stacked sequentially from bottom to top. The strong adhesion between the bottom TaN attachment layer 510 and the low-k second interlayer dielectric layer 200 maintains the stability of the bonding interface. The middle TaSiN barrier layer 520 is amorphous. Amorphous TaSiN has no obvious grain boundary defects, which can block metal diffusion channels. It also has high density, high hardness, and excellent thermal stability, significantly resisting ion bombardment during subsequent backsputtering and improving the structure's resistance to over-etching. The surface Ta layer can be redeposited on the sidewalls of the metal trench 300 and via 400 during backsputtering, which is beneficial for the wetting and coverage of subsequent seed layers and improves step coverage. The multilayer diffusion barrier layer 500 of this application can directly reduce the etching of the bottom dielectric material by backsputtering, and the interface is flat with few defects, which helps to reduce and stabilize interconnect resistance and ensure the reliability of electrical signal transmission.

[0049] In some embodiments, the thickness of the TaN attachment layer 510 is 30 Å to 40 Å, exemplarily 30 Å, 35 Å, or 40 Å; the TaSiN barrier layer 520, as the main barrier layer, has a relatively large thickness of 50 Å to 60 Å, exemplarily 50 Å, 55 Å, or 60 Å; furthermore, the atomic concentration of Si element in the TaSiN barrier layer 520 is 20 at% to 25 at%, specifically 20 at%, 22 at%, or 25 at%, etc.; the Ta sacrificial layer 530 is mainly used to consume the etching amount in the subsequent anti-sputtering process, and its thickness is 20 Å to 30 Å, exemplarily 20 Å, 25 Å, or 30 Å. The above thickness range can achieve a good metal diffusion blocking effect while avoiding adverse effects on subsequent metal filling processes.

[0050] In one embodiment, the diffusion barrier layer 500 is prepared using a magnetron sputtering process, with the following specific steps: First, high-purity nitrogen (N2) and high-purity argon (Ar) are simultaneously introduced into the reaction chamber using magnetron sputtering of a pure Ta target, depositing a TaN adhesion layer 510 of a predetermined thickness on the inner wall of the through-hole 400 and the inner wall of the metal trench 300. High-purity nitrogen is used as the reactant gas, and high-purity argon is used as the working gas. A bias voltage is applied between the Ta target and the substrate, causing the gases to ionize and form a layer containing Ar. + Plasma containing electrons and neutral particles, accelerated by an electric field. + Moving towards a negatively charged Ta target, high-energy Ar + When the Ta target surface is bombarded, the Ta atoms are freed from the lattice bondage through momentum transfer (i.e. sputtering). The sputtered Ta atoms move toward the substrate and collide with the reactive gas N2 molecules to generate TaN atomic clusters, which finally land on the inner walls of the through hole 400 and the metal trench 300 and form a film through surface diffusion.

[0051] Subsequently, using a Ta / Si dual-target co-sputtering method, high-purity nitrogen and high-purity argon are simultaneously introduced into the reaction chamber to deposit a TaSiN barrier layer 520 of a predetermined thickness on the TaN deposited layer 510. In this step, high-purity nitrogen and high-purity argon serve as the reactant and working gases, respectively. Si atoms play a dual role in the barrier layer: on the one hand, they act as impurities, blocking the Ta-N grain boundaries and promoting their amorphization; on the other hand, the SiN formed by the reaction of Si and N2 is itself amorphous.

[0052] Finally, high-purity argon gas was introduced into the reaction chamber using magnetron sputtering of a pure Ta target to deposit a Ta sacrificial layer 530 of a predetermined thickness on the TaSiN barrier layer 520. High-purity Ar was used as the working gas, and its ionization formed Ar. + Under the influence of an electric field, it accelerates towards a negatively charged Ta target, high-energy Ar + When the surface of a Ta target is bombarded, the Ta atoms are released from their lattice constraints and move toward the substrate through momentum transfer, forming a Ta layer.

[0053] Please see Figure 13 In step S5, a mixture of helium (He) and argon (Ar) is used to perform back-sputtering treatment on the diffusion barrier layer 500, causing a portion of the Ta sacrificial layer 530 formed on the bottom wall of the through-hole 400 and the metal trench 300 to be transferred to the sidewall. Figure 13 The middle arrow indicates the direction of plasma bombardment.

[0054] Backsputtering refers to the process of using ion bombardment of the bottom walls of the vias 400 and metal trenches 300 to transfer the material originally deposited on the bottom walls of the vias 400 and metal trenches 300 to the sidewalls by setting appropriate PVD process conditions. In this application, through the backsputtering process, part of the Ta sacrificial layer 530 formed on the bottom wall can be transferred to the sidewall, thereby improving the coverage and thickness of the Ta layer on the sidewall.

[0055] The applicant discovered in their research that traditional PVD processes use Ar... + (Atomic weight 40) as a sputtering ion, its high-energy direct-sputtering characteristics easily lead to directional backsputtering damage at the bottom of the trench. Therefore, this application introduces a light inert gas, He. + (Atomic weight 4) and Ar + By using a combination of two types of ions, the mass difference between them can be leveraged to modulate the ion bombardment intensity and scattering behavior, thereby synergistically reducing the directional etching effect of backsputtering from its source. Among them, Ar... + It can ensure stable sputtering efficiency; while He + Atomic weight much smaller than Ar + It has a longer path of freedom and a higher collision probability within the cavity, and is compatible with high-energy Ar. +After frequent collisions, Ar can + The direct trajectory of the backsplash is transformed into a scattered trajectory, effectively reducing the directional bombardment damage to both sides of the trench bottom. Ta and TaN atoms or molecules that detach from the bottom wall after bombardment will sputter at a certain angle and redeposit on the sidewalls, achieving good wetting with the subsequently deposited seed layer. Furthermore, this application uses a ternary amorphous TaSiN structure as the main barrier layer. This material possesses high hardness, high density, and excellent thermal stability, effectively resisting ion bombardment during backsplashing and further enhancing the barrier layer's resistance to metal diffusion.

[0056] In some embodiments, during the backsputtering process, the He and Ar mixed gas has a He to Ar flow rate ratio of 1:1 to 1:3, which can be 1:1 / 1:2 or 1:3, etc., for example; and the backsputtering time is 5 to 7 seconds, which can be 5 seconds, 6 seconds or 7 seconds, etc., for example.

[0057] Please see Figure 14 In one embodiment, after the reverse sputtering process, a pure Ta target is sputtered using magnetron sputtering. High-purity Ar is introduced into the reaction chamber as the working gas, thereby depositing a Ta wetting layer 540 with a thickness of 20 Å to 30 Å to repair the damage to the Ta sacrificial layer 530 generated during the reverse sputtering process. Simultaneously, by optimizing the thickness of this wetting layer, good wettability with subsequent metal materials is ensured. Specifically, the thickness of the Ta wetting layer 540 can be selected from 20 Å, 25 Å, or 30 Å, etc.

[0058] Please see Figure 15 and Figure 16 The figure only shows the diffusion barrier layer 500 as an example; for the specific structure of the diffusion barrier layer 500, please refer to [link / reference]. Figure 14 Step S6 is performed to fill the through-hole 400 and the metal trench 300 with metal material to form a metal interconnect structure electrically connected to the first metal layer 100.

[0059] The metal material used in this step can be a material with low resistivity, good electromigration resistance and process compatibility, such as at least one of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co) and ruthenium (Ru). For example, the metal material is copper (Cu).

[0060] In one embodiment, the step of filling the via 400 and the metal trench 300 with metal material is as follows: First, a seed crystal layer is formed on the surface of the diffusion barrier layer 500. The core function of the seed crystal layer is to provide a continuous and uniform conductive path, provide nucleation sites for the subsequent deposition of metal material, ensure uniform growth of metal grains during the filling process, avoid filling defects such as voids and gaps, and at the same time improve the interfacial adhesion between the metal material and the diffusion barrier layer 500 to prevent interlayer peeling during subsequent use.

[0061] The seed layer is made of a material with excellent conductivity and good compatibility with the diffusion barrier layer 500 and the subsequent filler metal, such as at least one of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), and ruthenium (Ru). The seed layer can be the same as or different from the subsequently filler metal. Preferably, the seed layer is made of the same material as the subsequently filler metal to minimize interfacial contact resistance, ensure excellent interfacial bonding and conductivity, and reduce the impact of interfacial defects on device performance. For example, if the metal is copper, a copper seed layer is selected. Furthermore, the thickness of the seed layer is 500 Å to 600 Å, specifically 500 Å, 550 Å, or 600 Å, etc. If the seed layer thickness is insufficient, it is difficult to form a complete and continuous conductive film on the surface of the diffusion barrier layer 500, which can easily lead to problems such as film breaks and pinholes. This can result in defects such as localized copper-free areas and uneven filling when the metal material is filled in later. If the thickness is too large, it will significantly reduce the effective filling space of the via 400 and the metal trench 300. Especially for structures with a high aspect ratio, it can easily lead to the metal material not being able to completely fill the trench and via, forming void defects and affecting the reliability of interconnection.

[0062] The seed layer can be formed using conventional processes in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). In one specific embodiment, a 500-600 Å Cu seed layer is deposited by using magnetron sputtering on a pure Cu target and introducing high-purity Ar as the working gas. This seed layer has a crystal structure that is completely consistent with the crystal structure of the subsequent copper electroplating, which can effectively ensure the uniform nucleation and growth of the subsequent copper electroplating.

[0063] Subsequently, a metallic material is formed on the surface of the seed layer to completely fill the vias 400 and metal trenches 300, forming vias 620 and a second metal layer 610. The vias 620 are used for interlayer conduction, and the second metal layer 610 is used for signal transmission. In one embodiment, an electrochemical electroplating (ECP) process is used to deposit copper 600 on the surface of the seed layer until the vias 400 and metal trenches 300 are completely filled. Since there are no obstructions on the hard mask layer 310, the copper 600 is deposited on the surface of the hard mask layer 310 while filling the vias 400 and metal trenches 300. Therefore, after the ECP process, a chemical mechanical polishing (CMP) process is required to remove excess copper 600 from the surface of the hard mask layer 310 until the surface of the hard mask layer 310 is exposed, ensuring no copper residue remains. This completes the entire fabrication process of the downstream metal interconnect layer.

[0064] In other embodiments, the hard mask layer 310 is also removed, for example by etching.

[0065] Please see Figure 12 and Figure 16 The present invention also provides a semiconductor structure manufactured using the above-described manufacturing method. The semiconductor structure includes a semiconductor substrate, an interlayer dielectric layer, a diffusion barrier layer 500, a second metal layer 610, and a via 620.

[0066] The semiconductor substrate includes one or more electronic components and a first metal layer 100 formed on the substrate. The electronic components may include at least one of a MOS (Metal-Oxide-Semiconductor) device, a sensor, a memory device, etc. The first metal layer 100 is a wiring layer formed on the substrate using a metal interconnect process. The first metal layer 100 may be the bottom wiring layer or a wiring layer above the bottom wiring layer. The first metal layer 100 can be connected to the electronic components on the substrate. A first interlayer dielectric layer 101 is provided around the first metal layer 100, which can serve as an isolation layer between the first metal layer 100 and its underlying structure and / or co-layer structure.

[0067] An interlayer dielectric layer is formed on a semiconductor substrate and covers the first metal layer 100. To distinguish it from the first interlayer dielectric layer 101, the interlayer dielectric layer is referred to here as the second interlayer dielectric layer 200. The second interlayer dielectric layer 200 includes a nitrogen-doped silicon carbide layer 210, a hydrogen-containing silicon oxide layer 220, and a tetraethyl orthosilicate layer 230, which are arranged sequentially from bottom to top. The thickness of the nitrogen-doped silicon carbide layer 210 is 380 Å to 420 Å, specifically 380 Å, 400 Å, or 420 Å, etc.; the thickness of the hydrogen-containing silicon oxide layer 220 is 2610 Å to 2890 Å, specifically 2610 Å, 2750 Å, or 2890 Å, etc.; and the thickness of the tetraethyl orthosilicate layer 230 is 240 Å to 260 Å, specifically 240 Å, 250 Å, or 260 Å, etc.

[0068] The second metal layer 610 and the via 620 are formed in the metal trench 300 and via 400 within the second interlayer dielectric layer 200, respectively. The diffusion barrier layer 500 is formed on the inner wall of the metal trench 300 and via 400, and includes a TaN attachment layer 510, a TaSiN barrier layer 520 and a Ta sacrificial layer 530 stacked sequentially from bottom to top. The strong adhesion between the bottom TaN attachment layer 510 and the low-k second interlayer dielectric layer 200 maintains the stability of the bonding interface. The middle TaSiN barrier layer 520 is amorphous. Amorphous TaSiN has no obvious grain boundary defects, which can block the metal diffusion channel. It also has high density, high hardness and excellent thermal stability, which can significantly resist ion bombardment in the subsequent back sputtering process and improve the structure's resistance to over-etching. The surface Ta layer can be redeposited on the sidewalls of the metal trench 300 and via 400 during the back sputtering process, which is beneficial to the wetting and coverage of the subsequent seed layer and improves the step coverage effect. The multi-layer diffusion barrier layer 500 of this application can directly reduce the etching of the underlying dielectric material by anti-sputtering, and the interface is flat with few defects, which helps to reduce and stabilize the interconnect resistance and ensure the reliability of electrical signal transmission.

[0069] The semiconductor structure manufacturing method provided by this invention employs a TaN / TaSiN / Ta multilayer barrier layer structure combined with He + / Ar + The hybrid anti-sputtering process enables directional suppression of anti-sputtering etching and precise protection of weak areas, addressing the issues of over-sputtering and "tiger tooth" defects in high aspect ratio structures from both material structure and process conditions perspectives. It also exhibits good compatibility with subsequent interconnect processes. This manufacturing method does not require increasing the total thickness of the barrier layer, does not affect subsequent metal material filling processes, and is implemented based on existing mainstream process frameworks. It requires no modification to the equipment structure; implementation is achieved simply by adjusting the target material and gas source. It is low-cost, highly compatible, and flexibly applicable to advanced processes at 40nm and below, offering particularly outstanding protection and application advantages for high aspect ratio interconnect structures. This invention effectively overcomes some practical problems in existing technologies, thus possessing high utilization value and practical significance.

[0070] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: A semiconductor substrate is provided, the semiconductor substrate including a first metal layer; An interlayer dielectric layer is formed on the semiconductor substrate, and the interlayer dielectric layer covers the first metal layer; Metal trenches and vias are formed on the interlayer dielectric layer, the vias penetrating the interlayer dielectric layer and exposing the first metal layer; A diffusion barrier layer is formed on the inner wall of the through-hole and the inner wall of the metal trench using a magnetron sputtering process. The diffusion barrier layer comprises a TaN attachment layer, a TaSiN barrier layer, and a Ta sacrificial layer stacked sequentially. The atomic concentration of Si in the TaSiN barrier layer is 20 at%~25 at%. The diffusion barrier layer is subjected to backsputtering treatment using a mixture of helium and argon gas, which transfers part of the Ta sacrificial layer formed on the bottom wall of the through hole and the metal trench to the side wall. The flow rate ratio of helium to argon is 1:1 to 1:3, and the backsputtering time is 5 to 7 seconds. After the anti-sputtering process is completed, the method further includes: depositing a Ta wetting layer on the Ta sacrificial layer; Metal material is filled into the through holes and the metal trenches to form corresponding through holes and a second metal layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of forming a diffusion barrier layer on the inner wall of the through hole and the inner wall of the metal trench includes: Using magnetron sputtering of a pure Ta target, high-purity nitrogen and argon are simultaneously introduced into the reaction chamber to deposit a TaN deposit with a thickness of 30 Å to 40 Å on the inner wall of the through hole and the inner wall of the metal trench. A TaSiN barrier layer with a thickness of 50 Å to 60 Å was deposited on the TaN deposited layer by simultaneously introducing high-purity nitrogen and argon gas into the reaction chamber using a Ta and Si dual-target co-sputtering method. High-purity argon gas was introduced into the reaction chamber by magnetron sputtering of a pure Ta target, and a Ta sacrificial layer with a thickness of 20 Å to 30 Å was deposited on the TaSiN barrier layer.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of depositing a Ta wetting layer on the Ta sacrificial layer includes: introducing high-purity argon gas into the reaction chamber by magnetron sputtering a pure Ta target, and depositing a Ta wetting layer with a thickness of 20 Å to 30 Å on the Ta sacrificial layer.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of filling the through hole and the metal trench with metal material includes: A seed crystal layer is formed on the surface of the diffusion barrier layer; A metallic material is formed on the surface of the seed crystal layer to fill the through holes and the metal trenches, thereby forming a via and a second metal layer.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of forming an interlayer dielectric layer on the semiconductor substrate includes: A nitrogen-doped silicon carbide layer is formed on the semiconductor substrate; A hydrogen-containing silicon oxide layer is formed on the nitrogen-doped silicon carbide layer; A tetraethyl orthosilicate layer is formed on the hydrogen-containing carbon oxide layer; The thickness of the nitrogen-doped silicon carbide layer is 380 Å to 420 Å, the thickness of the hydrogen-containing silicon oxide layer is 2610 Å to 2890 Å, and the thickness of the tetraethyl orthosilicate layer is 240 Å to 260 Å.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of forming metal trenches and vias on the interlayer dielectric layer includes: The patterns of the vias and the metal trenches are defined on the interlayer dielectric layer using photolithography and etching processes to form a template for a metal interconnect structure. The template for the metal interconnect structure includes a first trench corresponding to the metal trenches and a second trench corresponding to the vias. Based on the template of the metal interconnect structure, the interlayer dielectric layer is etched until the second trench communicates with the first metal layer, forming a metal trench and a through hole.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, The step of defining the patterns of the vias and metal trenches on the interlayer dielectric layer using photolithography and etching processes to form a template for a metal interconnect structure includes: A hard mask layer, an oxide layer, and a first anti-reflection layer are sequentially formed on the interlayer dielectric layer; A first patterned photoresist layer is formed on the first anti-reflective layer, and the first patterned photoresist layer has the pattern of the metal trenches. Using the first patterned photoresist layer as a template, the first anti-reflection layer, oxide layer and hard mask layer are etched sequentially to form the first trench; Remove the first patterned photoresist layer and the first anti-reflective layer; A second anti-reflective layer is formed on the oxide layer and within the first trench; A second patterned photoresist layer is formed on the second anti-reflective layer, and the second patterned photoresist layer has the pattern of the through hole; Using the second patterned photoresist layer as a template, the second antireflective layer, the oxide layer, the hard mask layer, and part of the interlayer dielectric layer are etched sequentially to form the second trench; Remove the second anti-reflective layer and the second patterned photoresist layer.

8. A semiconductor structure, characterized in that, The semiconductor structure is manufactured using any one of the manufacturing methods described in claims 1 to 7; the semiconductor structure comprises: A semiconductor substrate, comprising a first metal layer; An interlayer dielectric layer is formed on the semiconductor substrate and covers the first metal layer; metal trenches and vias are formed in the interlayer dielectric layer; A diffusion barrier layer is formed on the inner wall of the metal trench and the inner wall of the through hole. The diffusion barrier layer includes a TaN attachment layer, a TaSiN barrier layer and a Ta sacrificial layer stacked sequentially. A second metal layer is formed within the metal trench; A via is formed within the via and communicates with the first metal layer.

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