Chip carrier, method of manufacturing the same, and chip package structure

Abstract

This invention provides a chip carrier board, its fabrication method, and a chip packaging structure. The fabrication method of the chip carrier board includes: forming conductive holes in a core layer; the conductive holes, in a direction perpendicular to the plane of the core layer, include a first filling region, a second filling region, and a third filling region connected sequentially; forming a liquid column in the conductive holes, the liquid column filling the second filling region; reducing the liquid column using a laser process to form a first sub-part, the first sub-part located in the second filling region of the conductive holes; forming second sub-parts at both ends of the first sub-part, the second sub-parts filling the first and third filling regions of the conductive holes, and the two ends of the first sub-parts connecting to the corresponding second sub-parts to form conductive pillars. This invention reduces the fabrication difficulty of the conductive pillars by fabricating them in stages, thereby improving the structural strength and electrical performance of the conductive pillars and increasing the production yield of the chip carrier board.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a chip carrier, its preparation method, and a chip packaging structure. Background Technology

[0002] A chip, also known as a microcircuit, microchip, or integrated circuit, is actually a general term for semiconductor electronic components. Chips can be classified in many ways; based on their signal processing capabilities, they can be divided into analog chips and digital chips. To protect the chip, it needs to be packaged, forming a chip package structure.

[0003] However, the performance of chip packaging structures made using existing technologies is poor. Summary of the Invention

[0004] The purpose of this invention is to provide a chip carrier board and its preparation method, as well as a chip packaging structure, to solve the problem of poor performance of chip packaging structures in related technologies.

[0005] To achieve the above objectives, the present invention provides a method for fabricating a chip carrier, comprising: forming a conductive hole in a core layer, wherein the conductive hole includes a first filling region, a second filling region, and a third filling region connected sequentially in a direction perpendicular to the plane of the core layer; forming a liquid column in the conductive hole, wherein the liquid column fills the second filling region; reducing the liquid column by a laser process to form a first sub-part, wherein the first sub-part is located in the second filling region of the conductive hole; forming a second sub-part at both ends of the first sub-part, wherein the second sub-part fills the first filling region and the third filling region of the conductive hole, and wherein both ends of the first sub-part are connected to the corresponding second sub-part to form a conductive pillar.

[0006] Further, the step of forming a liquid column in the conductive hole includes: spraying ink into the conductive hole to form the liquid column, the ink comprising a metal oxide, the liquid column filling the second filling area, and the liquid column extending at both ends into the first filling area and the third filling area respectively in a direction perpendicular to the plane of the core layer. Preferably, in the direction perpendicular to the plane of the core layer, the length of the liquid column is less than or equal to the depth of the conductive hole. Preferably, in the direction perpendicular to the plane of the core layer, the length of the liquid column is 30%-50% of the depth of the conductive hole.

[0007] Further, after the step of spraying ink into the conductive hole to form the liquid column, the method further includes: heating the core layer to evaporate a portion of the liquid phase in the liquid column; in a direction perpendicular to the plane of the core layer, the length of the liquid column after the heating step is less than the length of the liquid column before the heating step. Preferably, the core layer includes a first surface and a second surface disposed opposite to each other, the extension direction of the conductive hole is perpendicular to the first surface and the second surface, and after the heating step, the distance between the end of the liquid column near the first surface and the first surface is 10 micrometers-20 micrometers, and the distance between the end of the liquid column near the second surface and the second surface is 10 micrometers-20 micrometers.

[0008] Furthermore, the ink also includes a solvent, and the solid content of the ink is 10wt%-12wt%. Preferably, the solvent includes at least one of ethylene glycol and water.

[0009] Furthermore, the ink also includes a dispersant, and the content of the metal oxide in the ink is less than the content of the dispersant. Preferably, the particle size of the metal oxide is 20 nm to 40 nm. Preferably, the molecular weight of the dispersant is 35 kg / mol to 45 kg / mol. Preferably, the dispersant includes polyvinylpyrrolidone.

[0010] Further, in the step of reducing the liquid column to form the first sub-part using a laser process, the laser wavelength used is 10 nm to 560 nm. Preferably, in the step of reducing the liquid column to form the first sub-part using a laser process, the pulse width of the laser used is at least one of picosecond or femtosecond. Preferably, in the step of forming the second sub-part at both ends of the first sub-part, the second sub-part is formed in the conductive hole by an electroplating process.

[0011] Furthermore, before the step of forming a liquid column in the conductive hole, the method further includes: forming a seed layer on the surface of the core layer. Preferably, before the step of forming a seed layer on the surface of the core layer, the method further includes: forming a barrier layer on the surface of the core layer.

[0012] The present invention also provides a chip carrier, which is prepared by the chip carrier preparation method described above, and the chip carrier comprises:

[0013] A core layer, wherein conductive holes are provided in the core layer;

[0014] A conductive post is disposed in the conductive hole, and the conductive post includes a first sub-part and at least two second sub-parts, the at least two second sub-parts being located at both ends of the first sub-part in a direction perpendicular to the plane of the core layer.

[0015] Furthermore, in a direction parallel to the plane of the core layer, the width of the first sub-part is less than or equal to the width of the second sub-part. Preferably, in a direction parallel to the plane of the core layer, the width of the second sub-part on the side away from the first sub-part is less than the width of the second sub-part on the side closer to the first sub-part.

[0016] The present invention also provides a chip packaging structure, which includes the chip carrier board as described above.

[0017] The advantages of this invention are: the chip carrier and its preparation method of this invention prepare conductive pillars in stages to reduce the difficulty of preparing conductive pillars, achieve void-free filling of conductive pillars, thereby improving the structural strength and electrical performance of conductive pillars, and improving the production yield of chip carrier. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the layered structure of a chip carrier board according to one embodiment of the present invention;

[0020] Figure 2 This is an enlarged schematic diagram of the core layer structure in one embodiment of the present invention;

[0021] Figure 3 This is an enlarged schematic diagram of the core layer structure in one embodiment of the present invention;

[0022] Figure 4 This is an enlarged schematic diagram of the core layer structure in one embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the layered structure of the chip packaging structure in some embodiments of the present invention;

[0024] Figure 6 This is a schematic flowchart of a chip carrier preparation method according to one embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of a layered structure forming a conductive hole according to one embodiment of the present invention;

[0026] Figure 8 This is a schematic diagram of a layered structure forming a barrier layer and a seed layer in one embodiment of the present invention;

[0027] Figure 9 This is a schematic diagram of a layered structure forming a liquid column according to one embodiment of the present invention;

[0028] Figure 10 This is a schematic diagram of the layered structure after the liquid column evaporates a portion of the liquid phase in one embodiment of the present invention;

[0029] Figure 11 This is a schematic diagram of the layered structure forming the first sub-part in one embodiment of the present invention;

[0030] Figure 12 This is a schematic diagram of the layered structure forming the second sub-part in one embodiment of the present invention.

[0031] The components in the diagram are shown below:

[0032] Chip carrier 1; Core layer 10;

[0033] First surface 11; Second surface 12;

[0034] Conductive hole 13; First hole wall 131;

[0035] Second hole wall 132; First filling area 133;

[0036] Second filling area 134; Third filling area 135;

[0037] Conductive post 20; First sub-part 21;

[0038] Second sub-section 22; First wiring layer 31;

[0039] Second wiring layer 32; wiring structure 33;

[0040] Medium structure 34; barrier layer 41;

[0041] Seed layer 42; Liquid column 21';

[0042] 50 solder balls;

[0043] Chip 2; Circuit board 3. Detailed Implementation

[0044] The following description, with reference to the accompanying drawings, illustrates preferred embodiments of the present invention, demonstrating its implementability. These embodiments provide a complete overview of the invention for those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments mentioned herein.

[0045] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. The dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component. To make the illustrations clearer, the thickness of components is appropriately exaggerated in some places in the drawings.

[0046] Furthermore, the following descriptions of the embodiments of the invention are made with reference to the accompanying illustrations, illustrating specific embodiments in which the invention can be implemented. Directional terms used in this invention, such as "upper," "lower," "front," "rear," "left," "right," "inner," "outer," and "side," are merely directional references to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of the invention, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0047] When a component is described as being "on" another component, the component may be placed directly on the other component; alternatively, there may be an intermediate component on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "installed to" or "connected to" another component, both can be understood as being directly "installed" or "connected" to, or as being indirectly "installed to" or "connected to" another component via an intermediate component.

[0048] In related semiconductor technologies, glass core-layer based chip packaging technology uses a glass substrate as the core layer, encapsulating the chip on or inside the glass core layer to form a chip packaging structure. This chip packaging structure has the advantages of good electrical performance and low manufacturing cost. However, with the evolution of advanced packaging structures such as 2.5D and 3D towards higher wiring density and higher reliability, the via size of the core layer in the chip carrier is also becoming smaller and smaller. In related technologies, the electroplating process for fabricating conductive pillars with high aspect ratio (AR) faces the following inherent challenges: Firstly, the current density and deposition rate are highest in the orifice region, making it prone to "necking" and premature sealing in the early stages of electroplating. Once the orifice is sealed, the flow path of the electrolyte inside the hole is cut off, and copper ions cannot replenish the middle position of the through hole, resulting in fatal voids in the conductive pillar and severely affecting its performance. Secondly, the conductive pillar fabrication processes used in related technologies introduce new problems such as long process cycles, excessive waste liquid, mechanical scratches, and thermal stress concentration, which cannot meet the requirements of advanced packaging structures for high yield, high cycle time, and no damage.

[0049] Based on the technical problems raised in the aforementioned related semiconductor technologies, one embodiment of the present invention provides a chip carrier 1 and its fabrication method. The chip carrier 1 includes a core layer 10 and conductive pillars 20 disposed in the core layer 10. Furthermore, the fabrication method of the chip carrier 1 utilizes both laser reduction and electroplating to achieve void-free filling of the conductive pillars 20, thereby improving the structural strength and electrical performance of the conductive pillars 20 and increasing the production yield of the chip carrier.

[0050] like Figure 1 As shown, the chip carrier 1 includes a core layer 10 and a plurality of conductive pillars 20. In some embodiments of the present invention, the chip carrier also includes a first wiring layer 31 and a second wiring layer 32.

[0051] The core layer 10 includes a first surface 11 and a second surface 12 that are arranged opposite to each other and parallel to each other. A first wiring layer 31 is disposed on the first surface 11 of the core layer 10, and a second wiring layer 32 is disposed on the second surface 12 of the core layer 10. The core layer 10 is provided with a plurality of conductive holes 13, and conductive posts 20 are disposed in the conductive holes 13. The first wiring layer 31 and the second wiring layer 32, located on both sides of the core layer 10, are electrically connected through the conductive posts 20 in the conductive holes 13.

[0052] Specifically, the conductive hole 13 penetrates the core layer 10, and the extension direction of the conductive hole 13 is perpendicular to the first surface 11 and the second surface 12, that is, the axial central axis of the conductive hole 13 is perpendicular to the first surface 11 and the second surface 12. The conductive post 20 fills the corresponding conductive hole 13, and the two end faces of the conductive post 20 in the extension direction of the conductive hole 13, respectively, are located in the same plane, that is, the two ends of the conductive post 20 in the extension direction of the conductive hole 13 are flush with the corresponding surface in the core layer 10, thereby preventing the two ends of the conductive post 20 from protruding from the surface of the core layer 10 and affecting the surface flatness of the core layer 10, thereby improving the adhesion between the core layer 10 and other film layers.

[0053] The conductive post 20 includes a first sub-part 21 and at least two second sub-parts 22. For example... Figure 2As shown, in a direction perpendicular to the plane of the core layer 10 (the extension direction of the conductive hole 13 is parallel to this direction), multiple second sub-parts 22 are respectively located at both ends of the first sub-part 21, and the end of the first sub-part 21 near the first surface 11 is connected to a second sub-part 22, and the end of the first sub-part 21 near the second surface 12 is connected to another second sub-part 22. The surface of the second sub-part 22 facing away from the first sub-part 21 is flush with the first surface 11 or the second surface 12 of the core layer 10. In this embodiment of the invention, the first sub-part 21 and the second sub-part 22 in the conductive post 20 are prepared by different processes, and the first sub-part 21 located at the middle position of the conductive hole 13 is prepared first, followed by the second sub-part 22 located at the opening of the conductive hole 13, thereby preventing voids in the conductive post 20 in the conductive hole 13, improving the structural strength of the conductive post 20, and also improving the conductivity of the conductive hole 13. Furthermore, the first sub-part 21 can be prepared by laser processing, and the second sub-part 22 can be prepared by electroplating.

[0054] Optionally, the width of the conductive hole 13 in the direction parallel to the plane of the core layer 10 is 10-30 micrometers, and the aspect ratio of the conductive hole 13 (i.e., the ratio between the depth of the conductive hole 13 in the plane perpendicular to the plane of the core layer 10 and its width in the direction parallel to the plane of the core layer 10) is greater than or equal to 10 and less than 20, so as to form a smaller size conductive hole 13. This smaller size conductive hole 13 facilitates capillary action between the ink material of the first sub-part 21 and the hole wall of the conductive hole 13 during the fabrication of the first sub-part 21, thereby promoting ink retention in the conductive hole 13. In some embodiments of the present invention, the width of the conductive hole 13 in the direction parallel to the plane of the core layer 10 can be at least one of 15 micrometers, 20 micrometers, or 25 micrometers, and the aspect ratio of the conductive hole 13 can be at least one of 12, 15, or 18.

[0055] Furthermore, in a direction parallel to the plane of the core layer 10, the width of the first sub-part 21 is less than or equal to the width of the second sub-part 22, and the width of the second sub-part 22 on the side away from the first sub-part 21 is less than the width of the second sub-part 22 on the side closer to the first sub-part 21, thereby forming a conductive hole 13 structure that is wide at both ends and narrow in the middle. This facilitates the ink material of the first sub-part 21 to remain at the middle position of the conductive hole 13 under the action of surface tension during the fabrication of the first sub-part 21. Optionally, the hole wall of the conductive hole 13 can be as follows: Figures 2-4 At least one of the shapes shown, such as arc, rhombus, and stepped shape.

[0056] Taking a conductive post 20 with a prismatic hole wall as an example, such as Figure 2As shown, the hole wall of the conductive hole 13 is formed by splicing together at least two annular surfaces. That is, the conductive hole 13 includes a first hole wall 131 and a second hole wall 132 connected in sequence in a direction perpendicular to the plane where the core layer 10 is located. There is an included angle α between the first hole wall 131 and the second hole wall 132. The included angle α is located on the side of the first hole wall 131 and the second hole wall 132 away from the conductive hole 13, and the angle of the included angle α is less than 180°. This causes the cross section of the conductive hole 13 perpendicular to the first surface 11 and the second surface 12 to be an hourglass shape that is wide at both ends and narrow in the middle. When the first sub-part 21 is prepared, the ink filled into the conductive hole 13 will stay in the narrow middle part of the conductive hole 13 to facilitate the subsequent preparation of the second sub-part 22.

[0057] Optionally, the core layer 10 may be made of at least one of organic and inorganic materials. Inorganic materials generally exhibit better chemical stability than organic materials, effectively resisting environmental corrosion such as moisture and acids / alkalis. Therefore, the core layer 10 is preferably made of inorganic materials, such as glass. The inorganic core layer 10 exhibits better high-temperature resistance than the organic core layer 10, better adapting to the high-temperature environment in subsequent manufacturing processes. Furthermore, the coefficient of thermal expansion of the inorganic core layer 10 is similar to that of the material in chip 2, thus reducing stress warping problems caused by thermal mismatch. In addition, the surface of the inorganic core layer 10 has superior flatness and lower roughness compared to the organic core layer 10, enabling denser wiring. Simultaneously, the inorganic core layer 10 also possesses extremely low dielectric constant and dielectric loss, which can improve signal transmission speed and signal integrity, making it more conducive to developing advanced chip packaging structures with high computing power.

[0058] The first wiring layer 31 and the second wiring layer 32 are respectively disposed on both sides of the core layer 10. Both the first wiring layer 31 and the second wiring layer 32 are provided with a trace structure 33 and a dielectric structure 34. The trace structure 33 in the first wiring layer 31 and the second wiring layer 32 is in contact with both ends of the corresponding conductive post 20 (i.e., the ends of the two second sub-parts 22 away from the first sub-part 21), thereby enabling data and signal transmission between the first wiring layer 31 and the second wiring layer 32 through the corresponding conductive post 20. The dielectric structure 34 is disposed around the corresponding trace structure 33, thereby insulating and protecting the trace structure 33 and preventing short circuits between adjacent traces in the trace structure 33.

[0059] Optionally, the wiring structure 33 in the first wiring layer 31 and the second wiring layer 32 includes a metallic material, while the dielectric structure 34 includes an insulating material. Optionally, the wiring structure 33 in the first wiring layer 31 and the second wiring layer 32 includes at least one of the following metallic materials: copper (Cu), aluminum (Al), gold (Au), and nickel (Ni); and the dielectric structure 34 in the first wiring layer 31 and the second wiring layer 32 includes one of the following insulating materials: silicon oxide (SiOx), silicon nitride (SiNx), resin, polyimide (PI), and ABF (Ajinomoto Build-up Film).

[0060] In other embodiments of the present invention, the chip carrier 1 provided does not limit the number of film layers of the wiring structure 33 and the dielectric structure 34 in its first wiring layer 31 and second wiring layer 32. The number of film layers of the wiring structure 33 and the dielectric structure 34 can be adjusted according to actual needs. For example, the first wiring layer 31 and the second wiring layer 32 can be a stacked structure of a single-layer wiring structure 33 and a single-layer dielectric structure 34, or it can be an overlapping structure of multiple layers of wiring structure 33 and multiple layers of dielectric structure 34 (i.e., a redistribution layer structure, or RDL for short).

[0061] In some embodiments of the present invention, a chip packaging structure is also provided, such as... Figure 5 As shown, the chip package structure includes a chip carrier 1 and a chip 2 as described above. The chip carrier 1 also has solder balls 50 disposed on the side of the second wiring layer 32 opposite to the core layer 10 and electrically connected to the wiring structure 33 in the second wiring layer 32. The chip 2 is disposed on the side of the first wiring layer 31 of the chip carrier 1 opposite to the core layer 10, and is electrically connected to the wiring in the first wiring layer 31. This chip package structure can be electrically connected to the circuit board 3 via the solder balls 50, and the chip 2 mounted on the chip carrier 1 can be electrically connected to the circuit board 3 via the conductive structure in the chip carrier 1, thereby enabling data and signal transmission between the chip 2 and the circuit board 3. This chip package structure can be applied to electronic devices such as mobile phones, desktop computers, laptops, tablets, automotive displays, and wearable devices. Because this chip package structure includes the chip package structure described in this application, the reliability of the electronic device is higher.

[0062] In one embodiment of the present invention, a method for preparing a chip carrier 1 is also provided, for preparing the chip carrier 1 as described above. The process of the method for preparing the chip carrier 1 is as follows: Figure 6 As shown, it includes steps S10-S50.

[0063] Step S10) Forming conductive holes 13 in the core layer 10:

[0064] Prepare a core layer 10, the material of which includes at least one of inorganic and organic materials; optionally, the material of the core layer 10 is glass.

[0065] like Figure 7 As shown, a plurality of conductive holes 13 are formed in the core layer 10. The core layer 10 includes a first surface 11 and a second surface 12 that are arranged opposite to each other and parallel to each other. The extension direction of the conductive holes 13 is perpendicular to the first surface 11 and the second surface 12, and the cross-sectional shape of the conductive holes 13 perpendicular to the first surface 11 and the second surface 12 is a structure that is wider at the top and bottom ends and narrower in the middle. Specifically, in the direction perpendicular to the plane of the core layer 10, the conductive holes 13 include a first filling region 133, a second filling region 134 and a third filling region 135 connected in sequence.

[0066] Optionally, in this step, multiple conductive holes 13 can be formed in the glass core layer 10 using TGV (Through Glass Via) technology. When forming the conductive holes 13 using the TGV process, at least one of the following techniques can be employed: laser-induced wet etching, laser melting, focused discharge machining, plasma etching, and electrochemical discharge machining. In some embodiments of the present invention, laser-induced wet etching is preferably used to form the conductive holes 13 in this step. For example, the conductive holes 13 can be processed by using laser-induced modification of the glass core layer 10 and by forming TGV holes in the core layer 10 through wet etching. Specifically, the glass at the location where the conductive holes 13 are to be formed on the core layer 10 is induced to modify by laser irradiation, and then the core layer 10 to which the conductive holes 13 are to be formed is removed by wet etching to form the conductive holes 13. The core layer 10 where the conductive hole 13 is to be formed is etched faster by laser induction than other areas that are not laser-induced, thus enabling the conductive hole 13 to be formed quickly on the glass core layer 10. Of course, laser drilling, sandblasting, mechanical drilling, etc. can also be used. This application does not impose any special limitation on the specific forming method of the conductive hole 13 in the core layer 10.

[0067] Furthermore, after the conductive hole 13 is formed, the surface of the core layer 10 can be cleaned with deionized water to remove impurities and contaminants remaining on the surface of the core layer 10 during the hole opening process. After cleaning, the core layer 10 is dehydrated for about 10 minutes in a high-temperature environment (i.e., a temperature greater than 100°C, such as 120°C) to remove water stains from the surface of the core layer 10.

[0068] like Figure 8As shown, a barrier layer 41 and a seed layer 42 are sequentially sputtered onto the surface of the core layer 10 using a physical vapor deposition (PVD) process. The barrier layer 41 covers the exposed surface of the core layer 10, while the seed layer 42 covers the surface of the barrier layer 41 facing away from the core layer 10. The barrier layer 41 enhances the adhesion of the seed layer 42 to the surface of the core layer 10, and the seed layer 42 is used in subsequent processes to fabricate the second sub-part 22 via electroplating. Optionally, the thickness of the barrier layer 41 is 50 nm to 100 nm, and the thickness of the seed layer 42 is 100 nm to 500 nm; for example, the thickness of the barrier layer 41 can be 60 nm, 75 nm, or 90 nm, and the thickness of the seed layer 42 can be 150 nm, 300 nm, or 400 nm.

[0069] Optionally, the materials of the barrier layer 41 and the seed layer 42 include metals. For example, the material of the barrier layer 41 includes at least one of titanium (Ti) and tantalum nitride (TaN), and the material of the seed layer 42 includes at least one of copper (Cu), nickel (Ni), gold (Au), titanium (Ti), and tungsten (W). In some embodiments of the present invention, before forming the barrier layer 41 and the seed layer 42 by sputtering, the exposed surface of the core layer 10 can be pretreated by plasma to make the surface roughness of the core layer 10 less than 200 nanometers, providing an atomically smooth surface for subsequent processes, thereby improving the adhesion of the barrier layer 41 material to the surface of the core layer 10.

[0070] Step S20) Forming a liquid column 21' in the conductive hole 13:

[0071] Prepare an ink comprising a metal oxide, a dispersant, and a solvent. The ink has a solid content of 10wt%-12wt% (e.g., 11wt%), meaning the total content of the metal oxide and dispersant is 10wt%-12wt%, with the metal oxide content being less than the dispersant content. Optionally, the ratio of metal oxide to dispersant can be 1:1.25-1:2. Further, the solvent in the ink can be ethylene glycol and water, and the ratio of metal oxide, dispersant, and ethylene glycol to water can be one of 7:3, 3:2, or 4:1. The dispersant is used to prevent the metal oxide particles from agglomerating, promoting uniform and stable dispersion of the metal oxides in the ink. In some embodiments of the invention, the viscosity of the ink can be adjusted by changing the proportion of water in the ink to accommodate conductive holes 13 of different sizes. Optionally, the viscosity of the ink can be adjusted to 8cP-15cP, for example, 10cP, 11cP, or 12cP, depending on requirements.

[0072] Optionally, the metal oxide is a metal oxide particle with a particle size of 20 nm to 40 nm, and the dispersant has a molecular weight of 35 kg / mol to 45 kg / mol. For example, the metal oxide can be copper oxide (CuO) particles with a particle size of at least 25 nm, 30 nm, or 35 nm, and the dispersant can be polyvinylpyrrolidone (PVP) with a molecular weight of 40 kg / mol, 42 kg / mol, or 44 kg / mol.

[0073] Ink is sprayed into the conductive hole 13 using an inkjet printing process to form a shape such as... Figure 9 The liquid column 21' shown is formed by the special structure of the conductive hole 13, which is wide at both ends and narrow in the middle, and has a small aspect ratio. This causes capillary action between the sprayed ink and the hole wall of the conductive hole 13. Under the action of surface tension, the ink can stay in the second filling area 134, which has the smallest width in the conductive hole 13, to form the liquid column 21'. The liquid column 21' fills the second filling area 134, and its two ends extend into the first filling area 133 and the third filling area 135, respectively, in the direction perpendicular to the plane of the core layer 10. During inkjet printing, the amount of ink sprayed can be precisely controlled by counting droplets, so that the length of the liquid column 21' in the direction perpendicular to the plane of the core layer 10 is less than or equal to the depth of the conductive hole 13 in the direction perpendicular to the plane of the core layer 10. Preferably, the length of the liquid column 21' in the direction perpendicular to the plane of the core layer 10 is 30%-50% of the depth of the conductive hole 13. For example, the length of the liquid column 21' can be 40 micrometers, 45 micrometers, or 50 micrometers.

[0074] like Figure 10As shown, the core layer 10 is preheated in a low-temperature environment (temperature less than 100°C, such as 75°C, 80°C or 85°C) to evaporate about 60%-80% (e.g. 70%) of the liquid phase in the liquid column 21', causing the volume of the liquid column 21' to shrink and the viscosity to increase. Under the action of liquid surface tension and viscosity, the liquid column 21' still adheres to the hole wall of the conductive hole 13, so that the width of the liquid column 21' in the direction parallel to the plane of the core layer 10 does not change, while the length of the liquid column 21' in the direction perpendicular to the plane of the core layer 10 shrinks. That is, the length of the liquid column 21' after the heating step is less than its length before the heating step, thereby forming blind holes (i.e., spaces not filled by the liquid column 21') at the upper and lower ends of the liquid column 21', so as to reserve space for the preparation of the second sub-part 22. Optionally, the length of the liquid column 21' after heating and pre-drying in the direction perpendicular to the plane of the core layer 10 can be 35 micrometers to 45 micrometers. The distance between the end of the liquid column 21' near the first surface 11 and the first surface 11 can be 10 micrometers to 20 micrometers. The distance between the end of the liquid column 21' near the second surface 12 and the second surface 12 can also be 10 micrometers to 20 micrometers. The distances between the two ends of the liquid column 21' and the adjacent surface of the core layer 10 can be equal or unequal.

[0075] Step S30) The liquid column 21' is reduced by laser process to form the first sub-part 21:

[0076] The liquid column 21' is irradiated with a laser with a pulse width in the picosecond or femtosecond range. After absorbing the energy from the laser, the liquid column 21' rapidly and completely evaporates its liquid phase. Meanwhile, the metal oxides within the liquid column 21' also rapidly heat up under laser irradiation, thereby reducing the metal oxides to metal through the principle of laser welding, to form a structure like... Figure 11 The first sub-part 21, made of metal, is shown in the second filling region 134. Taking copper oxide as an example, the copper oxide particles are reduced to metallic copper under laser irradiation, thereby forming a first sub-part 21 containing metallic copper in the second filling region 134 of the conductive hole 13. The reduction rate of the metallic copper is greater than 95%, the grain size is 60 nanometers, and it is continuous without voids.

[0077] Optionally, the laser wavelength used in this step can be adjusted according to the properties of the metal oxide used in the ink. For example, copper oxide has a high reflectivity to infrared light (such as 1064 nm), so traditional infrared lasers are not recommended. Lasers with wavelengths of 10 nm to 560 nm are preferred, such as 532 nm green light, 450 nm blue light, or 355 nm ultraviolet light. Furthermore, in this step, the energy loss of the laser penetrating the core layer 10 is less than 8%, the width of the heat-affected zone of the ultrafast laser with picosecond or femtosecond pulse width is less than 1 micrometer, and the core layer 10 will not develop cracks.

[0078] (Step S40) Forming second sub-parts 22 at both ends of the first sub-part 21:

[0079] Metal material is formed on the seed layer 42 exposed in the conductive hole 13 by electroplating. This metal material fills the blind holes (i.e., the first filling area 133 and the third filling area 135) located at both ends of the first sub-part 21 in the conductive hole 13, and connects to both ends of the first sub-part 21. The first sub-part 21 and the second sub-parts 22 located at its two ends are combined to form a structure as shown in the figure. Figure 12 The conductive post 20 shown in the figure.

[0080] Specifically, taking copper oxide as an example, the electroplating solution used during electroplating includes copper sulfate, chloride ions, sulfur hydrogen oxide and water, and the current density is 0.5ASD-2ASD. The first sub-part 21 can serve as the common cathode for the two blind holes at its two ends, enabling the two blind holes to be electroplated simultaneously (the growth rate of the upper and lower sections is less than 5%) to form the second sub-part 22.

[0081] After this step, the barrier layer 41, seed layer 42, and metal material on the seed layer 42 on the first surface 11 and the second surface 12 of the core layer 10 can be removed by grinding or etching processes, and the surface of the core layer 10 can be planarized, so that the first surface 11 and the second surface 12 of the core layer 10 are also exposed, so as to facilitate the subsequent preparation of a wiring layer with better compatibility.

[0082] Step S50) A first wiring layer 31 and a second wiring layer 32 are fabricated on both sides of the core layer 10:

[0083] Multilayer metal traces are fabricated on the first surface 11 and the second surface 12 of the core layer 10 using an electroplating process to form the trace structure 33 in the first wiring layer 31 and the second wiring layer 32. In some embodiments of the present invention, the number of metal trace layers can be selected according to different needs. A dielectric structure 34 surrounding the trace structure 33 is formed on both sides of the core layer 10 using processes such as coating and lamination, thereby forming the first wiring layer 31 and the second wiring layer 32 on both sides of the core layer 10, ultimately forming a structure as shown in the diagram. Figure 1 The chip carrier board 1 described herein.

[0084] In the chip carrier and its preparation method provided in the embodiments of the present invention, a first sub-part without voids is first prepared in the conductive hole by laser process, thereby forming blind holes at both ends of the first sub-part. When the second sub-part is prepared by electroplating process, the electroplating solution can still flow in the blind hole to achieve the effect of "material in the middle and still open at the top and bottom" for local sealing. At the same time, electroplating filling in blind holes is less difficult and has fewer voids than electroplating filling in through holes, which also leads to a higher success rate, improves the structural strength and conductivity of the prepared conductive pillar, and thus improves the performance and production yield of the chip carrier.

[0085] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A method for preparing a chip carrier, characterized in that, include: Conductive holes are formed in the core layer. In a direction perpendicular to the plane of the core layer, the conductive holes include a first filling area, a second filling area, and a third filling area connected in sequence. A seed layer is formed on the surface of the core layer, the seed layer extending from the first filling region and the third filling region to the second filling region; An ink is provided, the ink further comprising a dispersant, wherein the content of metal oxide in the ink is less than the content of the dispersant; the particle size of the metal oxide is 20 nanometers-40 nanometers; and the molecular weight of the dispersant is 35 kg / mol-45 kg / mol. A liquid column is formed in the conductive hole, and the liquid column fills the second filling area. In the direction perpendicular to the plane where the core layer is located, the length of the liquid column is 30%-50% of the depth of the conductive hole. The core layer is heated to evaporate a portion of the liquid phase in the liquid column. In a direction perpendicular to the plane of the core layer, the length of the liquid column after the heating step is less than the length before the heating step. The core layer includes a first surface and a second surface disposed opposite to each other. The extension direction of the conductive hole is perpendicular to the first surface and the second surface. After the heating step, the distance between the end of the liquid column near the first surface and the first surface is 10-20 micrometers, and the distance between the end of the liquid column near the second surface and the second surface is also 10-20 micrometers. The liquid column is reduced by laser process to form a first sub-part, which is located in the second filling area of ​​the conductive hole. The laser wavelength used is 10 nanometers to 560 nanometers, and the pulse width of the laser used is at least one of picosecond or femtosecond. A second sub-part is formed at both ends of the first sub-part. The second sub-part fills the first filling area and the third filling area of ​​the conductive hole. The two ends of the first sub-part are connected to the corresponding second sub-part to form a conductive pillar. The second sub-part is formed in the conductive hole by an electroplating process.

2. The method for preparing a chip carrier as described in claim 1, characterized in that, The step of forming a liquid column in the conductive hole includes: Ink is sprayed into the conductive hole to form the liquid column, the ink comprising a metal oxide, the liquid column filling the second filling area, and the liquid column extending at both ends in a direction perpendicular to the plane of the core layer into the first filling area and the third filling area, respectively.

3. The method for preparing a chip carrier as described in claim 2, characterized in that, The ink also includes a solvent, and the solid content of the ink is 10wt%-12wt%.

4. The method for preparing a chip carrier as described in claim 1, characterized in that, Before the step of forming a seed layer on the surface of the core layer, the method further includes forming a barrier layer on the surface of the core layer.

5. A chip carrier board, characterized in that, It is prepared by the chip carrier board preparation method as described in any one of claims 1-4; The chip carrier includes: A core layer, wherein conductive holes are provided in the core layer; A conductive post is disposed in the conductive hole, and the conductive post includes a first sub-part and at least two second sub-parts, the at least two second sub-parts being located at both ends of the first sub-part in a direction perpendicular to the plane of the core layer.

6. The chip carrier board as described in claim 5, characterized in that, In a direction parallel to the plane containing the core layer, the width of the first sub-part is less than or equal to the width of the second sub-part; In a direction parallel to the plane of the core layer, the width of the second sub-part away from the first sub-part is smaller than the width of the second sub-part closer to the first sub-part.

7. A chip packaging structure, characterized in that, Includes the chip carrier as described in any one of claims 5-6.

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