A simulation result display method and device, a storage medium and an apparatus

Abstract

This application belongs to the field of simulation technology, specifically relating to a method, apparatus, storage medium, and device for displaying simulation results. The display method includes: obtaining a global program count address and instruction information based on a firmware logic file, and constructing a reference address mapping table based on the global program count address and the instruction information; wherein, the firmware logic file is a file storing information related to firmware execution logic; obtaining a firmware program count address based on a firmware signal file; wherein, the global program count address includes the firmware program count address, and the firmware signal file is a file storing information related to response signals generated when the firmware executes the instruction information; during the playback of the instruction information execution, displaying the firmware program count address based on the firmware program count address and the reference address mapping table; this application will improve the debugging efficiency between software and firmware.

Description

Technical Field

[0001] This application belongs to the field of simulation technology, specifically relating to a method, apparatus, storage medium, and device for displaying simulation results. Background Technology

[0002] In related technologies, co-simulation of firmware is a crucial step in verifying system functionality during System on a Chip (SoC) development. Firmware behavior is recorded in firmware signal files, and the execution logic of firmware behavior is embodied in software instructions and stored in firmware logic files. However, during firmware logic debugging, the changes in firmware signals cannot be observed, which severely impacts debugging efficiency.

[0003] Therefore, improving the debugging efficiency between software and firmware is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a method, apparatus, storage medium, and device for displaying simulation results, which solves the problem of low debugging efficiency between software and firmware.

[0005] In a first aspect, this application provides a method for displaying simulation results. The method includes: obtaining a global program count address and instruction information based on a firmware logic file, and constructing a base address mapping table based on the global program count address and the instruction information; wherein the firmware logic file is a file storing information related to firmware execution logic; obtaining a firmware program count address based on a firmware signal file; wherein the global program count address includes the firmware program count address, and the firmware signal file is a file storing information related to response signals generated when the firmware executes the instruction information; and displaying the firmware program count address based on the firmware program count address and the base address mapping table during the playback of the instruction information execution.

[0006] Optionally, displaying the firmware program count address based on the firmware program count address and the reference address mapping table during the playback of the instruction information includes: determining the row in which the firmware program count address is located during the playback of the instruction information based on the firmware program count address and the reference address mapping table; wherein the instruction information consists of multiple rows; rendering the playback instruction information with a target color according to the execution status of the firmware program count address and its row in the playback of the instruction information to display the firmware program count address; wherein the execution status includes: dynamic trajectory status and current focus status.

[0007] Optionally, the method further includes: when the execution state of the firmware program counter address is the current focus state, triggering the pause of the execution playback process of the instruction information.

[0008] Optionally, the instruction information includes: C source program information and / or assembly code information; when the instruction information is the C source program information, the step of constructing a base address mapping table based on the global program count address and the instruction information includes: obtaining the assembly code information based on the C source program information and an assembly tool; constructing a base address mapping table based on the global program count address, the C source program information, and the assembly code information; or, when the instruction information is assembly code information, the step of constructing a base address mapping table based on the global program count address and the instruction information includes: obtaining the C source program information based on the assembly code information and a disassembler; constructing a base address mapping table based on the global program count address, the C source program information, and the assembly code information.

[0009] Optionally, the method further includes: obtaining non-instruction information based on the firmware signal file; wherein the non-instruction information and the firmware program count address share a simulation time axis; constructing a ternary array based on the non-instruction information, the simulation time axis, and the firmware program count address; and during the playback of the instruction information, synchronously displaying the non-instruction information and the firmware program count address based on the firmware program count address and the ternary array.

[0010] Optionally, obtaining non-instruction information from the firmware signal file includes: determining the global variable address range based on memory access signals; and obtaining non-instruction information from the firmware signal file based on the global variable address range and a data export tool.

[0011] Optionally, obtaining the firmware program count address based on the firmware signal file includes: extracting the initial program count address from the firmware signal file; and compensating the initial program count address based on a preset address compensation parameter to obtain the firmware program count address.

[0012] Secondly, this application provides a simulation result display device, the device comprising: a construction module, configured to obtain a global program count address and instruction information according to a firmware logic file, and construct a base address mapping table based on the global program count address and the instruction information; wherein the firmware logic file is a file storing information related to firmware execution logic; an acquisition module, configured to obtain a firmware program count address according to a firmware signal file; wherein the global program count address includes the firmware program count address, and the firmware signal file is a file storing information related to response signals generated when the firmware executes the instruction information; and a display module, configured to display the firmware program count address based on the firmware program count address and the base address mapping table during the playback of the instruction information execution process.

[0013] Thirdly, this application provides a computer-readable storage medium including computer-executable instructions, which, when executed on the computer, cause the computer to perform the simulation result display method described in any of the first aspects.

[0014] Fourthly, this application provides an electronic device including a processor and a memory, wherein the processor is coupled to the memory; the memory is used to store computer instructions, which are loaded and executed by the processor to implement the simulation result display method described in any one of the first aspects in a computer device.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] In this application, the global program counter address and instruction information are obtained from the firmware logic file, and a base address mapping table is constructed based on the global program counter address and instruction information to determine the mapping relationship between the global program counter address and instruction information. The firmware program counter address is obtained from the firmware signal file. During the playback of instruction information execution, the global program counter address and instruction information will be displayed synchronously. Since the global program counter address includes the firmware program counter address, the correspondence between the firmware program counter address and instruction information can be determined based on the firmware program counter address and base address mapping table. Displaying the firmware program counter address during the playback of instruction information execution allows observation of the changes in the firmware program counter address within the instruction information, thereby establishing the relationship between the changes in the firmware's response signals and the firmware execution logic. Users can observe the changes between the firmware's response signals during the debugging process of the firmware execution logic, and debug the firmware execution logic or firmware parameters based on the firmware's response signals, thus improving debugging efficiency. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 A flowchart illustrating a method for displaying simulation results provided in an embodiment of this application is shown.

[0019] Figure 2 A flowchart illustrating another method for displaying simulation results provided in an embodiment of this application is shown.

[0020] Figure 3 A flowchart illustrating another method for displaying simulation results provided in an embodiment of this application is shown.

[0021] Figure 4 A schematic diagram of the structure of a simulation result display device provided in an embodiment of this application is shown.

[0022] Figure 5 This illustration shows a structural schematic diagram of an embodiment of an electronic device provided in this application. Detailed Implementation

[0023] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0024] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0025] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0026] In related technologies, during the development of a System on a Chip (SoC), co-simulation is a crucial step in verifying system functionality. Firmware behavior is recorded in firmware signal storage files such as FastSignal Database (FSDB), while the execution logic of firmware behavior is embodied in software instructions. However, during firmware logic debugging, the changes in firmware signals cannot be observed, which severely impacts debugging efficiency.

[0027] Therefore, improving the debugging efficiency between software and firmware is an urgent problem to be solved.

[0028] Figure 1 This document shows a flowchart illustrating a method for displaying simulation results according to an embodiment of this application. Please refer to [link / reference]. Figure 1 As shown, the display method includes the following steps S110~S130, which are described in detail below.

[0029] S110. Based on the firmware logic file, obtain the global program counter address and instruction information, and construct a base address mapping table based on the global program counter address and instruction information; wherein, the firmware logic file is a file that stores information related to firmware execution logic.

[0030] In some embodiments, the firmware logic file stores firmware execution logic-related information, including the global program counter (PC) address and instruction information. The firmware runs according to the execution logic, which is obtained by editing the instruction information. The process of the firmware executing the instruction information reflects the execution logic. The global program counter (PC) address is the storage address of all instruction information. The instruction information includes multiple instructions, and the global program counter address includes the storage address of each instruction. A base address mapping table is constructed to determine the mapping relationship between instruction information and the global program counter address.

[0031] For example, the firmware logic file can be an Executable and Linkable Format (ELF) file. The instruction information can be assembly code information and / or C source code information. Specifically, regular expressions can be used to extract instruction information from the ELF file. The assembly code information is assembly text. For instance, when the instruction information is assembly code, the following regular expression can be used to extract it: Regex="^([0-9a-fA-F]+):\s+([0-9a-fA-F]{4}|[0-9a-fA-F]{8})\s+. This regular expression requires that the beginning of each line of assembly code information contains a hexadecimal address, followed by 2 or 4 bytes of assembly code information.

[0032] S120. Obtain the firmware program count address based on the firmware signal file; wherein, the global program count address includes the firmware program count address, and the firmware signal file is a file that stores information related to the response signals generated when the firmware executes instruction information.

[0033] In some embodiments, when the firmware executes instruction information, the firmware will respond and generate a corresponding response signal. The relevant information of the response signal is stored in the firmware signal file. The firmware program count address is the address where the response signal is stored. When the firmware generates a response signal, the firmware program count address will jump. By obtaining the firmware program count address, the change characteristics of the firmware's response signal can be determined.

[0034] For example, firmware signal files can specifically be Fast Signal Database (FSDB) files and Value Change Dump (VCD) files. Response signals can include waveform signals, etc. The FSDB file and VCD file can store relevant information about the waveform signals.

[0035] S130. During the execution of the playback instruction information, the firmware program count address is displayed based on the firmware program count address and base address mapping table.

[0036] In some embodiments, after the simulation ends, during the playback of instruction information execution, the global program counter address and instruction information will be displayed synchronously to facilitate the analysis of the instruction information execution process and thus enable debugging of the instruction information. Since the global program counter address includes the firmware program counter address, the correspondence between the firmware program counter address and instruction information can be determined according to the firmware program counter address and base address mapping table. During the playback of instruction information execution, the firmware program counter address is displayed, and the change characteristics of the firmware program counter address in the instruction information can be observed, thereby establishing the relationship between the change characteristics of the firmware response signal and the firmware execution logic. Users can observe the changes between the firmware response signals during the debugging of the firmware execution logic, and debug the firmware execution logic or firmware parameters based on the firmware response signals, which can improve debugging efficiency.

[0037] Figure 2 This document illustrates a flowchart of another method for displaying simulation results provided in an embodiment of this application. Please refer to [link / reference]. Figure 2 As shown, Figure 1 S130 includes the following S210~S220, which are described in detail below.

[0038] S210. Based on the firmware program count address and base address mapping table, determine the line where the firmware program count address is located during the execution of the playback instruction information; wherein, the instruction information consists of multiple lines.

[0039] In some embodiments, during the execution of playback instruction information, the instruction information is executed line by line. Since the global program address includes the firmware program counter address, and the base address mapping table stores the mapping relationship between the global program address and the instruction information, matching the firmware program counter address with the global program counter address can obtain the position of the firmware program counter address in the global counter address, thereby determining the line in which the firmware program counter address is located during the execution of the playback instruction information.

[0040] It should be noted that the global program counter address is also multiple lines, and the number of lines of the global program counter address may be different from the number of lines of instruction information. One line of global program counter address may correspond to multiple lines of instruction information.

[0041] S220. Based on the execution status of the firmware program counter address and the line it is in during the execution of the playback instruction information, render the instruction information in the playback with the target color to display the firmware program counter address; wherein, the execution status includes: dynamic trajectory status and current focus status.

[0042] In some embodiments, the dynamic trajectory state is the path that the firmware program count address has already executed during the execution of the playback instruction information, and the current focus state is the state in which the firmware program address is being executed during the execution of the playback instruction information. By rendering the instruction information in the playback with the target color according to the execution state of the firmware program address and the line it is in during the execution of the playback instruction information, the user can observe the movement trajectory of the firmware's response signal, thereby establishing the relationship between the changing characteristics of the firmware's response signal and the firmware execution logic.

[0043] For example, the target color may include: a first color, a second color, a third color, and a fourth color; the line containing the address of the unexecuted firmware program in the code information can be marked with the first color, the address of the executed firmware program can be marked with the second color, the address of the currently executing firmware program can be marked with the third color, and the fourth color represents the color of the code information when playback is not started. The first color can be black, the second color can be light green, the third color can be dark green, and the fourth color can be light gray. It should be noted that the specific colors of the first, second, third, and fourth colors are not limited here and can be set according to actual needs.

[0044] In some embodiments, during the execution of replay instruction information, the following operations can also be performed: full-speed operation, single-step operation, and Goto operation. Full-speed operation means completing the entire replay process from the current position to the trajectory endpoint in one go, which can verify the correctness of the overall process. Single-step operation means executing only one instruction at a time, which can analyze the details of instruction execution in detail. Goto operation means jumping directly to a specified time point, global program address, or instruction sequence number, which can quickly locate known abnormal points or key instruction positions and skip irrelevant normal processes.

[0045] In some embodiments, the method further includes: pausing the instruction information playback process when the execution state of the firmware program counter address is the current focus state. Pausing the instruction information playback process when the execution state of the firmware program counter address is the current focus state allows the user to analyze the contextual instruction information of the firmware's response signals, thereby improving debugging efficiency between the software and firmware.

[0046] In some embodiments, the instruction information includes: C source program information and / or assembly code information. During the replay of the instruction information execution, only the execution process of the C source program information and global program information, or the execution process of the assembly code information and global program information, may be displayed, or the C source program information, assembly code information, and global program information may be displayed simultaneously.

[0047] In some embodiments, when the instruction information is C source program information, a base address mapping table is constructed based on the global program count address and the instruction information, including: obtaining assembly code information based on the C source program information and the assembly tool; and constructing a base address mapping table based on the global program count address, the C source program information, and the assembly code information.

[0048] For example, C source program information and assembly code information can be converted to each other. When the instruction information is C source program information, it can be converted into assembly code information using an assembler. A base address mapping table can then be constructed based on the global program counter address, C source program information, and assembly code information. This allows the movement trajectory of the global program counter address, C source program information, assembly code information, and target program address to be displayed simultaneously during instruction playback. For example, assemblers such as objdump and Radare2 can be used.

[0049] In some embodiments, when the instruction information is assembly code information, a base address mapping table is constructed based on the global program count address and the instruction information, including: obtaining C source program information based on the assembly code information and a disassembler; and constructing a base address mapping table based on the global program count address, the C source program information, and the assembly code information.

[0050] For example, when the instruction information is assembly code, it can be converted into C source program information using a disassembler. A base address mapping table can then be constructed based on the global program counter (GPC), C source program information, and assembly code information. This allows the movement trajectories of the GPC, C source program information, assembly code information, and target program address to be displayed simultaneously during instruction playback. Disassemblers such as GCC / G++ and Keil ARM Compiler can be used.

[0051] Figure 3 This document illustrates a flowchart of another method for displaying simulation results provided in an embodiment of this application. Please refer to [link / reference]. Figure 3 As shown, the display method includes the following steps S310~S330, which are described in detail below.

[0052] S310. Obtain non-instruction information based on the firmware signal file; wherein, the non-instruction information and the firmware program count address share the simulation time axis.

[0053] In some embodiments, non-instruction information may specifically include at least one of the following: bus address, peripheral status, register status, RAM access address, etc.

[0054] S320, based on non-instruction information, simulation timeline and firmware program count address, constructs a ternary array.

[0055] In some embodiments, during the simulation process, the firmware program count address and non-instruction information share the simulation time axis. A ternary array is constructed using the non-instruction information, the simulation time axis, and the firmware program count address to determine the mapping relationship between the non-instruction information and the firmware program count address.

[0056] S330. During the playback of instruction information, non-instruction information is displayed synchronously with the firmware program count address based on the firmware program count address and the ternary array.

[0057] In some embodiments, during the playback of instruction information, the mapping relationship between non-instruction information and firmware program address can be determined by the firmware program count address and the ternary array. At the same time as the firmware program address, the corresponding non-instruction information is displayed, thereby realizing the synchronous display of global program count address, instruction information, firmware program count address and non-instruction information, so as to improve the user's debugging efficiency.

[0058] In some embodiments, obtaining non-instruction information from the firmware signal file includes: determining the address range of global variables based on memory access signals; and obtaining non-instruction information from the firmware signal file based on the address range of global variables and a data export tool.

[0059] For example, the address range of global variables can be calculated through memory access signals. This range can be the storage space for non-instruction information. By using a data export tool and the address range of the global variables containing non-instruction information, the non-instruction information can be obtained. Exporting only the necessary non-instruction information reduces the amount of data processed, thus improving the efficiency of non-instruction information extraction. For instance, the address range of global variables could be: $[Addr_{min}, Addr_{max}]$, and the export tool could be fsdbreport, etc. The export process can be implemented using the following code: -exp "(ram_addr>= Addr_min)&&(ram_addr<= Addr_max)".

[0060] In some embodiments, obtaining the firmware program count address based on the firmware signal file includes: extracting the initial program count address from the firmware signal file; and compensating the initial program count address based on a preset address compensation parameter to obtain the firmware program count address.

[0061] For example, when there is instruction alignment or frequency multiplication logic between the processor architecture and instruction information, the extracted initial program counter address cannot be directly matched with the global program counter address. A preset address compensation parameter is used to compensate the initial program counter address to obtain the actual firmware program counter address, enabling it to match the global program counter address. For instance, the preset address compensation coefficient can be 2 times, and the compensation process can be implemented using the following code: $PC_{real} = PC_{trace} \times 2$.

[0062] Figure 4 This paper shows a schematic diagram of the structure of a simulation result display device provided in an embodiment of this application. Please refer to [link / reference]. Figure 4 As shown, the simulation result display device 400 includes: a construction module 410, an acquisition module 420, and a display module 430.

[0063] The construction module 410 is used to obtain the global program count address and instruction information based on the firmware logic file, and to construct a base address mapping table based on the global program count address and instruction information; wherein, the firmware logic file is a file that stores information related to firmware execution logic;

[0064] The acquisition module 420 is used to obtain the firmware program count address based on the firmware signal file; wherein, the global program count address includes the firmware program count address, and the firmware signal file is a file that stores information related to the response signals generated when the firmware executes instruction information;

[0065] Display module 430 is used to display the firmware program count address based on the firmware program count address and base address mapping table during the execution of playback instruction information.

[0066] The simulation result display device provided in the above embodiments and the simulation result display method provided in the foregoing embodiments belong to the same concept. The specific way in which each module and unit performs operations has been described in detail in the method embodiments, and will not be repeated here.

[0067] Figure 5 The diagram shows a structural schematic of an embodiment of an electronic device provided in this application. Please refer to [link / reference]. Figure 5 As shown, the electronic device includes: a controller; and a memory for storing one or more programs, which, when executed by the controller, perform the simulation result display method described above.

[0068] Please continue reading. Figure 5 As shown, the computer system 500 of this electronic device includes a Central Processing Unit (CPU) 501, which can perform various appropriate actions and processes, such as executing the methods described in the above embodiments, based on programs stored in Read-Only Memory (ROM) 502 or programs loaded from storage portion 508 into Random Access Memory (RAM) 503. The RAM 503 also stores various programs and data required for system operation. The CPU 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0069] The following components are connected to I / O interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to I / O interface 505 as needed. Removable media 511, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 510 as needed so that computer programs read from them can be installed into storage section 508 as needed.

[0070] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program including a computer program for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 509, and / or installed from removable medium 511. When the computer program is executed by central processing unit (CPU) 501, it performs various functions defined in the system of this application.

[0071] Another aspect of this application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the simulation result display method described above. This computer-readable storage medium may be included in the electronic device described in the above embodiments, or it may exist independently and not assembled into the electronic device.

[0072] Another aspect of this application provides a computer program product or computer program that includes at least one executable instruction that, when executed on a simulation result display device / electronic device, causes the simulation result display device / electronic device to perform the simulation result display method as described above.

[0073] Specifically, the executable instructions can be used to cause the simulation result display device / electronic device to perform the following operations:

[0074] Based on the firmware logic file, the global program counter address and instruction information are obtained, and a base address mapping table is constructed based on the global program counter address and instruction information; wherein, the firmware logic file is a file that stores information related to firmware execution logic;

[0075] The firmware program counter address is obtained from the firmware signal file; the global program counter address includes the firmware program counter address, and the firmware signal file is a file that stores information related to the response signals generated when the firmware executes instructions.

[0076] During the execution of the replay instruction information, the firmware program count address is displayed based on the firmware program count address and base address mapping table.

[0077] The computer-readable medium shown in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying a computer-readable computer program. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0078] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0079] The units described in the embodiments of this application can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0080] According to one aspect of the embodiments of this application, a computer system is also provided, including a Central Processing Unit (CPU), which can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) or a program loaded from storage into random access memory (RAM), such as performing the methods described above. Various programs and data required for system operation are also stored in the RAM. The CPU, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0081] The following components are connected to the I / O interface: input components including keyboards, mice, etc.; output components including cathode ray tubes (CRTs), liquid crystal displays (LCDs), and speakers; storage components including hard drives; and communication components including network interface cards such as LAN (Local Area Network) cards and modems. The communication components perform communication processing via networks such as the Internet. Drives are also connected to the I / O interface as needed. Removable media, such as disks, optical discs, magneto-optical discs, semiconductor memories, etc., are installed on the drive as needed so that computer programs read from them can be installed into the storage components as required.

[0082] The above description is merely a preferred exemplary embodiment of this application and is not intended to limit the implementation of this application. Those skilled in the art can easily make corresponding modifications or alterations based on the main concept and spirit of this application. Therefore, the scope of protection of this application should be determined by the scope of protection claimed in the claims.

[0083] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0084] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0085] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A method for displaying simulation results, characterized in that, The display method includes: According to the firmware logic file, the global program counter address and instruction information are obtained, and a base address mapping table is constructed based on the global program counter address and the instruction information; wherein, the firmware logic file is a file storing firmware execution logic related information, and the firmware execution logic related information includes the global program counter address and the instruction information; The firmware program counter address is obtained from the firmware signal file; wherein, the global program counter address includes the firmware program counter address, and the firmware signal file is a file that stores information related to the response signals generated when the firmware executes the instruction information, and the information related to the response signals includes the firmware program counter address. During the replay of the instruction information, the firmware program count address is displayed based on the firmware program count address and the reference address mapping table.

2. The method for displaying simulation results according to claim 1, characterized in that, During the execution of the replay of the instruction information, displaying the firmware program count address based on the firmware program count address and the reference address mapping table includes: Based on the firmware program counter address and the reference address mapping table, the line in which the firmware program counter address is located during the execution process of replaying the instruction information is determined; wherein, the instruction information consists of multiple lines; Based on the execution status of the firmware program counter address and its position in the line during the execution process of the replaying instruction information, the instruction information in the replay is rendered with the target color to display the firmware program counter address; wherein, the execution status includes: dynamic trajectory status and current focus status.

3. The method for displaying simulation results according to claim 2, characterized in that, The method further includes: when the execution state of the firmware program counter address is the current focus state, triggering the pause of the execution playback process of the instruction information.

4. The method for displaying simulation results according to claim 1, characterized in that, The instruction information includes: C source program information and / or assembly code information; When the instruction information is the C source program information, the step of constructing a base address mapping table based on the global program counter address and the instruction information includes: Based on the C source program information and the assembly tool, the assembly code information is obtained; A baseline address mapping table is constructed based on the global program counter address, the C source program information, and the assembly code information; Alternatively, when the instruction information is assembly code information, the step of constructing a base address mapping table based on the global program counter address and the instruction information includes: Based on the assembly code information and the disassembler, the C source program information is obtained; A baseline address mapping table is constructed based on the global program counter address, the C source program information, and the assembly code information.

5. The method for displaying simulation results according to claim 1, characterized in that, The method further includes: Based on the firmware signal file, non-instruction information is obtained; wherein, the non-instruction information and the firmware program count address share the simulation time axis; A ternary array is constructed based on the non-instruction information, the simulation timeline, and the firmware program count address; During the playback of the instruction information, the non-instruction information is displayed synchronously with the firmware program count address based on the firmware program count address and the ternary array.

6. The method for displaying simulation results according to claim 5, characterized in that, The step of obtaining non-instruction information based on the firmware signal file includes: Determine the address range of global variables based on memory access signals; Based on the global variable address range and data export tool, non-instruction information is obtained from the firmware signal file.

7. The method for displaying simulation results according to claim 1, characterized in that, The step of obtaining the firmware program counter address based on the firmware signal file includes: Extract the initial program counter address from the firmware signal file; The initial program count address is compensated based on preset address compensation parameters to obtain the firmware program count address.

8. A simulation result display device, characterized in that, The device includes: A construction module is used to obtain the global program counter address and instruction information based on the firmware logic file, and to construct a base address mapping table based on the global program counter address and the instruction information; wherein, the firmware logic file is a file storing firmware execution logic related information, and the firmware execution logic related information includes the global program counter address and the instruction information; The acquisition module is used to obtain the firmware program counter address based on the firmware signal file; wherein, the global program counter address includes the firmware program counter address, and the firmware signal file is a file storing information related to response signals generated when the firmware executes the instruction information, and the information related to response signals includes the firmware program counter address; The display module is used to display the firmware program count address based on the firmware program count address and the reference address mapping table during the playback of the instruction information.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes computer-executable instructions that, when executed on the computer, cause the computer to perform the method for displaying simulation results according to any one of claims 1 to 7.

10. An electronic device, characterized in that, It includes a processor and a memory, the processor being coupled to the memory; the memory is used to store computer instructions, which are loaded and executed by the processor to implement the method for displaying simulation results as described in any one of claims 1 to 7.

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