Core particle interconnection interface tracking debugging system and chip

Abstract

The application provides a kind of core particle interconnection interface tracking debugging system and chip, system includes: trigger flag generation module, when target core particle interconnection interface IP reaches preset trigger condition, generates trigger flag;Interface data capture module, real-time capture the internal interface data of the target core particle interconnection interface IP, and after receiving trigger flag, continue to capture the internal interface data of preset quantity and stop capturing;It is provided with the timer that working clock is synchronized with target core particle interconnection interface IP, for each group of effective interface data captured to generate timestamp information;Interface data capture module and target core particle interconnection interface IP between using the mechanism based on credit for data flow control, to notify target core particle interconnection interface IP interface data capture module current data amount that can be received.Utilizing the application, can guarantee that there is no data loss in the whole tracking debugging process, effectively improve the effectiveness of data capture, and then improve the debugging efficiency.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and in particular relates to a chip interconnect interface tracking and debugging system and chip. Background Technology

[0002] This invention addresses the problem of tracking and debugging high-frequency, high-bandwidth signals within the core interconnect interface IP, improving design flexibility, accuracy of fault location, and density of effective debugging information in the tracking data.

[0003] Existing tracing and debugging methods, such as CN101493847, US7107494, CN103593271, and CN107066707, have the following drawbacks: 1) The tracing and debugging module requires a large internal data cache to store the data captured during the tracing and debugging process, resulting in a significant increase in the module's area; 2) To save internal tracing data cache space, the amount of information carried by the captured tracing data is limited, especially for high-speed interconnect interface IPs that operate at high bandwidth for extended periods. The limited internal information captured by the tracing and debugging module is insufficient for IP internal state recovery and fault analysis; 3) The tracing and debugging module uses a single method to determine the start / end of tracing data, for example... If the exhaustion of internal cache space is used as the marker for ending the tracing, the start time of the tracing data needs to be accurately determined to ensure a good debugging effect. Otherwise, the fault scenario may not have occurred when the internal cache space is exhausted. 4) In order to facilitate the recovery of data waveforms in subsequent debugging, the tracing data often needs to carry system time information. However, this requires the chip to have a clock module. Such clock modules generally operate at low frequencies, so the accuracy of the time information they can provide is limited and cannot meet the debugging needs of the internal signals of high-speed interconnect interface IPs that operate at high frequencies. 5) Although carrying system time information in the tracing data is helpful for the recovery of data waveforms in subsequent debugging, it will also reduce the effective information density tracked by the tracing debugging module.

[0004] In the field of integrated circuit design and verification, with the rapid expansion of chip size and the increase in functional complexity, debugging internal signals has become a core challenge. Traditional debugging methods mainly rely on software simulation and external logic analyzers. The former simulates circuit behavior by modeling, but often cannot fully reproduce timing problems, noise interference, or manufacturing defects in the actual hardware environment; the latter captures signals by connecting chip pins with probes, but it is difficult to access deep internal nodes, resulting in limited observation of complex SoC designs, low debugging efficiency, and high costs.

[0005] To overcome these limitations, embedded trace debugging technology has emerged, with Xilinx's Integrated Logic Analyzer (ILA) serving as a representative approach, providing an efficient solution for monitoring internal signals. The ILA is a customizable IP core that can be seamlessly embedded into FPGA designs, directly capturing and storing selected signals in real time. By configuring multiple probe ports, users can monitor hundreds to thousands of internal signals and set flexible triggering mechanisms, such as trigger signals based on signal level, edge changes, pattern matching, or counter conditions, to precisely control the start and end points of data capture. This avoids blindly recording massive amounts of data, instead activating capture only when events of interest occur, thereby optimizing storage resources and improving analysis efficiency. After data capture, it can be exported to host tools (such as the Vivado Logic Analyzer) via JTAG, USB, or other interfaces for waveform viewing, protocol decoding, and fault diagnosis.

[0006] However, this approach still has the following drawbacks: 1) When generating ILA IP, the amount of data that the user needs to observe during debugging is large, which will occupy a large amount of BRAM resources inside the FPGA; 2) At the same time, ILA IP requires that its clock domain be consistent with the clock domain of the signal inside the module being debugged. When debugging requires capturing and observing a large amount of data, ILA will occupy a large amount of BRAM resources on the FPGA. BRAM resources in FPGA are usually divided into regions and are scattered, which will lead to routing difficulties in the implementation stage, thus affecting the clock frequency that the module being debugged can operate at; 3) ILA is mainly used for tracing and debugging in FPGA design, while chip interconnect interface IP is mainly designed for ASIC and used for cross-chip data transmission. Therefore, it is difficult to maintain the original operating frequency in the ASIC when porting such high-speed interface IP to FPGA. Some faults that can only be exposed at high frequencies may not be reproducible in the FPGA environment; 4) Such interface IP contains PHY (analog circuit) part, and the analog circuit part design cannot be reproduced in FPGA. Therefore, even if the digital circuit part in such high-speed interface IP is ported to FPGA, the faults that can be reproduced and debugged are still limited. Summary of the Invention

[0007] Therefore, the purpose of this invention is to solve the aforementioned problems of the prior art and provide a chip interconnect interface tracking and debugging system coupled to at least one target chip interconnect interface IP. The chip interconnect interface tracking and debugging system includes: a trigger flag generation module, which generates a trigger flag when an internal signal received from the at least one target chip interconnect interface IP reaches a preset trigger condition; an interface data capture module, which captures the internal interface data of the target chip interconnect interface IP in real time, and after receiving the trigger flag, continues to capture a preset number of internal interface data before stopping capture, and is equipped with a timer whose working clock is synchronized with the target chip interconnect interface IP to generate a timestamp for each set of captured valid interface data; a bus master control interface module, which aggregates the data captured by the interface data capture module into data packets and exports them to an external memory in real time, the data packets containing the valid interface data and their corresponding timestamps; and a register module, where the user configures the preset trigger condition and the preset number of data packets through a configuration interface; wherein, the interface data capture module and the target chip interconnect interface IP employ a data flow control mechanism based on credit limits to notify the target chip interconnect interface IP of the amount of data that the interface data capture module can currently receive.

[0008] Furthermore, preferably, in the chip interconnect interface tracking and debugging system of the present invention, the triggering conditions are flexibly configured by the user through the register module, including selecting a specific internal signal as a triggering event and setting the level, edge, pattern matching or count value conditions of the triggering event.

[0009] Furthermore, preferably, in the chip interconnect interface tracking and debugging system of the present invention, the preset amount of data captured by the interface data capture module is configured by the user through the register module, so that the ratio of the data exported by the bus master control interface module to the external memory before the trigger event occurs to the data after the trigger event occurs is adjustable.

[0010] Furthermore, preferably, in the chip interconnect interface tracking and debugging system of the present invention, the timer has a preset bit width and generates an overflow flag when an overflow occurs; the interface data capture module or the bus master control interface module is provided with an overflow counter for counting the overflow flag; when the interface data capture module generates a data packet containing valid interface data and its timestamp, the current value of the overflow counter is concatenated with the data packet to form a composite data packet for final export.

[0011] Furthermore, preferably, in the chip interconnect interface tracking and debugging system of the present invention, an overflow counter is used to reduce the field length of the timestamp information carried by each valid interface data exported by the tracking and debugging system, and additional timestamp information is provided through the overflow data packet.

[0012] Furthermore, preferably, in the chip interconnect interface tracking and debugging system of the present invention, the mechanism for data flow control based on credit limit includes: the interface data capture module sending credit limit update information to the target chip interconnect interface IP, indicating the amount of data it can currently receive; the target chip interconnect interface IP controlling the amount of data it sends to the peer chip interconnect interface IP interconnected with the target chip interconnect interface IP according to the received credit limit update information, ensuring that this amount of data will not exceed the amount of data that the interface data capture module can receive.

[0013] Furthermore, preferably, in the chip interconnect interface tracking and debugging system of the present invention, when the internal interface data includes the receiving side data of the target chip interconnect interface IP, the credit limit update information is transmitted to the sending side of the peer chip interconnect interface IP interconnected with the target chip interconnect interface IP.

[0014] Furthermore, preferably, in the chip interconnect interface tracking and debugging system of the present invention, a data buffer is provided on the data export path of the bus master control interface module. The depth of the data buffer is set according to the difference between the data capture bandwidth of the interface data capture module and the data export bandwidth of the bus master control interface module, and is used in conjunction with the data flow control mechanism based on credit limit to ensure that no data is lost.

[0015] In addition, the present invention provides a chip comprising multiple interconnected chips that integrate any of the above-described chip interconnection interface tracking and debugging systems.

[0016] This invention ensures that when tracing and debugging the internal interface data of a chip interconnect interface IP, the tracing and debugging module does not need a separate large-capacity data cache. Tracing data is exported promptly through the bus master control interface module and stored using the SOC system's storage resources, guaranteeing no data loss throughout the entire tracing and debugging process. Furthermore, it effectively improves the effectiveness of data capture, thereby increasing debugging efficiency, and is not limited to tracing and debugging high-speed interconnect interface IPs. In addition to being applicable to high-speed interconnect interface IPs, it also helps increase the proportion of effective debugging data in the tracing data, further improving debugging efficiency. Attached Figure Description

[0017] Figure 1 This is a schematic diagram illustrating the module relationships of a chip interconnect interface tracking and debugging system according to a preferred embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram illustrating the module relationships of a chip interconnect interface tracking and debugging system according to yet another preferred embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram illustrating a situation where data capture has not yet started in a chip interconnect interface tracking and debugging system according to yet another preferred embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram illustrating a situation in a chip interconnect interface tracking and debugging system according to yet another preferred embodiment of the present invention, where data capture begins but the triggering event does not occur.

[0021] Figure 5 This is a schematic diagram illustrating one scenario of an event triggering in a chip interconnect interface tracking and debugging system according to yet another preferred embodiment of the present invention.

[0022] Figure 6 This is a schematic diagram illustrating yet another scenario in which a triggering event occurs in a chip interconnect interface tracking and debugging system according to yet another preferred embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0024] This invention is specifically designed for tracing and debugging of inter-chip interconnect interface IPs in ASIC designs, and has the following main advantages: 1) The tracing and debugging module does not require a large data buffer space. The captured data is exported externally via the AXI 4.0 Master interface, such as to on-chip SRAM or off-chip DRAM; 2) Since the debugging module does not have a large-capacity data buffer, even if the user needs to observe a large amount of data during debugging, it will not affect the internal timing of the IP being debugged; 3) The credit-based flow control method is used in conjunction with the inter-chip interconnect interface IP to ensure that the tracing and debugging module captures high-bandwidth interface data within the IP without data loss; 4) Users can flexibly select various internal signals provided by the inter-chip interconnect interface IP as trigger events, and continue to capture a certain amount of data after the trigger event occurs before ending data capture. This number can be flexibly configured by the user; 5) The interface data capture module starts capturing data after the tracing and debugging module is started, and continues to capture a certain amount of data after the trigger event occurs before stopping data capture. This number can be flexibly configured by the user. Therefore, the data ultimately exported by the debugging module includes data transmitted through the internal interface of the chip interconnect IP before and after the fault occurred, and the data ratio can be freely configured; 6) The tracing data exported by the tracing debugging module also carries time information, which facilitates subsequent software debugging and recovery of data waveforms, but the SOC system does not need to include a clock module. Furthermore, the proportion of time information in the data exported by the tracing debugging module is compressed to increase the proportion of effective tracing data.

[0025] Figure 1 This is a schematic diagram illustrating the module relationships of a chip interconnect interface tracking and debugging system according to a preferred embodiment of the present invention.

[0026] like Figure 1 As shown in the dashed line, the overall structure of this tracing and debugging design method consists of four main parts: a trigger flag generation module, an interface data capture module, a bus master control interface module, and a register module. The trigger flag generation module receives trigger signals provided by the IP. Users can set appropriate trigger events based on the actual fault scenarios. After a trigger event occurs, the trigger flag generation module generates a trigger flag to notify the interface data capture module to stop data capture. The interface data capture module receives the internal interface signals required for observation provided by the chip interconnect interface IP. After the tracing and debugging module starts, it begins capturing valid data. Data capture stops when a trigger event occurs and the number of captured data reaches the user's expectation. The bus master control interface module exports the valid data captured by the interface data capture module to the on-chip SRAM or off-chip DRAM in a timely manner. The register module provides function configuration. Users can access the register module through the low-speed configuration interface to configure functions and control the start and stop of the tracing and debugging module. The data stored in the on-chip SRAM or off-chip DRAM can be read and analyzed by the CPU or a host computer.

[0027] The interface data capture module does not require a large data cache: It exports the captured valid data promptly through the bus master interface module, thus eliminating the need for a large internal data cache to store all captured data during debugging. If the bandwidth exported through the bus master interface module is less than the bandwidth captured by the interface data capture module, a data buffer needs to be set in the data export path (its depth should be appropriately set based on the difference between the bandwidth exported by the bus master interface module and the bandwidth captured by the interface data capture module). This should be combined with a data flow control mechanism based on credit limits to ensure that the buffer does not overflow and cause data loss.

[0028] A credit-based data flow control mechanism is employed between the tracing and debugging module and the ChipInterconnect interface IP to ensure no data loss. Since the tracing and debugging module primarily captures internal interface data from the ChipInterconnect interface IP, and the bit width of such internal interface data is typically much larger than the system bus bit width, data flow control between the tracing and debugging module and the ChipInterconnect interface IP is necessary to ensure that the valid data captured by the interface data capture module is exported outward through the bus master interface module in a timely manner without data loss. This invention employs a credit-based data flow control mechanism, whereby the tracing and debugging module notifies the ChipInterconnect interface IP in real time of the number of data it can continue to receive (i.e., the credit). The ChipInterconnect interface IP then determines the number of data its internal interface can continue to send based on the credit updated by the tracing and debugging module.

[0029] Figure 2 This is a schematic diagram illustrating the module relationships of a chip interconnect interface tracking and debugging system according to yet another preferred embodiment of the present invention.

[0030] like Figure 2 As shown, the internal interface data that the interface data capture module needs to capture includes the transmitting side Tx and the receiving side Rx. The transmitting side Tx of the interconnect interface IP in core 0 only needs to determine the amount of data it can continue to send based on the Tx credit updated to it by the tracing and debugging module. However, the receiving side Rx of the interconnect interface IP in core 0 receives data from the transmitting side Tx of the interconnect interface IP in core 1. Therefore, the Rx credit provided by the tracing and debugging module to the interconnect interface IP in core 0 needs to be sent to core 1. The transmitting side Tx of the interconnect interface IP in core 1 needs to wait for the Rx credit provided by the interconnect interface IP in core 0 before continuing to send data.

[0031] This credit-based data flow control mechanism for capturing internal interface data of the interconnect interface IP in the tracking and debugging module has the advantage that, when capturing receiver-side Rx data, the transmitter-side Tx of the interconnect interface IP in core 1 is aware of the amount of data that the tracking and debugging module in core 0 can capture from the receiver-side Rx of the interconnect interface IP. Otherwise, if the transmitter-side Tx of the interconnect interface IP in core 1 continuously sends data, data loss will occur due to the bandwidth difference between the data exported by the internal bus master control interface module and the data captured by the interface data capture module.

[0032] Users can flexibly configure the trigger event selected in the trigger flag generation module according to the actual fault scenario to locate the data transmission status of the internal interface of the core interconnect interface IP at the time of the fault: For possible fault scenarios, such as core 0 writing data B to address space A in core 1 through the interconnect interface IP, but the system crashes at this time, the user can set the trigger flag generation module to select the write request address A or data B received by the core interconnect interface IP from the system bus as the trigger event, so as to locate the time of the fault and capture and observe the data transmission status of the internal interface of the core interconnect interface IP before and after the fault.

[0033] The interface data captured before and after a fault in the data exported by the interface data capture module can be flexibly configured: Since the interface data capture module starts capturing data from the start of the tracing and debugging module, and the occurrence of a trigger event serves as a marker for the interface data capture module to stop capturing data. If, during debugging, the trigger event fails to occur due to improper trigger condition settings, the storage space allocated by the user for storing the data exported by the tracing and debugging module may have been filled. In this case, the tracing and debugging module will return to the user-allocated starting address for writing data and continue writing data.

[0034] Figure 3 This is a schematic diagram illustrating a situation where data capture has not yet started in a chip interconnect interface tracking and debugging system according to yet another preferred embodiment of the present invention.

[0035] Figure 4 This is a schematic diagram illustrating a situation in a chip interconnect interface tracking and debugging system according to yet another preferred embodiment of the present invention, where data capture begins but the triggering event does not occur.

[0036] Figure 5 This is a schematic diagram illustrating one scenario of an event triggering in a chip interconnect interface tracking and debugging system according to yet another preferred embodiment of the present invention.

[0037] By setting the amount of data that the interface data capture module needs to continue capturing after a trigger event occurs, users can flexibly configure the proportion of data captured before and after a fault occurs in the data exported by the tracking and debugging module.

[0038] Figure 6 This is a schematic diagram illustrating yet another scenario in which a triggering event occurs in a chip interconnect interface tracking and debugging system according to yet another preferred embodiment of the present invention.

[0039] The data exported by the tracing and debugging module includes time information, but does not require a separate clock module within the system. To facilitate subsequent debugging, the time information in the exported data helps restore the data waveform and facilitates the display of the order in which different interface data appears, thus improving work efficiency. However, because the internal operating frequency of the ChipInterconnect interface IP is relatively high (e.g., 1.5 / 2GHz), the time information provided by traditional system clock modules (typically operating at several hundred MHz) is insufficient to meet the requirement of distinguishing the order of different interface data within the ChipInterconnect interface IP. Therefore, a dedicated timer is set up within the interface data capture module. Its operating frequency is the same as the high-frequency clock frequency inside the ChipInterconnect interface IP, so the accuracy of the time information it provides is sufficient for debugging needs. When the interface data capture module captures valid data, it exports a valid data packet containing the time information provided by the timer. The data packet format is as follows: To minimize the proportion of time information in the data exported by the tracing and debugging module, the bit width of this timer can be set as small as possible. However, this introduces another problem: when the amount of data to be captured is large or the triggering event is delayed, resulting in excessive debugging time, the timer may overflow due to the small bit width. In this case, the tracing and debugging module needs to provide a timer overflow flag. This flag will be used to compose the subsequent timer overflow data packet (8-bit, minimizing the proportion of the timer overflow flag in the data exported by the tracing and debugging module). When the software analyzes the data, if it identifies this timer overflow data packet, it can be equated with the actual time information corresponding to the time information carried in the subsequent valid interface data packets. Simultaneously, to maximize the utilization of system bus bandwidth, the timer overflow flag data packet will be concatenated and exported when the next set of valid interface data packets is exported. The concatenation format is as follows: In actual debugging scenarios, there may be situations where there is no data transmission within the Core Interconnect interface IP for extended periods. In such cases, the timer overflows multiple times but cannot be concatenated with valid data packets for export. This results in continuous timer overflow flag data packets appearing in the data exported by the tracing and debugging module, reducing the proportion of valid data. Therefore, a timer overflow flag counter (7-bit) is set in the bus master interface module, incrementing by 1 upon receiving a timer overflow flag from the interface data capture module. When the interface data capture module receives a valid interface data packet, this counter value is concatenated with the valid interface data packet to form the timer overflow flag data packet for export. The format of the timer overflow flag data packet is as follows: In the preferred embodiments of the present invention described above, at least the following features are present: 1) This tracing and debugging design method supports a credit-based data flow control mechanism. When working with the ChipInterconnect interface IP, it ensures that when tracing and debugging the internal interface data of the ChipInterconnect interface IP, the tracing and debugging module does not require a separate large-capacity data cache. Tracing data is exported promptly through the bus master interface and stored using the SOC system's storage resources. Simultaneously, it ensures no data loss during the entire tracing and debugging process. This key point is applicable to the tracing and debugging of high-speed interconnect interface IPs, primarily used for capturing and observing the internal Tx and Rx interface data of the IP.

[0040] 2) This tracing and debugging design method allows users to freely choose the location and size of the tracing data storage, and flexibly configure the ratio of tracing data before and after a fault by using "loop writing" and setting the number of data to continue capturing after a trigger event occurs. Since the selection of trigger events and the setting of conditions may not be able to accurately locate the moment of fault occurrence, this key point can effectively improve the effectiveness of data capture, thereby improving debugging efficiency, and is not only applicable to tracing and debugging of high-speed interconnect interface IPs.

[0041] 3) The mechanism for generating time information carried in the trace data, the mechanism for handling timer overflows, and the subsequent data export packaging mechanism in this tracing and debugging design method can maximize the proportion of valid data in the data exported by the tracing and debugging module. This key point is not only applicable to the tracing and debugging of high-speed interconnect interface IPs, but also helps to increase the proportion of valid debugging data in the trace data, thereby improving debugging efficiency.

[0042] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0043] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0044] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0045] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A chip interconnect interface tracking and debugging system, coupled to at least one target chip interconnect interface IP, characterized in that, The chip interconnect interface tracking and debugging system includes: The trigger flag generation module determines that when the internal signal received from the at least one target chip interconnect interface IP reaches a preset trigger condition, it generates a trigger flag. The interface data capture module captures the internal interface data of the target chip interconnect interface IP in real time, and stops capturing after receiving the trigger flag after capturing a preset number of internal interface data. It is equipped with a timer whose working clock is synchronized with the target chip interconnect interface IP to generate a timestamp for each set of valid interface data captured. The bus master control interface module collects the data captured by the interface data capture module into a data packet and exports it to an external storage in real time. The data packet contains the valid interface data and its corresponding timestamp. The register module allows users to configure the preset trigger conditions and the preset quantity through a configuration interface. Specifically, the interface data capture module and the target chip interconnect interface IP employ a credit-based data flow control mechanism to notify the target chip interconnect interface IP of the amount of data that the interface data capture module can currently receive. The mechanism for data flow control based on credit limits includes: The interface data capture module sends credit update information to the target core interconnect interface IP, indicating the amount of data it can currently receive; The target kernel interconnect interface IP controls the amount of data it sends to the peer kernel interconnect interface IP interconnected with the target kernel interconnect interface IP based on the received credit limit update information, ensuring that this amount of data does not exceed the amount of data that the interface data capture module can receive.

2. The corelet interconnect interface trace debug system of claim 1, wherein, The triggering conditions are flexibly configured by the user through the register module, including selecting a specific internal signal as a triggering event and setting the level, edge, pattern matching, or count value conditions of the triggering event to generate a trigger flag.

3. The corelet interconnect interface trace debug system of claim 1, wherein, The preset amount of data captured by the interface data capture module is configured by the user through the register module, so that the ratio of data exported by the bus master control interface module to the external memory before and after the trigger event is adjustable.

4. The chip interconnect interface tracking and debugging system according to claim 1, characterized in that, The timer has a preset bit width and generates an overflow flag when an overflow occurs; The interface data capture module or the bus master control interface module is equipped with an overflow counter for counting the overflow flags. When the interface data capture module generates a data packet containing valid interface data and its timestamp, it concatenates the current overflow counter value with the data packet to form a composite data packet for final export.

5. The corelet interconnect interface trace debug system of claim 4, wherein, Use an overflow counter to reduce the field length of the timestamp information carried by each valid interface data exported by this tracing and debugging system, and provide additional timestamp information through overflow packets.

6. The corelet interconnect interface trace debug system of claim 1, wherein, When the internal interface data includes the receiving side data of the target kernel interconnect interface IP, the credit limit update information is transmitted to the sending side of the peer kernel interconnect interface IP interconnected with the target kernel interconnect interface IP.

7. The chip interconnect interface tracking and debugging system according to claim 1, characterized in that, A data buffer is provided on the data export path of the bus master control interface module. The depth of the data buffer is set according to the difference between the data capture bandwidth of the interface data capture module and the data export bandwidth of the bus master control interface module. It works in conjunction with the data flow control mechanism based on credit limit to ensure that no data is lost.

8. A chip comprising a plurality of interconnected chips and integrating a chip interconnect interface tracking and debugging system as described in any one of claims 1-7.

Images