指令调度器的验证方法、电子设备和存储介质
By inserting delayed instructions into the basic instruction sequence of the instruction scheduler and configuring differentiated delay parameters, a multi-issue interleaved combination is generated, which solves the problems of low efficiency and insufficient coverage in the prior art and achieves efficient and accurate instruction scheduler verification.
CN122064597BActive Publication Date: 2026-07-17SHANGHAI BIREN TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2026-04-03
- Publication Date
- 2026-07-17
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Figure CN122064597B_ABST
Abstract
本发明涉及人工智能芯片技术领域，提供一种指令调度器的验证方法、电子设备和存储介质，包括：获取待测的基础指令序列，在其中插入延迟指令并使用循环指令进行多次循环，生成目标指令序列；针对不同线程束的延迟指令配置差异化的延迟参数，并输入至待验证的指令调度器；在处理指令序列的过程中，基于延迟参数和循环指令，使不同线程束的指令流产生交错，在发射端生成多发射指令交错组合以进行验证。本发明通过在基础指令序列中引入参数化的延迟指令与循环执行机制，能够动态制造指令流交错，从而实现了在不增加代码复杂度的情况下，自动且准确地生成大量多发射并发冲突测试场景，具有验证效率高、场景覆盖率全面且代码易维护的优点。
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