Input data preformatting caching method and apparatus, computer device, storage medium, and program product

Abstract

The present disclosure provides an input data preformatting caching method, device, equipment, medium and program product, relating to the technical field of computer and data processing, and the implementation scheme is: obtaining input data, output ports, data formats corresponding to the input data and the output ports; based on whether the data formats corresponding to the output ports are the same, classifying the output ports into output port groups; dividing a register array into a number of partitions equal to the number of the output port groups; based on the correspondence between each partition and the output port group, one-to-one mapping each output port to a physical location of the corresponding partition; converting the input data into sub-data blocks with the same data format as the data format corresponding to the output ports; and based on the data format corresponding to the output ports, writing the sub-data blocks with the same data format into the physical location of the corresponding partition, which can significantly reduce the hardware wiring complexity and timing convergence difficulty, and greatly improve the data reading efficiency and hardware running stability.

Description

Technical Field

[0001] This disclosure relates to the fields of computer and data processing technology, particularly to the fields of data storage and data formatting, and especially to an input data pre-formatting caching method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Technology

[0002] In hardware architectures such as neural network accelerators, sparse computing processors, and high-bandwidth memory interfaces, storage architecture and multi-port parallel output capabilities have become one of the core bottlenecks determining system throughput, timing convergence efficiency, and overall energy efficiency. As application scenarios continuously increase the demands for data bit width, the number of output ports, and real-time processing, data paths become increasingly complex, significantly increasing the wiring complexity of storage arrays. This can lead to problems such as excessive critical path latency, global wiring congestion, and bloated hierarchical control logic, further limiting efficiency improvements. Simultaneously, complex control and multiplexing also incur additional power consumption, resulting in a decrease in the overall system energy efficiency ratio, making it difficult to meet the comprehensive requirements of high throughput, low latency, and low power consumption. Summary of the Invention

[0003] This disclosure provides a method, apparatus, computer device, computer-readable storage medium, and computer program product for pre-formatting input data caching.

[0004] According to one aspect of this disclosure, an input data pre-formatting caching method is provided, comprising: acquiring input data, at least one output port, a data format of the input data, and a data format corresponding to the at least one output port, the data format including bit width and dimension arrangement information, the dimension arrangement information including first sub-information for characterizing the dimensional arrangement of the data format; classifying the at least one output port into at least one output port group based on whether the bit width and first sub-information corresponding to the at least one output port are the same, wherein the bit width and first sub-information corresponding to all output ports in each output port group are the same; dividing a register array used for caching input data into a number of partitions equal to the number of output port groups based on the number of output port groups, and each partition corresponding to one output port group; mapping each output port in the output port group to the physical location of the corresponding partition based on the correspondence between each partition in the register array and the output port group; converting the input data into sub-data blocks with the same bit width and first sub-information as the bit width and first sub-information corresponding to the output port; and writing the sub-data blocks with the same bit width and first sub-information as the output port into the physical location of the corresponding partition with the one-to-one mapping relationship.

[0005] In some embodiments, the dimensional arrangement information of the data format further includes second sub-information for characterizing the dimensional size of each dimension in the data format.

[0006] In some embodiments, based on the bit width and first sub-information corresponding to the output port, sub-data blocks with the same bit width and first sub-information are written into the physical location of the corresponding partition that has a one-to-one mapping relationship with the output port. This includes: in response to the fact that the dimension size of any dimension in the second sub-information of the sub-data block is greater than the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition, the input data is split along that dimension based on the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition.

[0007] In some embodiments, based on the bit width and first sub-information corresponding to the output port, sub-data blocks with the same bit width and first sub-information are written into the physical location of the corresponding partition that has a one-to-one mapping relationship with the output port. This includes: in response to the fact that the dimension size of any dimension in the second sub-information of the sub-data block is less than the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition, the input data is merged in that dimension based on the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition.

[0008] In some embodiments, the method further includes: in response to a read request for at least one output port, reading sub-data blocks in parallel from the physical location of the partition based on a one-to-one mapping between the at least one output port and the corresponding physical location of the partition in the register array.

[0009] In some embodiments, the register array used to buffer input data is a multidimensional register array.

[0010] According to another aspect of this disclosure, an input data pre-formatting caching device is provided, comprising: an information acquisition module configured to acquire input data, at least one output port, a data format of the input data, and a data format corresponding to the at least one output port, the data format including bit width and dimension arrangement information, the dimension arrangement information including first sub-information for characterizing the dimension arrangement of the data format; an output port classification module configured to classify the at least one output port into at least one output port group based on whether the bit width and the first sub-information corresponding to the at least one output port are the same, wherein the bit width and the first sub-information corresponding to all output ports in each output port group are the same; and a partitioning module configured to partition based on the output port The number of port groups divides the register array used for buffering input data into the same number of partitions as the number of output port groups, with each partition corresponding to one output port group; the mapping module is configured to map each output port in the output port group to the physical location of the corresponding partition based on the correspondence between each partition in the register array and the output port group; the conversion module is configured to convert the input data into sub-data blocks with the same bit width and first sub-information as the output port; and the writing module is configured to write the sub-data blocks with the same bit width and first sub-information as the output port to the physical location of the corresponding partition with a one-to-one mapping relationship.

[0011] According to another aspect of this disclosure, a computer device is provided, comprising: a processor; and a memory having a computer program stored thereon, wherein when executed by the processor, the computer program causes the processor to perform the methods provided above in this disclosure.

[0012] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0013] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0014] According to one or more embodiments of this disclosure, hardware wiring complexity and timing convergence difficulty can be significantly reduced, while greatly improving data reading efficiency and hardware operation stability while ensuring bandwidth and format conversion functions.

[0015] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0016] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of this disclosure. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0017] Figure 1 This is a flowchart illustrating an input data pre-formatting caching method according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram illustrating output port grouping and register partitioning according to embodiments of the present disclosure; Figure 3 This is a block diagram illustrating an input data preformatting cache apparatus according to an embodiment of the present disclosure; Figure 4 An example computer device is shown in which any of the embodiments described herein may be implemented. Detailed Implementation

[0018] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0019] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0020] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.

[0021] In related technologies, existing multi-port data output hardware architectures mostly use register-type multidimensional arrays as cache units, coupled with dedicated data selection paths and rearrangement control circuits, to complete the parallel data distribution task across multiple ports. During the data writing process to the storage unit, data is typically arranged in a linear address increment order, or according to the timing requirements of external control instructions. The data reading phase relies on modules such as multiplexers, data reconstruction logic, and format conversion circuits to filter and convert data into the target output format based on the real-time data requirements of each output port.

[0022] While this traditional architecture can initially meet the basic requirements of multi-port parallel access, once the number of output ports increases and the amount of data transmitted in a single transmission increases significantly, the supporting control circuits and multiplexing links will increase exponentially, leading to a sharp increase in the overall circuit complexity. At the same time, the physical connection paths between the buffer unit and each output port are messy and intertwined, and the signal transmission paths are inconsistent. This not only increases the difficulty of circuit routing but also increases signal delay and power consumption, bringing many unavoidable adverse effects to the back-end circuit design, hardware architecture implementation, and timing convergence.

[0023] Therefore, embodiments of this disclosure provide an input data pre-formatting caching method, which can significantly reduce hardware wiring complexity and timing convergence difficulty, and greatly improve data reading efficiency and hardware operation stability.

[0024] Figure 1 This is a flowchart illustrating an input data preformatting caching method according to an embodiment of the present disclosure.

[0025] like Figure 1 As shown, the input data preformatting caching method includes steps S101, S102, S103, S104, S105, and S106.

[0026] In step S101, input data, at least one output port, the data format of the input data, and the data format corresponding to at least one output port are obtained. The data format includes bit width and dimension arrangement information. The dimension arrangement information includes first sub-information used to characterize the dimension arrangement of the data format.

[0027] In the example, input data can refer to the raw data to be stored in the register array. Data format defines the organization of the data and can include bit width and dimensional arrangement information. Bit width refers to the number of binary bits occupied by a single data set, i.e., the bit width during data transmission. Dimensional arrangement information describes the structural form of the data in multidimensional space. The first sub-information in the dimensional arrangement information can be a specific limitation on this structural form, i.e., the distribution and combination of the data in multidimensional space, specifically the number and order of different dimensions of the data. For example, if the bit width of input data is 8 bits, the first sub-information in its dimensional arrangement information indicates that the data adopts a three-dimensional arrangement; if the bit width of the data format corresponding to an output port is 16 bits, the first sub-information in its dimensional arrangement information indicates that the data adopts a four-dimensional arrangement.

[0028] In step S102, based on whether the bit width and the first sub-information corresponding to at least one output port are the same, at least one output port is classified into at least one output port group, and the bit width and the first sub-information corresponding to all output ports in each output port group are the same.

[0029] In the example, since output ports with the same bit width and dimensional arrangement have consistent requirements for data read bit width and data concatenation method, these output ports can be grouped into the same group. This ensures that all output ports within the same group have the same read control logic, thereby avoiding the need to configure addressing rules and data paths independently for individual output ports and fundamentally reducing the redundancy of control logic and the complexity of circuit design. Specifically, this can be achieved by reading the bit width and first sub-information of each output port one by one, and then grouping output ports with the same bit width and first sub-information into the same output port group, so that the output ports within each group have unified data access and output characteristics.

[0030] In step S103, the register array used to buffer input data is divided into the same number of partitions as the number of output port groups, based on the number of output port groups, and each partition corresponds to one output port group.

[0031] In step S104, based on the correspondence between each partition in the register array and the output port group, each output port in the output port group is mapped to the physical location of the corresponding partition.

[0032] In the example, the register array can be used to temporarily store input data to be output. Partitioning can be a physical division of the register array according to the number of output port groups, splitting it into independent storage areas to ensure that each group of output ports corresponds to an independent cache area. One-to-one mapping can establish a one-to-one correspondence between output ports and their corresponding physical locations within a partition. That is, each output port within the same output port group is bound to a fixed physical storage location within its corresponding partition, ensuring that each output port can only access its own corresponding physical location, thus avoiding access conflicts or data overlap with other output ports and improving output efficiency. This mapping relationship can be implemented, for example, through backend hardware routing.

[0033] Therefore, by partitioning registers according to the number of output port groups and establishing a one-to-one mapping, a one-to-one correspondence between cache resources and output ports can be achieved, eliminating data selection logic and access conflicts at the output end. Simultaneously, it fixes the data path, makes wiring more organized, effectively reduces back-end wiring congestion, shortens signal transmission paths, and improves timing convergence. While reducing circuit area and power consumption, it ensures stable and efficient data output.

[0034] Figure 2 This is a schematic diagram illustrating output port grouping and register partitioning according to an embodiment of the present disclosure.

[0035] like Figure 2 As shown, in some examples, it can be like... Figure 2 The seven output ports shown are categorized according to their bit width and dimension, forming three output port groups. Output port group E can include two output ports 201; output port group F can include three output ports 202; and output port group G can include two output ports 203. Thus, the register array 210 can also be divided into the same number of partitions based on these three output port groups: partition e, partition f, and partition g. Furthermore, each partition corresponds to a set of output port groups. In... Figure 2 In the example shown, output port group E is bound to partition e, output port group F is bound to partition f, and output port group G is bound to partition g.

[0036] In step S105, the input data is converted into a sub-data block with the same bit width and first sub-information as the output port.

[0037] In step S106, based on the bit width and first sub-information corresponding to the output port, sub-data blocks with the same bit width and first sub-information are written into the physical location of the corresponding partition that has a one-to-one mapping relationship with the output port.

[0038] In the example, converting input data into sub-data blocks ensures that the bit width and dimensional arrangement of these sub-data blocks match the requirements of the corresponding output port, guaranteeing that the data can be directly read by the port after writing. Writing to the corresponding partition's physical location based on the mapping relationship allows the established correspondence between output ports and partitions to directly store format-matching sub-data blocks into the bound storage area, preventing data of different formats and from different output ports from being stored together, thus avoiding dynamic addressing or data relocation. This process completes all format conversion and storage during the input stage, eliminating the need for data relocation, selection, or rearrangement during the output stage. This not only simplifies the data path and reduces backend wiring complexity and timing convergence difficulty but also improves data reading stability and bandwidth efficiency.

[0039] Therefore, by classifying output ports, partitioning register arrays, and mapping them in a targeted manner, the data selection and conversion logic of output ports can be significantly reduced, hardware routing complexity and timing convergence difficulty can be lowered, while access conflicts can be avoided, and data read bandwidth and stability can be improved. Pre-formatting data during the write phase can effectively reduce circuit power consumption and ensure efficient and reliable input / output bandwidth and format conversion.

[0040] The following describes in further detail various aspects of the input data preformatting caching method according to embodiments of the present disclosure.

[0041] In some embodiments, the dimensional arrangement information of the data format further includes second sub-information for characterizing the dimensional size of each dimension in the data format.

[0042] In the example, dimensional arrangement information can be used to comprehensively define the structural form of data in a multidimensional structure. The first sub-information clarifies the number and order of the different dimensions of the data, while the second sub-information characterizes the specific size of each dimension under this data format. Only by combining the two can the multidimensional structural form of the data be fully defined, providing a complete basis for data splitting, partitioning, and write positioning. That is, only by combining the dimension size represented by the second sub-information can the size of the sub-data block, the capacity of the register partition, and the mapping boundary between the output port and the physical location be accurately calculated, ensuring the matching of the size of pre-formatted writes and output reads.

[0043] In some embodiments, based on the bit width and first sub-information corresponding to the output port, writing sub-data blocks with the same bit width and first sub-information into the physical location of the corresponding partition that has a one-to-one mapping relationship with the output port may include: in response to the fact that the dimension size of any dimension in the second sub-information of the sub-data block is greater than the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition, splitting the input data in terms of dimension based on the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition.

[0044] In the example, the sum of the dimensions of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition represents the maximum effective data size that the partition can support for storage. When the size of a certain dimension of a sub-data block exceeds the upper limit that the partition can bear, direct writing will cause storage out-of-bounds errors, data corruption, or the output port being unable to read completely. Therefore, it is necessary to split the input data along that dimension using the sum of the dimensions of the partition's output port group as the standard. For each dimension of the sub-data block, the size of the sub-data block can be compared with the corresponding dimension size of the corresponding partition's output port group. Once any dimension is detected to exceed the carrying limit, the input data can be divided into multiple sub-data blocks that meet the size requirements along that dimension, using the total carrying size of the corresponding dimension of the partition as the unit, and then written one by one to the mapped physical location, so that each split sub-data block can match the dimension specifications of the partition and the output port. For example, if the size of a certain dimension of the sub-data block is 64, and the sum of that dimension of the corresponding partition's output port group is 16, the input data can be divided into 4 equal parts along that dimension, so that the size of each part is adapted to the partition's carrying capacity before writing.

[0045] Therefore, by dimensionally splitting the oversized sub-data blocks according to the sum of the dimensions of the partition output port groups, it can be ensured that the size of the written data strictly matches the hardware specifications of the register partition and the output port, avoiding storage out-of-bounds errors and data read anomalies. Since no additional size trimming or reorganization is required at the output end, it can also simplify the data processing logic and improve the stability and timing convergence of cache reads and writes.

[0046] In some embodiments, based on the bit width and first sub-information corresponding to the output port, writing sub-data blocks with the same bit width and first sub-information into the physical location of the corresponding partition that has a one-to-one mapping relationship with the output port may include: in response to the fact that the dimension size of any dimension in the second sub-information of the sub-data block is less than the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition, merging the input data in terms of dimension based on the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition.

[0047] Similarly, in the example, when the size of any dimension of a sub-data block is smaller than the total size of the corresponding dimension of the partition's output port group, direct writing may result in wasted register space and scattered data distribution, leading to reduced read efficiency at the output end. Therefore, the total size of the dimensions of the partition's output port group can be used as the target size to perform merging processing on the input data in the corresponding dimensions. For each dimension of the sub-data block, the size of the sub-data block can be compared with the dimension size of the corresponding partition's output port group. When it is determined that the size of a certain dimension of the sub-data block is insufficient, the total size of the corresponding dimension of the partition can be used as the merging basis. Multiple small-sized sub-data blocks can be integrated in that dimension to form a complete data unit that matches the total size of the partition's dimensions. This unit is then written to the physical location mapped one-to-one with the output port, aligning the storage structure with the dimension specifications of the output port. This eliminates the need for data splicing or padding during the output stage. For example, if the size of a certain dimension of the sub-data block is 16, and the total size of that dimension of the corresponding partition's output port group is 64, then four identical sub-data blocks can be merged into a complete data block of the same size in that dimension before being written to the corresponding partition.

[0048] Therefore, by merging sub-data blocks with insufficient size according to the sum of the dimensions of the partition output port groups, the storage space of the register partition can be fully utilized, avoiding the decrease in access efficiency caused by fragmented data storage. This further reduces the logic of data splicing and format adjustment at the output end, improving the continuity of cache read and write operations and the stability of hardware operation.

[0049] In some embodiments, the input data preformatted cache may further include: in response to a read request for at least one output port, reading sub-data blocks in parallel from the physical location of the partition based on a one-to-one mapping between the at least one output port and the corresponding physical location of the partition in the register array.

[0050] In the example, since the output ports have been grouped, the register array partitioned, and the sub-data blocks written into physical locations that form a fixed and unique mapping relationship with each output port in the above steps, when a read request is received, there is no need to re-parse the data format, query the storage location, or reconstruct the data structure. It is only necessary to directly locate the physical location of the partition in the register array bound to that output port according to the pre-established correspondence. To further improve data output efficiency, read requests from multiple output ports can be responded to simultaneously, that is, sub-data blocks can be read in parallel from their respective corresponding partition physical locations. Data reading between each output port is independent and does not interfere with each other.

[0051] Therefore, by reading the sub-data blocks corresponding to each output port in parallel based on a one-to-one mapping relationship, the read control logic can be greatly simplified, eliminating the processes of data addressing, format verification, and dimension reorganization, effectively reducing read latency. At the same time, the parallel read method can fully utilize the bandwidth advantage of the register array, improving the overall data output efficiency and ensuring the stability and timing performance of the output data.

[0052] In some embodiments, the register array used to buffer input data is a multidimensional register array.

[0053] In the example, a multidimensional register array is preferably used for caching input data. Unlike one-dimensional registers, which can only store data sequentially according to linear addresses, multidimensional register arrays can arrange data spatially according to the actual dimensional structure of the data. This aligns with the data pre-formatting logic in this patent, which is based on bit width, dimensional arrangement information, and dimensional size, ensuring that the physical structure of the registers remains consistent with the logical structure of the data. Furthermore, when using a multidimensional register array, there is no need to flatten multidimensional data into a one-dimensional form for storage, avoiding the additional logical overhead and timing losses caused by address translation and dimensional reconstruction.

[0054] The following section will take input data preformatting caching as an example to specifically describe the data conversion process in the input data preformatting caching method according to embodiments of this disclosure.

[0055] In some examples, if the input data is a three-dimensional structure (a×b×c), the output format is a four-dimensional structure (A×B×C×D), and the maximum output format size supported by the output port is 2×64×64×16. Simultaneously, the output data format follows preset hardware constraints: the output dimension C supports a value of 64 only when the input dimension b is 64; in other input cases, the output dimension C is fixed at 16 (i.e., dimension C does not support a value of 32). Under these conditions, it can be deduced that: A can take values ​​of 1 and 2, B can take values ​​of 16, 32, and 64, and D is fixed at 16.

[0056] In the above example, the data transformation can be analyzed using a table. Table 1 shows an example of input data transformation according to an embodiment of this disclosure. As shown in Table 1, the leftmost column shows the data formats that the output port can support under the above-mentioned conditions; the middle column shows some given input data; and the rightmost column shows the sub-data blocks after each input data transformation.

[0057]

Table 1

[0058] In the example, as shown in Table 1, taking the input data a×b×c=64×16×8 as an example, 64 corresponds to the dimension a of the input data, 16 corresponds to the dimension b of the input data, and 8 corresponds to the bit width of the input data. The maximum output format size that the output port can support is 2×64×64×16. According to the preset constraints, the output dimension C can only support a size of 64 when the size of dimension b in the input data is 64. In this case, dimension b=16 in the input data, which does not meet the constraint condition of b=64. Therefore, the size of the output dimension C is fixed at 16. Under this premise, dimension b=16 and output dimension C=16 are perfectly matched, and there is no need to perform splitting or merging operations on this dimension. Therefore, in the multidimensional register array, a valid write format of 1×(4×16)×(1×16)×8 can be formed. This format matches the input data 64×16×8 and the corresponding output port data format in terms of bit width, dimension arrangement information, and dimension size.

[0059] In the example, as shown in Table 1, taking the input data a×b×c=16×64×8 as an example, 16 corresponds to the dimension a of the input data, 64 corresponds to the dimension b of the input data, and 8 corresponds to the bit width of the input data. Similarly, according to the preset constraints, dimension b=64 in this input data, satisfying the constraint condition b=64, therefore the size of the output dimension C is 64. Under this premise, since a=16, in the multidimensional register array, a merging operation can be performed based on the size of dimension a, that is, by writing sub-data blocks in the format of 1×(1×16)×(4×16)×8 four times, 1×(4×16)×(4×16)×8 written data can be obtained. Since the maximum output format size that the output port can support is 2×64×64×16, 1×(1×16)×(4×16)×8 can also be written eight times to obtain 2×(4×16)×(4×16)×8. Both of these data writing formats match the data format of the corresponding output port in terms of bit width, dimension arrangement information, and dimension size.

[0060] Furthermore, for example, in the case of input data a×b×c=64×16×8, if we further consider that the output port can support a maximum output format size of 2×64×64×16, i.e., 2×(4×16)×(4×16)×16, then based on the dimensional ratio between the input data and the maximum output format size, we can also write two sub-data blocks with a format of 1×(4×16)×(1×16)×8, resulting in 2×(4×16)×(1×16)×8. Here, since dimension C only supports 64 or 16, there is no need to further split or merge along this dimension.

[0061] According to embodiments of this disclosure, an input data preformatting caching device is also provided.

[0062] Figure 3 This is a block diagram illustrating an input data preformatting cache apparatus according to an embodiment of the present disclosure.

[0063] like Figure 3 As shown, in some embodiments, the input data preformatting cache device 300 includes an information acquisition module 301, an output port classification module 302, a partitioning module 303, a mapping module 304, a conversion module 305, and a writing module 306.

[0064] The information acquisition module 301 is configured to acquire input data, at least one output port, the data format of the input data, and the data format corresponding to the at least one output port. The data format includes bit width and dimension arrangement information. The dimension arrangement information includes first sub-information used to characterize the dimension arrangement of the data format.

[0065] The output port classification module 302 is configured to classify the at least one output port into at least one output port group based on whether the bit width and first sub-information corresponding to the at least one output port are the same, wherein the bit width and first sub-information corresponding to all output ports in each output port group are the same.

[0066] The partitioning module 303 is configured to divide the register array used for buffering input data into a number of partitions based on the number of output port groups, with each partition corresponding to one output port group.

[0067] The mapping module 304 is configured to map each output port in the output port group to the physical location of the corresponding partition based on the correspondence between each partition in the register array and the output port group.

[0068] The conversion module 305 is configured to convert the input data into a sub-data block with the same bit width and first sub-information as the output port.

[0069] The writing module 306 is configured to write sub-data blocks with the same bit width and first sub-information to the physical location of the corresponding partition that has a one-to-one mapping relationship with the output port, based on the bit width and first sub-information corresponding to the output port.

[0070] The operations of the aforementioned information acquisition module 301, output port classification module 302, partitioning module 303, mapping module 304, conversion module 305, and writing module 306 can be combined. Figure 1 The operations of steps S101-S106 are the same, so the details of each aspect will not be repeated here.

[0071] In some embodiments, the writing module 306 further includes a splitting module 3061, configured to: in response to the fact that the dimension size of any dimension in the second sub-information of the sub-data block is greater than the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition, split the input data in that dimension based on the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition.

[0072] In some embodiments, the writing module 306 further includes a merging module 3062, configured to: in response to the fact that the dimension size of any dimension in the second sub-information of the sub-data block is less than the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition, merge the input data in that dimension based on the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition.

[0073] In some embodiments, the input data preformatted cache device 300 further includes a parallel read module 307 configured to: in response to a read request for at least one output port, read sub-data blocks in parallel from the physical location of the partition based on a one-to-one mapping between the at least one output port and the corresponding physical location of the partition in the register array.

[0074] According to one aspect of this disclosure, a computer device is also provided, including a memory, a processor, and a computer program stored in the memory. The processor is configured to execute the computer program to implement the steps of any of the method embodiments described above.

[0075] According to one aspect of this disclosure, a non-transitory computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the method embodiments described above.

[0076] According to one aspect of this disclosure, a computer program product is also provided, which includes a computer program that, when executed by a processor, implements the steps of any of the method embodiments described above.

[0077] Figure 4 An example computer device 400 is shown in which any of the embodiments described herein may be implemented. Computer device 400 may be used to implement one or more components of the systems and methods described above. Computer device 400 may include a bus 402 or other communication mechanism for communicating information, and one or more processors 404 coupled to the bus 402 for processing information. Processor 404 may be, for example, one or more general-purpose microprocessors.

[0078] Computer device 400 may also include main memory 406, such as random access memory (RAM), cache, and / or other dynamic storage devices, coupled to bus 402, for storing information and instructions to be executed by processor 404. Main memory 406 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by processor 404. Such instructions, when stored in a storage medium accessible to processor 404, can make computer device 400 a special-purpose machine customized to perform the operations specified in the instructions. Main memory 406 may include non-volatile media and / or volatile media. Non-volatile media may include, for example, optical discs or magnetic disks. Volatile media may include dynamic memory. Common media formats may include, for example, floppy disks, collapsible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage media, CD-ROMs (read-only optical disc drives), any other optical data storage media, any physical media with a perforated arrangement, RAM (random access memory), DRAM (dynamic random access memory), PROM (programmable read-only memory) and EPROM (erasable programmable read-only memory), FLASH-EPROM (fast erase programmable read-only memory), NVRAM (non-volatile random access memory), any other memory chips or tape cartridges, or network versions of the above.

[0079] Computer device 400 may implement the techniques described herein using custom hardwired logic, one or more ASICs (Application-Specific Integrated Circuits) or FPGAs (Field-Programmable Gate Arrays), firmware, and / or program logic, which, when combined with computer device 400, enable computer device 400 to become a special-purpose machine or to be programmed therein. According to one embodiment, the techniques described herein are executed by computer device 400 in response to processor 404 executing one or more sequences of one or more instructions contained in main memory 406. Such instructions may be read into main memory 406 from another storage medium, such as storage device 408. Executing the sequence of instructions contained in main memory 406 causes processor 404 to perform the processing steps described herein. For example, the processes / methods disclosed herein may be implemented by computer program instructions stored in main memory 406. When these instructions are executed by processor 404, they may perform the steps shown in the corresponding figures and as described above. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions.

[0080] Computer device 400 also includes a network interface 410 coupled to bus 402. Network interface 410 can provide bidirectional data communication coupled to one or more network links connected to one or more networks. As another example, network interface 410 can be a local area network (LAN) card to provide data communication connectivity with a compatible LAN (or a WAN component communicating with a WAN (wide area network)). Wireless links can also be implemented.

[0081] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or the processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or the processor-implemented engine may be distributed across many geographic locations.

[0082] Each process, method, and algorithm described in the preceding sections can be embodied in a code module executed by one or more computer systems or computer processors including computer hardware, and can be fully or partially automated by them. These processes and algorithms can be implemented, in part or in whole, in a specific application circuit.

[0083] When the functions disclosed herein are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the prior art, can be embodied in the form of a software product. This software product can be stored in a storage medium and includes instructions to cause a computer device (which may be a personal computer, server, network device, etc.) to perform all or part of the steps of the methods described in the embodiments of this application. The storage medium may include a flash drive, a portable hard drive, ROM, RAM, a magnetic disk, an optical disk, another medium suitable for storing program code, or any combination thereof.

[0084] The embodiments disclosed herein can be implemented via a cloud platform, server, or group of servers that interact with a client. The client can be a terminal device or a client registered by a user on the platform, wherein the terminal device can be a mobile terminal, a personal computer (PC), or any device that can install platform applications.

[0085] The various features and processes described above can be used independently or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Furthermore, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and associated blocks or states may be executed in other suitable orders. For example, described blocks or states may be executed in a non-specifically disclosed order, or multiple blocks or states may be combined in a single block or state. Exemplary blocks or states may be executed serially, in parallel, or otherwise. Blocks or states may be added to or removed from the disclosed exemplary embodiments. The exemplary systems and components described herein may be configured differently from those described. For example, elements may be added, removed, or rearranged compared to the disclosed exemplary embodiments.

[0086] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. An algorithm may consist of program code or instructions stored in memory (such as the non-transitory computer-readable storage medium described above). Such an algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not be explicitly programmed into the computer to perform the function, but may learn from training data to obtain a predictive model for performing that function.

[0087] The various operations of the exemplary methods described herein can be performed at least in part by one or more processors, which are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, such processors can constitute the engine of a processor implementation whose operation is to perform one or more of the operations or functions described herein.

[0088] Similarly, the methods described herein can be implemented at least partially by a processor, where a specific processor or one or more processors are examples of hardware. For example, at least some operations of the methods can be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors can also run in a “cloud computing” environment or as “Software as a Service” (SaaS) to support the execution of the relevant operations. For example, at least some operations can be performed by a group of computers (as an example of a machine including processors), which can be accessed via a network (e.g., the Internet) and through one or more appropriate interfaces (e.g., application programming interfaces (APIs)).

[0089] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or the processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or the processor-implemented engine may be distributed across many geographic locations.

[0090] In this specification, multiple instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are described and illustrated as independent operations, one or more individual operations may be performed concurrently, and these operations are not required to be performed in the order shown. Structures and functionalities presented as independent components in the example configuration may be implemented as combined structures or components. Similarly, structures and functionalities presented as individual components may be implemented as independent components. These and other variations, modifications, additions, and improvements are all within the scope of this document.

[0091] As used herein, “or” is inclusive rather than exclusive unless explicitly stated or indicated by context. Furthermore, “and” is both common and individual unless explicitly stated or indicated by context. Moreover, multiple instances may be provided for the resources, operations, or structures described herein as a single example. Furthermore, the boundaries between various resources, operations, engines, and data stores are somewhat arbitrary, and specific operations are illustrated within the context of a particular illustrative configuration. The allocation of other functionalities is conceivable and may fall within the scope of various embodiments of this disclosure. Generally, structures and functionalities presented as independent resources in example configurations may be implemented as combined structures or resources. Similarly, structures and functionalities presented as individual resources may be implemented as independent resources. These and other variations, modifications, additions, and improvements are all within the scope of embodiments of this disclosure. Therefore, this specification and accompanying drawings should be viewed in an illustrative rather than restrictive sense.

[0092] The terms “comprising” or “including” are used to indicate the presence of a subsequently stated feature, but do not preclude the addition of other features. Conditional language, in particular, such as “may,” “can,” or “may,” unless specifically stated or otherwise understood in the context of use, is generally intended to express that certain embodiments include certain features, elements, and / or steps, while other embodiments do not. Therefore, such conditional language generally does not imply that a feature, element, and / or step is necessary in any way for one or more embodiments, or that one or more embodiments must include logic that, with or without user input or prompting, determines whether such features, elements, and / or steps are included in any particular embodiment, or whether they are to be performed in any particular embodiment.

Claims

1. A method for pre-formatting and caching input data, characterized in that, The method includes: The system acquires input data, at least one output port, the data format of the input data, and the data format corresponding to the at least one output port. The data format includes bit width and dimension arrangement information. The dimension arrangement information includes first sub-information for characterizing the number and arrangement order of the dimensions in the data format and second sub-information for characterizing the dimension size of each dimension in the data format. Based on whether the bit width and first sub-information corresponding to the at least one output port are the same, the at least one output port is classified into at least one output port group, wherein the bit width and first sub-information corresponding to all output ports in each output port group are the same; Based on the number of output port groups, the register array used to cache the input data is divided into the same number of partitions as the number of output port groups, and each partition corresponds to one output port group; Based on the correspondence between each partition in the register array and the output port group, each output port in the output port group is mapped to the physical location of the corresponding partition. The input data is converted into a sub-data block with the same bit width and first sub-information as the output port; Based on the bit width and first sub-information corresponding to the output port, the sub-data blocks with the same bit width and first sub-information are written into the physical location of the corresponding partition that has a one-to-one mapping relationship with the output port.

2. The method according to claim 1, characterized in that, The step of writing the sub-data blocks with the same bit width and first sub-information to the physical location of the corresponding partition that has a one-to-one mapping relationship with the output port, based on the bit width and first sub-information corresponding to the output port, includes: In response to the fact that the dimension size of any dimension in the second sub-information of the sub-data block is greater than the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition, the input data is split along the dimension based on the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all output ports of the corresponding partition.

3. The method according to claim 2, characterized in that, The step of writing the sub-data blocks with the same bit width and first sub-information to the physical location of the corresponding partition that has a one-to-one mapping relationship with the output port, based on the bit width and first sub-information corresponding to the output port, includes: In response to the fact that the dimension size of any dimension in the second sub-information of the sub-data block is less than the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all the output ports of the corresponding partition, the input data is merged along that dimension based on the sum of the dimension sizes of the corresponding dimensions in the second sub-information of all the output ports of the corresponding partition.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: In response to a read request for at least one output port, the sub-data block is read in parallel from the physical location of the partition based on the one-to-one mapping between the at least one output port and the corresponding physical location of the partition in the register array.

5. The method according to claim 4, characterized in that, The register array used to cache the input data is a multidimensional register array.

6. An input data pre-formatting buffer device, characterized in that, The device includes: The information acquisition module is configured to acquire input data, at least one output port, the data format of the input data, and the data format corresponding to the at least one output port. The data format includes bit width and dimension arrangement information. The dimension arrangement information includes first sub-information for characterizing the number and arrangement order of the dimensions of the data format and second sub-information for characterizing the dimension size of each dimension in the data format. The output port classification module is configured to classify the at least one output port into at least one output port group based on whether the bit width and first sub-information corresponding to the at least one output port are the same, wherein the bit width and first sub-information corresponding to all output ports in each output port group are the same; The partitioning module is configured to divide the register array used to cache the input data into a number of partitions equal to the number of output port groups, with each partition corresponding to one output port group. The mapping module is configured to map each output port in the output port group to the physical location of the corresponding partition based on the correspondence between each partition in the register array and the output port group. The conversion module is configured to convert the input data into a sub-data block with the same bit width and first sub-information as the output port; The writing module is configured to write the sub-data block with the same bit width and first sub-information to the physical location of the corresponding partition that has a one-to-one mapping relationship with the output port, based on the bit width and first sub-information corresponding to the output port.

7. A computer device, characterized in that, The computer device includes: At least one processor; A memory having a computer program stored thereon, wherein, when executed by the at least one processor, the computer program causes the at least one processor to perform the method of any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-5.

9. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-5.

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