Modeling and parameter extraction method for distributed parasitic inductance network of wide bandgap inverter

Abstract

The application discloses a wide-bandgap inverter distributed parasitic inductance network modeling and parameter extraction method, comprising: establishing an initial topology of a distributed parasitic inductance network according to a physical structure of an inverter; designing a measurement method based on two-port parallel through S parameters and a measurement fixture following common loop additional parasitic minimization and mutual inductance coupling minimization principles; performing two-port measurement, converting S parameters into impedance curves; adaptively selecting an inductance extraction mode according to resonance characteristics of the impedance curves and correcting a model; obtaining multiple groups of equivalent inductances by constructing multiple terminal interconnection topologies for measurement and solving to obtain each distributed branch parasitic inductance; and finally fusing the distributed parasitic inductance network and device parasitic capacitance to construct a distributed parasitic parameter network model for switch transient behavior prediction. The application realizes high-precision and high-robustness extraction of nH-level parasitic inductance, and improves the accuracy of switch behavior prediction.

Description

Technical Field

[0001] This invention relates to the field of modeling and parameter acquisition technology for power electronic power converters, specifically to a method for modeling and extracting parameters of distributed parasitic inductance networks in wide-bandgap inverters. Background Technology

[0002] In the switching and commutation process of power electronic converters, transient electromagnetic behavior is closely related to parameters such as parasitic inductance in the circuit. Parasitic parameters often cause non-ideal effects such as voltage / current overshoot, ringing, additional losses, and electromagnetic interference. With the continuous improvement of switching speed of wide bandgap devices such as silicon carbide (SiC) and gallium nitride (GaN), the impact of parasitic parameters on system performance and reliability is becoming increasingly significant. Therefore, accurate modeling and parameter extraction of distributed parasitic inductance are essential for predicting device / system switching behavior and optimizing structural design.

[0003] Existing methods for extracting parasitic inductance mainly fall into two categories: electromagnetic simulation and experimental measurement. Electromagnetic simulation is typically based on a detailed three-dimensional structural model of the device under test (DUT), and parasitic parameters are calculated by setting material and boundary conditions. However, in practical engineering applications, the internal geometric details of components such as power modules and capacitors in inverters are often difficult to obtain accurately, and the current paths and their coupling relationships are complex. Therefore, it is difficult to accurately obtain the parasitic parameters of key components through electromagnetic simulation, and thus construct a distributed parasitic inductance network model.

[0004] On the other hand, experimental measurement methods can be further divided into indirect measurement and direct measurement. Indirect measurement mainly calculates parasitic inductance based on the time-domain or frequency-domain characteristics of switching transient overshoot or ringing, but its accuracy is easily affected by the measurement link bandwidth, frequency resolution, and additional resonant networks; and when the busbar and capacitor are connected, only the total equivalent parasitic inductance of the entire commutation circuit of the inverter can be obtained, making it difficult to separate the parasitic inductance of the DC busbar, capacitors, and power modules, and thus it is impossible to obtain the distributed parasitic inductance of each key component.

[0005] Direct measurement methods primarily rely on impedance analyzers or vector network analyzers to measure parasitic inductance, theoretically offering high accuracy. However, these methods typically require fixtures or leads to convert the connection between the terminals of the device under test (DUT) (non-coaxial interface) and the coaxial line of the measuring instrument (coaxial interface), inevitably introducing additional parasitic inductance and electromagnetic coupling, resulting in an error on the order of nH in the parasitic inductance measurement. Considering the optimization requirements for parasitic inductance parameters in wide-bandgap inverter systems, the parasitic inductance of DC buses, capacitors, and power modules / devices is usually small (on the order of nH), and an error on the order of nH cannot be ignored. To improve measurement accuracy, existing methods often use electromagnetic simulation to calculate the parasitic inductance of the fixture and subtract it from the measurement results. However, for this type of method based on single-port measurement, the measurement accuracy is easily affected by instrument measurement noise and errors when the impedance of the DUT is small.

[0006] To address this, the paper "Liu Y, Zhao Z, Wang W, et al. Characterization and extraction of power loop stray inductance with SiC half-bridge power module[J]. IEEE Transactions on Electron Devices, 2020, 67(10): 4040-4045" proposes a measurement method based on two-port S-parameters. This method places the device under test (DUT), such as the power module, on the common path of the two-port measurement circuit and calculates the impedance corresponding to the common path using S-parameters, thereby obtaining the parasitic inductance of the DUT. The advantage of this approach is that it can reduce the impact of the equivalent parasitic self-inductance introduced by the signal path and ground path at the two ports on the measurement results to a certain extent. However, the measurement accuracy of this method is still limited by the parasitic inductance introduced by the clamps on the common path. Therefore, the paper "Wang Z, Yuan Z, Zhao Y. Parasitic inductances extraction for SiC power modules using an enhanced two-port S-parameter approach[C] / / 2021 IEEE Applied Power Electronics Conference and Exposition (APEC). 2021: 2420-2426." proposes an optimized fixture design that minimizes the common path to improve measurement accuracy. The paper "Guo Z, Li H, Peng FZ, et al. Gate driver development and stray inductance extraction of 10 kV SiCMOSFET module for a switched-capacitor MMC application[C] / / 2022 IEEE Applied Power Electronics Conference and Exposition (APEC). 2022: 1387-1393." calculates the parasitic inductance of the fixture's common path through electromagnetic simulation and subtracts it from the measurement results to improve the measurement accuracy of the device under test. However, none of the above methods take into account the mutual inductance coupling between different paths of the clamp (such as the mutual inductance between the signal path of port 1 and the signal path of port 2, the mutual inductance between the signal path of port 1 or 2 and the common path, etc.), and the influence of the mutual inductance between different paths on the measurement of nH-level parasitic inductance cannot be ignored.It is evident that existing fixture optimization design methods and their correction methods for the impact of parasitic inductance measurement cannot meet the requirements of accurate acquisition of nH-level inductance in the modeling of distributed parasitic inductance networks for wide-bandgap inverters. Therefore, it is difficult to accurately construct a distributed parasitic inductance model for effectively predicting switching behaviors such as drain-source voltage oscillations in wide-bandgap inverters. Summary of the Invention

[0007] The purpose of this invention is to propose a method for modeling and extracting parameters of distributed parasitic inductance networks in wide-bandgap inverters. This method establishes a refined distributed parasitic inductance model, designs an optimal measurement scheme and dedicated fixture, and achieves simple, accurate, and reliable extraction of parasitic inductance. Furthermore, by combining parameters such as the output parasitic capacitance of wide-bandgap devices, a high-precision prediction model for the switching behavior of wide-bandgap inverters is constructed. This effectively predicts key performance indicators such as voltage / current overshoot and oscillation, providing a basis for the structural design, parameter evaluation, and reliability optimization of wide-bandgap inverters.

[0008] This invention is based on distributed parasitic inductance modeling. First, it establishes a distributed parasitic inductance network model by combining the physical structure connection relationship of the overall power circuit of the wide bandgap inverter. On this basis, it further introduces the parasitic capacitance parameters of power devices to form a distributed parasitic parameter network model, which is used for inverter dynamic behavior prediction.

[0009] To achieve the objectives of this invention, the following technical solutions are employed:

[0010] (1) Based on the physical structure connection relationship of the overall power circuit of the wide bandgap inverter, determine the key nodes, branch division and initial network topology of the distributed parasitic inductor network model;

[0011] (2) Design a parasitic inductance extraction method based on two-port parallel through-through S-parameters, and a low-parasitic, low-coupling measurement fixture for parasitic inductance measurement;

[0012] (3) Use the measuring fixture to perform two-port measurements on the object under test, and convert the measured S-parameters into impedance parameters to obtain the impedance frequency response curve;

[0013] (4) Determine the method for extracting parasitic inductance based on the resonance characteristics of the impedance curve;

[0014] (5) Construct different measurement circuits, extract and solve the parasitic inductance parameters of each branch, and complete the parameterization construction of the distributed parasitic inductance network model;

[0015] (6) Combine the distributed parasitic inductance network model with the parasitic capacitance parameters of the power device to establish a distributed parasitic parameter network model, and use it for inverter dynamic behavior prediction.

[0016] In step (1), the method for determining the key nodes, branch division, and initial network topology of the distributed parasitic inductor network model includes: combining the physical structure connection relationship of the overall power circuit of the wide-bandgap inverter, identifying each conductor path through which the current flows in the power loop, and equating the loop corresponding to the conductor path to the parasitic inductor; dividing the parasitic inductor into branches according to the key connection nodes and actual interconnection relationships in the circuit, and establishing the initial network topology of the distributed parasitic inductor network model; for key power devices or power modules, further combining their internal physical structure, terminal interconnection relationships, and equivalent circuit diagrams to establish corresponding device-level or module-level distributed parasitic inductor network sub-models; and on this basis, determining the parasitic inductor to be measured and its corresponding measurement path.

[0017] In step (2), the parasitic inductance extraction method based on the two-port parallel direct-through S-parameters is as follows: a two-port parallel direct-through connection configuration is used for measurement. In this configuration, the object under test is placed in the common loop formed by the signal path and the ground return path, so that the parasitic characteristics of the object under test mainly correspond to the transmission impedance in the two-port impedance network. .

[0018] In step (2), the method for designing an optimized low-parasitic, low-coupling measurement fixture for parasitic inductance measurement follows the following two core design principles:

[0019] 1) Minimize additional parasitic parameters in the common loop: The fixture design should minimize the additional parasitic parameters it introduces in the measurement common loop, including parasitic parameters introduced by the fixture signal path. Parasitic parameters introduced by the clamp grounding return path To reduce such additional parasitic effects, specific measures include: providing clear, closed, and as symmetrical as possible independent return paths for each port to reduce the loop area and thus suppress the non-ideal sharing of signal and ground return paths caused by improper layout; at the same time, the use of special structures such as sockets, pads, and height adapters should be minimized to reduce the additional return parasitic effects they introduce.

[0020] 2) Minimize mutual inductance coupling: By optimizing the spatial layout and return path of the two ports of the fixture, the dominant mutual inductance between the ports is suppressed, that is, the mutual inductance between the two signal paths. Mutual inductance between the two grounding return paths To reduce its impact on transmission impedance The influence of the measured values ​​and the equivalent inductance derived therefrom. The influence of this dominant mutual inductance can be eliminated through simulation; its influence can be ignored when the measured inductance value is greater than 15nH or when the measurement accuracy requirement is not high. For other mutual inductance terms introduced by special structures, such as the mutual inductance between the signal path at port 1 and the signal path in the common loop. Mutual inductance between the signal path at port 2 and the signal path in the common loop Mutual inductance between the return path at port 1 and the common loop path Mutual inductance between the return path at port 2 and the common loop path The coupling contribution can be controlled within a preset error threshold by making the special structure approximately orthogonal to the main current path, having a compact structure, and minimizing its own loop area. When the individual error contribution of the other mutual inductance terms to the extraction of the equivalent inductance is no greater than 0.2nH and the total error contribution is no greater than 0.5nH, they will not be compensated separately during the extraction process; if the individual error contribution or the total error contribution exceeds the above limits, they will be included in the compensation model for correction.

[0021] In step (3), the two-port measurement of the object under test using the measuring fixture is specifically performed as follows: a vector network analyzer is used as the measuring device. Before measurement, the sweep frequency range and the number of sweep frequency points are selected based on the instrument performance and the characteristics of the object under test. The sweep frequency range needs to cover the frequency band of interest, and the number of frequency points should be sufficient to ensure the integrity of the impedance frequency response information. During measurement, the port calibration is first completed using the SOLT calibration method in two-port mode, and the reference plane is transferred from the coaxial terminal of the vector network analyzer to the coaxial terminal of the custom fixture. Then, the custom fixture is reliably connected to the object under test, and the entire measurement loop including the fixture and the object under test is swept to obtain the corresponding two-port S-parameters.

[0022] In step (3), the method for converting the measured S-parameters into impedance parameters and obtaining the impedance curve is as follows: When using a two-port parallel direct-through measurement structure, the object under test is located in a common loop formed by the signal and ground, so that the measured transmission impedance is mainly determined by the object under test. To reduce the measurement deviation caused by the residual parasitic effect of the fixture, the transmission impedance is calculated using the complete two-port network parameter transformation relationship. :

[0023]

[0024] in, This is the system reference impedance (typically 50Ω). The reflection coefficient of port 1, The reflection coefficient of port 2, Forward transmission coefficient from port 1 to port 2, This represents the reverse transmission coefficient from port 2 to port 1. Through this transformation, the measured S-parameters are converted into impedance parameters, thereby obtaining the impedance curve of the measured object as a function of frequency.

[0025] In step (4), the method for determining the parasitic inductance extraction method and its corresponding parasitic parameter circuit model based on the resonance characteristics of the impedance curve is as follows: observe and analyze the impedance frequency response curve of the object under test obtained in step (3), determine the parasitic inductance extraction method and its corresponding parasitic parameter circuit model based on the resonance characteristics in the impedance curve, and compare the determined parasitic parameter circuit model with the distributed parasitic inductance network model established in step (1); if the determined parasitic parameter circuit model is inconsistent with the distributed parasitic inductance network model in step (1), then the distributed parasitic inductance network model in step (1) is corrected accordingly to update the distributed parasitic inductance network model.

[0026] The corresponding analysis of the resonance characteristics of the impedance curve specifically includes:

[0027] When there is no resonant point in the impedance curve, the equivalent parasitic inductance is extracted based on the impedance slope in the high-frequency band. And determine the parasitic resistance based on the impedance. Its corresponding parasitic parameter circuit model is the RL circuit;

[0028] When there is a resonant point in the impedance curve, according to the resonant frequency With equivalent capacitance The parasitic inductance is extracted based on the relationship, and the calculation formula is as follows: ,in, Obtained from the impedance slope in the low-frequency band. Take the impedance phase as The frequency point, the impedance at the resonant frequency determines the parasitic resistance. Its corresponding parasitic parameter circuit model is an RLC circuit;

[0029] When the impedance curve contains At each resonance point, and ,Establish The parasitic parameters of the RLC equivalent circuit model are obtained by fitting the model parameters according to the root mean square error minimization criterion between the impedance curve of the equivalent circuit model and the measured impedance curve within the frequency band of interest. The corresponding parasitic parameter circuit model is as described above. Equivalent circuit model of parasitic parameters of order RLC.

[0030] In step (5), the specific implementation method for constructing different measurement circuits and extracting and solving the parasitic inductance parameters of each branch is applicable to discrete devices and power modules:

[0031] (1) Modeling method for discrete devices: Taking the drain-source parasitic inductance of a discrete device as an example, the drain is connected to the common node of the signal path and the common path, and the source is connected to the common node of the ground return path and the common path, forming a parallel direct connection structure. By switching the connection structure of the three terminals, the total parasitic inductance combination between the drain and the source can be obtained respectively. Total parasitic inductance combination between gate and drain Total parasitic inductance combination between gate and source The parasitic inductance of the drain is obtained by combining three sets of quantities. Parasitic inductance of the source electrode Parasitic inductance of the gate branch .

[0032] (2) Modeling method for power modules: For conventional power modules without bridge arm interconnection structures, the equivalent current loops flowing through the upper bridge arm, lower bridge arm, and AC output related paths can be constructed by switching the interconnection structure between module terminals, thereby extracting the parasitic inductance parameters on the corresponding paths. For power modules with bridge arm interconnection structures (such as six-module power modules), the parasitic inductance of the module terminals can be measured using the additional parameter of the terminal interconnection structure. This invention performs two-port measurements by switching different terminal interconnection topologies, so that the measured current forms different equivalent current paths inside the module, and obtains the corresponding equivalent parasitic inductance. The equivalent inductance under each topology can be regarded as a combination of several distributed branch parasitic inductances on that path. Further, multiple independent interconnection topologies are selected (e.g., DC positive terminal to DC negative terminal path, same polarity DC terminal interconnection path, DC terminal to phase output terminal path, etc.), and a set of constraint equations for multiple unknown branch inductances is established. Distributed parasitic inductance parameters such as upper branch, lower branch, output-related interconnection branches, and DC terminal interconnection branches are obtained through algebraic solutions or constraint optimization. Subsequently, these parameters are assembled into a distributed parasitic inductance network model according to the actual current paths. This modeling process focuses on terminal interconnection topology, path equivalent inductance, and equation solving, without relying on specific packages or lead structures. Therefore, it can be transferred to power modules with different terminal layouts and internal interconnection forms, and is suitable for various types of test objects, including power modules with pins or power terminals, and surface-mount or through-hole discrete devices.

[0033] Furthermore, the fixture used to measure the drain-source parasitic inductance can also be directly applied to the measurement of the parasitic inductance on the DC bus side to obtain the parasitic parameters on that side. That is, for the extraction of parasitic parameters on the DC bus side, the measurement point is the terminal on the DC bus side connected to the power module. The measuring fixture used does not need to be redesigned, as it is the fixture for measuring the parasitic inductance of the upper and lower bridge arms of the power module. In step (6), the method of "establishing a distributed parasitic parameter network model for inverter dynamic behavior prediction" specifically includes: after obtaining the distributed parasitic inductance network model of the overall power circuit of the wide-bandgap inverter, it is integrated with the parasitic capacitance parameters of the power devices or power modules to establish a distributed parasitic parameter network model that can simultaneously reflect the distribution of inductance and capacitance; based on this model, it can be used to predict voltage overshoot, ringing frequency and related dynamic behavior during the inverter switching transient process through circuit simulation or resonance characteristic calculation. Accordingly, the present invention also provides a system for implementing the above method, which mainly includes the following components: a two-port measurement device for performing two-port measurements under different interconnection topologies to obtain S-parameter data; a matching measurement fixture manufactured based on the aforementioned design principles for connecting the object under test and ensuring measurement accuracy; a data processing and parameter solving unit for performing the transformation from S-parameters to Z-parameters, extracting equivalent inductance, and solving distributed parameters; and a model building and prediction unit for assembling a distributed parasitic inductance network, fusing system-side parasitic parameters, and outputting prediction results such as drain-source ringing.

[0034] Depending on the application requirements, the present invention also provides the following alternatives or supplementary means: single-port measurement can be used as an auxiliary verification method; analytical solutions and least squares / constraint optimization fitting strategies can be adopted to adapt to different test conditions and accuracy requirements while ensuring extraction accuracy and engineering feasibility; for different accuracy levels, compensation models of different complexities can be selected, including ignoring coupling terms, partial compensation, or full compensation schemes.

[0035] Terminology Explanation:

[0036] S-parameters: Scattering parameters are network parameters used to describe the relationship between incident and reflected waves in radio frequency / microwave networks.

[0037] Z-parameters: Impedance parameters, network parameters used to describe the relationship between port voltage and current. SOLT calibration: A vector network analyzer calibration method based on short-circuit, open-circuit, load, and through standard components.

[0038] Compared with the prior art, the present invention has the following significant advantages:

[0039] (1) By using the two-port parallel direct S-parameter measurement method, the complete S-parameter to impedance parameter conversion method, and the means of reducing the additional parasitics in the common loop and suppressing the dominant mutual inductance coupling, the accuracy of the transmission impedance in characterizing the intrinsic parasitic inductance of the measured object is improved, and the high-precision extraction of nH-level parasitic inductance is realized, thereby improving the accuracy and repeatability of parasitic inductance measurement.

[0040] (2) The two-port parallel through-through S-parameter measurement method of the present invention is not sensitive to changes in port connection status, cable configuration and calibration conditions. Under test conditions such as changes in adapter, cable configuration and calibration status, it can still maintain high consistency and extraction accuracy, thereby significantly improving the robustness of the measurement results to test conditions.

[0041] (3) The present invention improves the traditional single equivalent inductance extraction into an assemblable distributed parasitic inductance network model, which can further solve for the parasitic inductance of each branch, enhancing the consistency between the model and the actual current path, as well as the applicability and transferability to different devices and module structures.

[0042] (4) The distributed parasitic parameter network model established by this invention can be used to predict switching transient behaviors such as drain-source oscillation of inverters, and can provide a basis for early structural design, parameter evaluation and scheme optimization, thereby simplifying the development process, reducing the number of trials and errors and shortening the design iteration cycle. Attached Figure Description

[0043] Figure 1 This is a flowchart of the method for modeling and extracting parameters of the distributed parasitic inductance network of a wide-bandgap inverter according to the present invention.

[0044] Figure 2 The following are the official data for the CCB021M12FM3 power module: (a) the physical structure of the power module including circuit nodes; and (b) the internal circuit connections of the power module.

[0045] Figure 3 The following is a schematic diagram of the distributed parasitic inductance network model of the silicon carbide inverter in this invention: (a) Distributed parasitic parameter model of the power module; (b) Distributed parasitic parameter model of the silicon carbide inverter.

[0046] Figure 4 The following is a schematic diagram of the two-port S-parameter measurement principle and the influence of the fixture in this invention: (a) Test equivalent circuit; (b) Three-dimensional schematic diagram of the fixture parasitic effect.

[0047] Figure 5 The following is a schematic diagram of the measurement principle of parasitic inductance of the converter circuit in this invention: (a) Distributed parasitic parameter model of the power module converter circuit; (b) Equivalent circuit diagram of two-port measurement (taking phase U as an example).

[0048] Figure 6 This is a comparison chart of the DC busbar side impedance curve and the fitted curve obtained by the two-port scheme in this invention.

[0049] Figure 7 This is a schematic diagram illustrating the measurement principle of the parasitic inductance on the upper tube and the output side in this invention (taking phase U as an example).

[0050] Figure 8 This is a schematic diagram illustrating the measurement principle of the parasitic inductance on the lower tube and the output side in this invention (taking phase U as an example).

[0051] Figure 9 This is a schematic diagram illustrating the measurement principle of the parasitic inductance of the inter-arm interconnection structure in this invention (taking phase U as an example).

[0052] Figure 10 This is a schematic diagram illustrating the measurement principle of parasitic inductance of module terminals (taking a pin structure as an example) in this invention.

[0053] Figure 11 This is a comparison of the simulation and experimental waveforms of drain-source voltage oscillation during the turn-off process of the lower transistor under 800V and 35A conditions in this invention. Detailed Implementation

[0054] The present invention will now be described in further detail with reference to the accompanying drawings. The following embodiments are only used to explain the technical solutions of the present invention and do not constitute a limitation on the scope of protection of the present invention.

[0055] This invention discloses a method for modeling and extracting parameters of distributed parasitic inductance networks in wide-bandgap inverters, the process of which is as follows: Figure 1 As shown, the process mainly includes six steps. In this embodiment, the wide bandgap inverter is a 10 kW inverter platform built based on the Wolfspeed CCB021M12FM3 six-unit power module. The specific implementation process is as follows:

[0056] The first step is to determine the key nodes, branch divisions, and initial network topology of the distributed parasitic inductance network model.

[0057] like Figure 2 As shown, the physical structure and circuit connection relationship of the power module used in this embodiment are determined. Figure 2In this diagram, DC+1, DC+2, and DC+3 represent the DC positive bus connection nodes corresponding to the upper transistors of the three bridge arms of the three-phase inverter, respectively; DC-1, DC-2, and DC-3 represent the DC negative bus connection nodes corresponding to the lower transistors of the three bridge arms, respectively; U, V, and W represent the three-phase output terminals, respectively; G1~G6 represent the gate drive terminals of the six power switching devices, respectively; S1~S6 represent the source reference terminals of the six power switching devices, respectively; and NTC1 and NTC2 represent the two connection terminals of the NTC thermistor. Based on this, the conductor paths through which the current flows in the power loop are identified, and the loops corresponding to these conductor paths are equivalent to parasitic inductances. According to the key connection nodes and actual interconnections in the circuit, the parasitic inductances are branched, establishing the initial network topology of the distributed parasitic inductance network model, as shown below. Figure 3 As shown. For key power devices or power modules, a corresponding device-level or module-level distributed parasitic inductance network sub-model is established by further combining their internal physical structure, terminal interconnection relationships, and equivalent circuit diagrams. Figure 3 In (a) ( ) indicates the first The parasitic inductance of the terminal connection between the power switching device chip terminals and the external terminals of the module, wherein... =1, 3, 5 correspond to the power devices in the upper bridge arm. =2, 4, and 6 correspond to the lower bridge arm power devices; ( =1, 3, 5) represents the parasitic inductance of the drain-side connection branch of the power switching device in the upper bridge arm. ( =2, 4, 6) represent the parasitic inductance of the source-side connection branch of the lower bridge arm power switching device; ( ) indicates the first Parasitic inductance of the gate drive circuit of a power switching device; , and ( ) respectively represent the first The gate-drain parasitic capacitance, gate-source parasitic capacitance, and drain-source parasitic capacitance of a power switching device; and This represents the parasitic inductance of the DC positive side interconnection structure of adjacent bridge arms; , , These represent the parasitic inductances of the U-phase, V-phase, and W-phase AC output paths, respectively.

[0058] Based on the physical structure of the module side and the capacitor and busbar interconnection structure of the DC busbar side, the main conductor paths through which the current flows in the overall power loop are identified. Parasitic inductance branches are then divided according to key connection nodes and actual interconnection relationships, thereby establishing the initial network topology of the wide-bandgap inverter distributed parasitic inductance network model. Since this embodiment primarily focuses on the switching transient characteristics such as voltage spikes and ringing of power devices, distributed branch modeling is used for the key parasitic loops on the module side, and lumped equivalent characterization is used for the parasitic parameters on the DC busbar side. Both together constitute the topological foundation of the overall power loop parasitic parameter model. The final result is as follows: Figure 3 The diagram shows a distributed parasitic parameter model of a silicon carbide inverter. Figure 3 In (b) This represents the equivalent series parasitic inductance of the DC bus support capacitor. This represents the parasitic inductance of the DC bus interconnection path. This indicates the DC bus support capacitor. This represents the equivalent parasitic capacitance on the DC bus side, and Q1~Q6 represent six power switching devices. These represent the output capacitances of the six power switching devices.

[0059] The second step is to construct a parasitic inductance extraction scheme based on two-port parallel through-S-parameters, and a low-parasitic, low-coupling measurement fixture for parasitic inductance measurement.

[0060] Figure 4 This diagram illustrates the principle of the two-port S-parameter measurement of this invention and the influence of the fixture. The fixture serves as a transition connection between the device under test (DUT) and the vector network analyzer via a coaxial cable, and minimizes the current path from the coaxial port to the DUT terminal to reduce measurement-introduced errors. Figure 4 In the equivalent model shown in (a), and This represents the parasitic impedance of the fixture signal path. and This represents the parasitic impedance of the fixture's return path. Within the target frequency band (e.g., 10 kHz to 50 MHz), the parasitic impedance can be equivalent to a low-impedance network dominated by parasitic inductance. To address the need for repeated testing of pin modules and adaptation to differences in terminal heights between different modules, this embodiment incorporates structures such as sockets, copper pads, or height adapters in the fixture. The additional common loop parasitics introduced by these structures are denoted as... and . The mutual inductance between the signal path at port 1 and the signal path at port 2. The mutual inductance between the return path at port 1 and the return path at port 2. The mutual inductance between the signal path at port 1 and the signal path in the common loop. The mutual inductance between the signal path at port 2 and the signal path in the common loop. The mutual inductance between the return path at port 1 and the common loop path. This refers to the mutual inductance between the return path at port 2 and the common loop path.

[0061] Regarding the optimized design of the measuring fixture, this embodiment focuses on two principles: minimizing parasitic additions to the common loop and minimizing mutual inductance coupling. Specifically, by providing independent, closed, and as symmetrical as possible return paths for each of the two ports, the loop area is reduced, and the fixture avoids introducing additional parasitics into the common path, thus... and The main characteristics are the parasitic additional common loop introduced by the special structure; at the same time, the mutual inductance between the two signal paths is suppressed by optimizing the spatial layout between ports and the return current path. Mutual inductance between the two grounding return paths For mutual inductance between different paths of the fixture, the mutual inductance value is calculated through three-dimensional electromagnetic simulation and then removed from the measurement results. When the measured inductance value is higher than 15nH and the allowable relative measurement error is no higher than 10%, the mutual inductance can be left unremoved. For mutual inductance introduced by special structures such as sockets and copper pads, the coupling contribution is controlled to within 0.5nH by making them orthogonal to the main current path and minimizing the loop area. After equivalent evaluation, the equivalent additional inductance introduced by the fixture is about 1.02~1.30 nH, accounting for about 5%~8% of the measured equivalent inductance. This indicates that the low parasitic and low coupling fixture can effectively reduce the influence of the fixture on the measurement results and provide a stable measurement basis for subsequent parasitic parameter extraction and distributed parameter solution.

[0062] The third step involves using the measuring fixture to perform two-port measurements on the object under test, converting the measured S-parameters into impedance parameters, and obtaining the impedance frequency response curve.

[0063] Specifically, a vector network analyzer was used to perform frequency sweep measurements on the object under test (DUT), with the sweep range set to 10 kHz to 50 MHz. Before measurement, the sweep range and number of sweep points were selected based on the instrument performance and the characteristics of the DUT. During measurement, port calibration was first performed in two-port mode using the SOLT calibration method, transferring the reference plane from the coaxial terminal of the vector network analyzer to the coaxial terminal of the custom fixture. Then, the custom fixture was reliably connected to the DUT, and the entire measurement loop, including the fixture and the DUT, was swept to obtain the corresponding two-port S-parameters.

[0064] After obtaining the S-parameters, the transmission impedance is calculated using the complete two-port network parameter transformation relationship. :

[0065]

[0066] in, The system reference impedance is 50Ω. The reflection coefficient of port 1, The reflection coefficient of port 2, Forward transmission coefficient from port 1 to port 2, This represents the reverse transmission coefficient from port 2 to port 1. Through this transformation, the measured S-parameters are converted into impedance parameters, thereby obtaining the impedance curve of the measured object as a function of frequency.

[0067] The fourth step is to determine the parasitic inductance extraction method and its corresponding parasitic parameter circuit model based on the resonance characteristics of the impedance curve. If the determined parasitic parameter model is inconsistent with that in the first step, the distributed parasitic inductance network model in the first step is modified accordingly.

[0068] Specifically, the appropriate parasitic inductance extraction method is selected based on the impedance characteristics of the object under test, and the corresponding parasitic parameter circuit model is determined accordingly:

[0069] When there is no resonant point in the impedance curve, the equivalent parasitic inductance is extracted based on the impedance slope in the high-frequency band. And determine the parasitic resistance based on the impedance. The corresponding parasitic parameter circuit model is an RL circuit;

[0070] When there is a resonant point in the impedance curve, according to the resonant frequency With equivalent capacitance The parasitic inductance is extracted based on the relationship, and the calculation formula is as follows: ,in Obtained from the impedance slope in the low-frequency band. The parasitic resistance is determined by the impedance at the resonant frequency, where the impedance phase is 0°. The corresponding parasitic parameter circuit model is an RLC circuit;

[0071] When the impedance curve contains One resonant point ( When establishing The equivalent circuit model of the parasitic parameters of the RLC is obtained by fitting the model parameters according to the root mean square error minimization criterion between the impedance curve of the equivalent circuit model and the measured impedance curve in the frequency band of interest. The corresponding parasitic parameters circuit model is as described above. Equivalent circuit model of parasitic parameters of order RLC.

[0072] The parasitic parameter circuit model is then compared with the distributed parasitic inductance network model established in the first step. If they are inconsistent, the distributed parasitic inductance network model in the first step is modified accordingly to update the distributed parasitic inductance network model. Figure 5 Taking the equivalent circuit shown in (b) as an example, its impedance curve has a resonant point. Therefore, the parasitic inductance can be extracted by combining the resonant frequency and the equivalent capacitance, and the corresponding parasitic parameter circuit model is determined to be an RLC circuit. Figure 5 In diagram (b), port1 is the connection point between port 1 of the vector network analyzer and the measuring fixture, and port2 is the connection point between port 2 of the vector network analyzer and the measuring fixture. oss_up C is the output capacitor of the upper bridge arm power switching device. oss_low Z is the output capacitance of the lower bridge arm power switching device, Z is the equivalent impedance of the measurement circuit or branch, and L is the output capacitance of the lower bridge arm power switching device. 1+ L is the distributed parasitic inductance of the internal interconnection branch on the DC positive bus side (DC+) of the power module. 2+ This refers to the distributed parasitic inductance of the secondary interconnection branch of the DC positive terminal inside the power module.

[0073] Under the same fixture conditions as the power loop measurement, this embodiment further employs a two-port method to measure the impedance frequency response of the DC busbar side, which is the combination of DC busbar capacitance and busbar interconnection structure. For the DC busbar interconnection structure, since it can be equivalent to a second-order RLC network, there are two resonant points in the impedance curve. Therefore, a second-order RLC equivalent model is used to fit the measured impedance curve. Based on the root mean square error minimization criterion, a gradient descent iterative optimization algorithm is used to solve for the equivalent parameters, ensuring that the fitting result simultaneously matches the low-frequency capacitor-dominated region and the mid-to-high frequency resonant region. This allows for the extraction of DC busbar-side equivalent parameters that can be used for switch transient analysis, such as... Figure 6 As shown. The fitting results show that the equivalent capacitance is approximately 64.73 μF, which is basically consistent with the nominal value of 65 μF; the equivalent series inductance is approximately 19.1 nH, which is basically consistent with the 19 nH given in the device datasheet. In addition, the measured parasitic inductances of the three-phase busbars / interconnects are 4.02 nH for phase U, 4.86 nH for phase V, and 3.53 nH for phase W, which are on the same order of magnitude as those obtained by Q3D (simulation software) simulation (3.78 nH for phase U, 4.53 nH for phase V, and 2.76 nH for phase W). The above results show that the resonance characteristics of the impedance curve are in good agreement with the established distributed parasitic parameter model, thus verifying the rationality of the established model and its consistency with the measured results. If the parasitic parameter model determined based on the resonance characteristics of the impedance curve is inconsistent with the initial network topology established in step (1), the distributed parasitic inductance network model in step (1) should be corrected accordingly.

[0074] The fifth step is to construct different measurement circuits, extract and solve the parasitic inductance parameters of each branch, and complete the parameterization construction of the distributed parasitic inductance network model.

[0075] Specifically, taking phase U as an example, under the same fixture design principles and measurement procedures, five different terminal interconnection topologies are switched and two-port measurements are performed respectively to obtain the corresponding equivalent parasitic inductance. ( (where N=5). It should be noted that the parasitic inductance participating in the equivalent combination is limited to the parasitic branches within the measurement link closed loop, i.e. Figure 5 , 7 The components marked in dark in 1, 8, 9, and 10 have connection points com_s and com_g between the fixture and the device under test, respectively; branches that do not enter the closed loop do not participate in the equivalent calculation under the corresponding topology.

[0076] (I) Modeling methods for power modules

[0077] First, through three basic topologies ( Figure 5 , 7 8) Obtain three sets of equivalent inductances: Figure 5 The measurement loop shown in (a) corresponds to the series path of the upper and lower bridge arms. Figure 7 Corresponding to the upper bridge arm and AC output path, Figure 8 This corresponds to the lower bridge arm and the AC output path. From this, we can obtain the following system of equations:

[0078]

[0079] Therefore, the parasitic inductance of the upper branch can be obtained by algebraic solution. Parasitic inductance of the lower branch Parasitic inductance of output-related interconnected branches :

[0080]

[0081] Based on this, further switching between the DC-side local path (e.g., DC+2-DC−1) and the DC positive-side interconnect path (DC+ interconnect) can obtain... , Equal combinations, respectively as follows Figure 9 As shown in Figure 10; combined with the previously obtained... , , The additional parasitic inductance parameters, such as those of the DC-end interconnect branches, can be obtained from the known branch contributions. For power modules with bridge arm interconnect structures (such as six-module power modules), additional parameter measurements are performed using the terminal interconnect structure. By switching different terminal interconnect topologies to conduct two-port measurements, the measured current forms different equivalent current paths within the module, and the corresponding equivalent parasitic inductances are obtained. The equivalent inductance under each topology is considered as a combination of several distributed branch parasitic inductances on that path. Multiple sets of independent interconnect topologies are selected (e.g., DC positive terminal-DC negative terminal path, same polarity DC terminal interconnect path, DC terminal-phase output terminal path, etc.), and a set of constraint equations for multiple unknown branch inductances is established. The distributed parasitic inductance parameters of the upper branch, lower branch, output-related interconnect branches, and DC-end interconnect branches are obtained through algebraic solutions or constraint optimization. Then, they are assembled into a distributed parasitic inductance network model according to the actual current paths. Furthermore, by incorporating the bridge arm interconnect structure and pin terminal structure into the measurement link, parameters such as bridge arm interconnect parasitic inductance and terminal / pin parasitic inductance can be obtained sequentially, ultimately assembling a distributed parasitic inductance network model that conforms to the actual current path. This modeling process does not depend on a specific package or lead structure, and therefore can be transferred to power modules with different terminal layouts and internal interconnection forms. It is applicable to various types of test objects, including power modules with pins or power terminals, as well as surface-mount or through-hole discrete devices.

[0082] (II) Modeling methods for discrete devices

[0083] For discrete devices (such as a single SiC MOSFET), a similar two-port parallel pass-through measurement method is used. The drain is connected to the common node of the signal path and the common path, and the source is connected to the common node of the ground return path and the common path, forming a parallel pass-through connection structure. By switching the connection structure of the three terminals, the total parasitic inductance combination between the drain and source can be obtained separately. Total parasitic inductance combination between gate and drain The combined total parasitic inductance between the gate and source The parasitic inductance of the drain is obtained by combining three sets of quantities. Parasitic inductance of the source electrode Parasitic inductance of the gate branch .

[0084] (III) Extraction of parasitic parameters on the DC bus side

[0085] For the extraction of parasitic parameters on the DC bus side, the measurement point is the terminal on the DC bus side connected to the power module. The measurement fixture used does not need to be redesigned, as it is the fixture for measuring the parasitic inductance of the upper and lower bridge arms of the power module.

[0086] (iv) Verification of measurement results

[0087] In this embodiment, when comparing and verifying the parasitic inductance related to the pins, the Q3D simulation results and measurement results showed high consistency, at 7.87 nH and 7.75 nH respectively. Table 1 shows the measurement results of the parasitic inductance of the power circuit, where the parameters in parentheses are those provided by the manufacturer's official model. As can be seen from the above results, this invention can directly extract distributed parasitic inductance parameters through experiments without relying on detailed internal structural information of the power module. Compared to existing methods that mainly rely on Q3D simulation and indirect verification through lumped converter circuit measurements, this invention can still be implemented even when the internal packaging details of the module are unavailable, thereby improving the traceability of the model source and engineering reliability. The above results further demonstrate that this method can achieve high-precision and repeatable extraction of parasitic inductance at the nH level.

[0088] Table 1. Measurement results of parasitic inductance in the power circuit (values ​​in parentheses are parameters from the manufacturer's official model)

[0089]

[0090] The sixth step is to combine the distributed parasitic inductance network model with the parasitic capacitance parameters of the power devices to establish a distributed parasitic parameter network model, which is then used for inverter dynamic behavior prediction.

[0091] Specifically, after obtaining the distributed parasitic inductance network model of the overall power circuit of the wide-bandgap inverter, it is combined with the parasitic capacitance parameters of the power devices or power modules to establish a distributed parasitic parameter network model that can simultaneously reflect the distribution of inductance and capacitance. Based on this model, voltage overshoot, ringing frequency, and related dynamic behaviors during the inverter's switching transient process are predicted through circuit simulation or resonance characteristic calculation. After obtaining the distributed parasitic inductance network model on the module side and the equivalent parameters on the DC bus side, a simulation topology consistent with the actual double-pulse experimental platform is built in the simulation platform, and the DC bus support capacitor is added. Equivalent series parasitic inductance of DC bus support capacitor Equivalent parasitic capacitance on the DC bus side Parasitic inductance of DC bus interconnection path Using parameters such as [parameter name] as input to the parasitic network of the power loop, the oscillation waveforms of the drain-source voltage and loop current are obtained, and then compared and analyzed with the measured waveforms. Figure 11 As shown in the figure. The results show that the distributed parasitic parameter network model established in this invention has good consistency with the experimental results in terms of overshoot amplitude and ringing frequency, and can be used for accurate prediction of inverter switching transient behavior.

[0092] System Composition and Optional Modes

[0093] The system implementing the above method mainly includes: a two-port measurement device (vector network analyzer) for performing two-port measurements under different interconnection topologies and obtaining S-parameter data; a matching measurement fixture, manufactured based on the aforementioned design principles, for connecting the object under test and ensuring measurement accuracy; a data processing and parameter solving unit for performing S-parameter to Z-parameter transformation, equivalent inductance extraction, and distributed parameter solving; and a model building and prediction unit for assembling the distributed parasitic inductance network, fusing system-side parasitic parameters, and outputting prediction results such as leakage-source ringing. The system supports the following optional operating modes: a single-port measurement-assisted verification mode; a parasitic parameter extraction mode based on analytical solution and least squares or constraint optimization fitting; and a compensation mode that selects a scheme that ignores coupling terms, provides partial compensation, or provides full compensation based on accuracy requirements.

[0094] Robustness verification

[0095] To verify the applicability and stability of the two-port parasitic inductance extraction method described in this invention under different connection conditions, the parasitic inductance extraction results were compared and analyzed by changing the external connection method and calibration state during the test process, using the same fixture structure. Specific test conditions included changes in adapter connection state, cable configuration, and calibration state. Test results show that the parasitic inductance obtained by the method of this invention maintains high consistency and minimal parameter fluctuations under different conditions. Using long-line calibration and long-line measurement as a reference, when switching to short-line measurement or measuring without recalibration, the deviation of the extracted parasitic inductance can still be controlled within [a certain range]. Within a certain range, the relative deviation does not exceed 1.78%. The above results demonstrate that the two-port extraction method proposed in this invention is highly robust to variations in the presence or absence of adapters, cable selection, and calibration conditions. Changes in actual test conditions do not significantly reduce the accuracy of the extracted parasitic inductance parameters, thus effectively suppressing systematic deviations and improving the stability, repeatability, and reliability of parasitic inductance extraction. The corresponding test conditions and results are shown in Table 2.

[0096] Table 2 Extraction results under different test conditions

[0097]

[0098] In summary, this embodiment achieves accurate and robust measurement of parasitic parameters on the power module and DC bus side under low impedance measurement conditions by utilizing a two-port parallel through-through measurement structure and low parasitic and low coupling fixtures. Multiple sets of equivalent parasitic inductances are obtained through various terminal interconnection topologies, and branch decomposition is completed to establish a distributed parasitic inductance network model that conforms to the actual current path. Furthermore, by combining two-port measurement on the DC bus side with second-order RLC fitting, equivalent parameters on the DC bus side, such as the bus and capacitor connection structure, are obtained. The final distributed parasitic parameter model can accurately predict oscillation waveforms.

Claims

1. A method for modeling and extracting parameters of distributed parasitic inductance networks in wide-bandgap inverters, characterized in that, Includes the following steps: Step (1): Based on the physical structure connection relationship of the overall power circuit of the wide bandgap inverter, determine the key nodes, branch division and initial network topology of the distributed parasitic inductor network model; Step (2): Construct a parasitic inductance extraction scheme based on two-port parallel through-through S-parameters. The object under test is always placed on the common path of the two ports, and a low parasitic and low coupling measurement fixture is provided. The low parasitic and low coupling measurement fixture provides independent, closed and symmetrical return paths for the two ports respectively, and optimizes the spatial layout and return path direction between the two ports. Step (3): Use the measuring fixture to perform two-port measurements on the object under test, and convert the measured S-parameters into impedance parameters to obtain the impedance frequency response curve; the specific steps include: using the measuring fixture to perform two-port measurements on the object under test specifically: using a vector network analyzer as the measuring device; before measurement, select the sweep frequency range and the number of sweep frequency points based on the instrument performance and the characteristics of the object under test; during measurement, first complete the port calibration using the SOLT calibration method in two-port mode, and transfer the reference plane from the coaxial terminal of the vector network analyzer to the coaxial terminal of the custom fixture; then, reliably connect the custom fixture to the object under test, sweep the frequency of the entire measurement loop including the fixture and the object under test, and obtain the corresponding two-port S-parameters; convert the measured S-parameters into impedance parameters to obtain the impedance curve. The method is as follows: when using a two-port parallel through-through S-parameter measurement structure, the object under test is located in the common loop formed by the signal and ground; calculate the transmission impedance using the complete two-port network parameter transformation relationship. : ,in, As the system reference impedance, The reflection coefficient of port 1, The reflection coefficient of port 2, Forward transmission coefficient from port 1 to port 2, The reverse transmission coefficient from port 2 to port 1 is given; through the transformation, the measured S-parameters are converted into impedance parameters, thereby obtaining the impedance curve of the measured object as a function of frequency. Step (4): Determine the parasitic inductance extraction method and its corresponding parasitic parameter circuit model based on the resonance characteristics of the impedance curve. If the determined parasitic parameter model is inconsistent with that in step (1), then the distributed parasitic inductance network model in step (1) is modified accordingly. Step (5): Construct different measurement circuits, extract and solve the parasitic inductance parameters of each branch, and complete the parameterization construction of the distributed parasitic inductance network model; Step (6): Combine the distributed parasitic inductance network model with the parasitic capacitance parameters of the power devices to establish a distributed parasitic parameter network model, and use it for inverter dynamic behavior prediction.

2. The method for modeling and extracting parameters of distributed parasitic inductance networks in wide-bandgap inverters according to claim 1, characterized in that, In step (1), the method for determining the key nodes, branch division, and initial network topology of the distributed parasitic inductor network model includes: combining the physical structure connection relationship of the overall power circuit of the wide-bandgap inverter, identifying each conductor path through which the current flows in the power loop, and equating the loop corresponding to the conductor path to the parasitic inductor; dividing the parasitic inductor into branches according to the key connection nodes and actual interconnection relationships in the circuit, and establishing the initial network topology of the distributed parasitic inductor network model; for key power devices or power modules, further combining their internal physical structure, terminal interconnection relationships, and equivalent circuit diagrams, establishing corresponding device-level or module-level distributed parasitic inductor network sub-models; after establishing the initial network topology and the sub-model, determining the parasitic inductor to be measured and its corresponding measurement path.

3. The method for modeling and extracting parameters of distributed parasitic inductance networks in wide-bandgap inverters according to claim 1, characterized in that, In step (2), the optimization of the spatial layout and return path between the two ports is used to suppress the mutual inductance between the two signal paths and the mutual inductance between the two ground return paths. The mutual inductance is obtained by simulation calculation and removed from the measurement results. When the measured inductance value is higher than 15nH and the allowable relative measurement error is not higher than 10%, the mutual inductance can be left unremoved. For mutual inductance introduced by special structures such as sockets, pad copper sheets, and height adapters, the coupling contribution is controlled within 0.5nH by making the special structure orthogonal to the main current path and minimizing its own loop area, and its influence is ignored.

4. The method for modeling and extracting parameters of distributed parasitic inductance networks in wide-bandgap inverters according to claim 1, characterized in that, In step (4), the method for extracting parasitic inductance and its corresponding parasitic parameter circuit model based on the resonance characteristics of the impedance curve is as follows: when there is no resonance point in the impedance curve, the equivalent parasitic inductance is extracted based on the impedance slope in the high-frequency band. The impedance determines the parasitic resistance R, and the corresponding parasitic parameter circuit model is an RL circuit; when there is a resonant point in the impedance curve, the resonant frequency is used... With equivalent capacitance Relationship Extraction of Parasitic Inductance The calculation formula is: ,in Obtained from the impedance slope in the low-frequency band. Take the impedance phase as The parasitic resistance R is determined by the impedance at the resonant frequency, and the corresponding parasitic parameter circuit model is an RLC circuit. When there are n resonant points in the impedance curve, n≥2, an nth-order RLC parasitic parameter equivalent circuit model is established. The parasitic parameters are obtained by fitting the measured impedance curve. The specific steps are as follows: based on the root mean square error minimization criterion between the impedance curve of the equivalent circuit model of the frequency band of interest and the measured impedance curve, the parasitic parameters are obtained by solving the problem. The corresponding parasitic parameter circuit model is the above-mentioned nth-order RLC parasitic parameter equivalent circuit model.

5. The method for modeling and extracting parameters of distributed parasitic inductance networks in wide-bandgap inverters according to claim 1, characterized in that, In step (5), constructing different measurement circuits and extracting and solving the parasitic inductance parameters of each branch includes: for discrete devices, connecting the drain to the common node of the signal path and the common path, and connecting the source to the common node of the ground return path and the common path to form a parallel direct connection structure; by switching the connection structure of the three terminals, the total parasitic inductance combination between the drain and the source is obtained respectively. Total parasitic inductance combination between gate and drain Total parasitic inductance combination between gate and source The parasitic inductance of the drain is obtained by solving for three sets of combined quantities. Parasitic inductance of the source electrode Parasitic inductance of the gate branch .

6. The method for modeling and extracting parameters of distributed parasitic inductance networks in wide-bandgap inverters according to claim 1, characterized in that, In step (5), constructing different measurement circuits and extracting and solving the parasitic inductance parameters of each branch includes: For conventional power modules without bridge arm interconnection structures, parasitic inductance parameters of the upper bridge arm, lower bridge arm, and AC output related paths are extracted by switching the module terminal interconnection structure. Alternatively, for power modules with bridge arm interconnection structures, additional parameter measurements are performed using the terminal interconnection structure. Two-port measurements are conducted by switching different terminal interconnection topologies, causing the measured current to form different equivalent current paths within the module, and the corresponding equivalent parasitic inductances are obtained. The equivalent inductance under each topology is considered as a combination of several distributed branch parasitic inductances on that path. Multiple sets of independent interconnection topologies are selected, and a set of constraint equations for multiple unknown branch inductances is established. The distributed parasitic inductance parameters of the upper branch, lower branch, output related interconnection branches, and DC terminal interconnection branches are obtained through algebraic solutions or constraint optimization. Subsequently, they are assembled into a distributed parasitic inductance network model according to the actual current paths.

7. The method for modeling and extracting parameters of distributed parasitic inductance networks in wide-bandgap inverters according to claim 1, characterized in that, In step (5), constructing different measurement circuits and extracting and solving the parasitic inductance parameters of each branch includes: For the extraction of parasitic parameters on the DC bus side, the measurement point is the terminal on the DC bus side connected to the power module. The measurement fixture used does not need to be redesigned, as it is the fixture for measuring the parasitic inductance of the upper and lower bridge arms of the power module.

8. The method for modeling and extracting parameters of distributed parasitic inductance networks in wide-bandgap inverters according to claim 1, characterized in that, In step (6), the method of establishing a distributed parasitic parameter network model for predicting the dynamic behavior of the inverter specifically includes: after obtaining the distributed parasitic inductance network model of the overall power circuit of the wide-bandgap inverter, combining it with the parasitic capacitance parameters of the power devices or power modules to establish a distributed parasitic parameter network model that can simultaneously reflect the distribution of inductance and capacitance; based on this model, through circuit simulation or resonance characteristic calculation, predicting the voltage overshoot, ringing frequency and related dynamic behavior during the switching transient process of the inverter.

9. A system for modeling and extracting parameters of a wide-bandgap inverter distributed parasitic inductor network for implementing the method of any one of claims 1-8, characterized in that, include: Two-port measurement equipment is used to perform two-port measurements and acquire S-parameter data under different interconnect topologies; The matching measuring fixture is manufactured based on the principles of minimizing parasitic additions to common loops and minimizing mutual inductance coupling, and is used to connect the object to be measured; The data processing and parameter solving unit is used to convert the S-parameters into Z-parameters, extract the equivalent inductance, and solve for the parasitic inductance of the distributed branches. The model building and prediction unit is used to assemble the distributed parasitic inductance network, integrate the parasitic capacitance parameters of the power devices, and output the prediction results of the inverter's switching transient behavior. The data processing and parameter solving unit is also configured to support at least one of the following operating modes: Single-port measurement auxiliary verification mode; Parasitic parameter extraction mode based on analytical solution and least squares or constrained optimization fitting; The compensation mode can be selected based on the accuracy requirements, including ignoring coupling terms, partial compensation, or full compensation.

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